JP3339542B2 - Sampling clock cycle control method and device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video information apparatus having a sampling means for converting an analog video signal into a digital video signal, and more particularly to a personal computer (hereinafter abbreviated as PC), a workstation (hereinafter abbreviated as WS) and the like. The present invention relates to an apparatus for accurately converting an analog video signal of one pixel unit into a digital video signal.

[0002]

2. Description of the Related Art In recent years, personal computers have rapidly become widespread with the progress of graphical user interfaces, and various video information devices such as displaying video signals of the personal computer on a liquid crystal projector or the like, or printing out with a video printer. It is increasingly used to connect with.

On the other hand, an output video signal of a personal computer or the like is 1
The signal level changes in the pixel cycle, and when displaying on a matrix display device or performing signal processing by writing to a memory, a sampling clock that matches the pixel cycle is required. However, since few personal computers have this clock output terminal, it is necessary to reproduce the sampling clock by multiplying the horizontal synchronizing signal by a PLL or the like on the video information device side.

[0004]

In order to reproduce a sampling clock by multiplying a horizontal synchronizing signal by a PLL circuit,
The multiplier must be known in advance. However, depending on the PC or WS, the period of the back porch or front and porch is different from the known value. Therefore, the sampling clock cycle reproduced based on the default number of pixels of the back porch, front porch, effective display area, etc. There is a problem that the pixel cycle of the analog video signal thus obtained is different, and one pixel cannot be sampled accurately.

On the other hand, Japanese Patent Application Laid-Open No. 1-237689 discloses a method in which a reference signal is generated in an effective display area for one line in a PC or WS, and a video signal is sampled by a reproduced sampling clock. There is disclosed a method of determining whether the total number of sampling clocks reproduced from the number is sufficient or not.

However, in this conventional technique, it is necessary to install a special program for generating a reference signal in a PC or WS, and when the PC or WS is set to operate with a specific program, the execution of the program is bothersome. Had to be interrupted, so that there was a problem in terms of usability such as the necessity of obtaining the help of an expert.

An object of the present invention is to reproduce a sampling clock for accurately sampling an analog video signal output from a PC or WS for each pixel without a special operation such as generating a reference signal in the PC or WS.

[0008]

In order to achieve the above object, means for calculating a correlation value between digital video signals sampled at different timings are provided, and the sampling timing is shifted by ± 1 pixel for each of a plurality of positions on the screen. To obtain a correlation value data string. The local sampling points at a plurality of points on the screen are obtained from the correlation value data sequence, and the deviation between the sampling clock cycle reproduced from the displacement of the sampling points at the plurality of points on the screen and the pixel cycle of the input video signal is detected. , The number of PLL multiplications is controlled so as to eliminate the deviation. As a result, the sampling clock cycle can be automatically set to an optimum value according to the input analog video signal, and accurate sampling is realized.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an apparatus for matching sampling clock periods according to the present invention, wherein 1 is an AD converter, 2 is a memory, 3 is a comparator, and 11 to 11. 18 is a counter, 4 is a control circuit, 20 is a memory write / read signal generation circuit, 21 to 28 are counter clock generation circuits, 5 is a PLL circuit, and 6 is a delay circuit.

Referring to FIG. 1, an embodiment includes an AD converter 1 for digitally converting an analog video signal, a memory 2 for delaying digital video data (hereinafter, the delay time is one frame or more), and a data size. And counters 11 to 18 for counting the comparison result.
A control circuit 4 including a memory write / read signal generation circuit 20 and counter clock generation circuits 21 to 28; a PLL circuit 5 for reproducing a sampling clock DotCK from the horizontal synchronization signal Hsync;
It is composed of a delay circuit 6 for delaying otCK for a predetermined time, and a microcomputer 7 for controlling each of these circuit blocks.

The microcomputer 7 measures and calculates the cycle of the horizontal synchronizing signal Hsysnc and the vertical synchronizing signal Vsync of the input analog video signal, and sets a predetermined value such as a pixel cycle of the input analog video signal against the built-in ROM data. Ask. From the result, the frequency divider 50 of the PLL circuit 5 is obtained.
, And the conditions such as the center oscillation frequency of the VCO 51, and the sampling clock Dot is set based on these conditions.
CK is generated from the PLL circuit 5. After the sampling clock DotCK is delayed by the delay circuit 6,
The signal is supplied to the D converter 1 as a sampling clock and to the control circuit 4.

On the other hand, in the control circuit 4, the memory write / read signal generation circuit 20 writes desired data in the display screen to the memory 3 and reads it. The counter clock generation circuits 20 to 28 enable the counters 10 to 18 to operate only for a specific period in a desired portion of the display screen.

Next, the operation of the first embodiment will be described in detail with reference to the flowchart shown in FIG. In addition,
FIG. 2 is a flowchart showing the overall operation of the first embodiment. The operation of the first embodiment starts when the power of the video information device is turned on, when the input analog video signal is changed to an analog video signal having a different specification, or when a request from the user is received. Such as when there was.

First, the microcomputer 7 sets the delay amount of the delay circuit 6 to the basic delay amount (step 1001), and writes the video data string sampled by the AD converter 1 to the memory 2 via the control circuit 4 (step 1002). ). This data string may be, for example, video data for one line or video data for several lines or one frame. The capture area is determined by the memory write / read signal generation circuit 20.

Next, the data sequence stored in the memory 2 in the next and subsequent frames is brought into a read state (step 100).
3). Then, the delay amount of the delay circuit 6 is changed from the reference delay amount by −1 pixel to 1 pixel at regular intervals, and the output of the AD converter 1 and the read data of the memory 2 are compared by the comparator 3 and coincidence is made. The number of data obtained is counted by the counters 11 to 18, and the results of the counters 11 to 18 are taken into the microcomputer 11 (step 1004).

The range counted by the counters 11 to 18 is determined by the counter clock generation circuits 21 to 28.
In this embodiment, for example, as shown in FIG. 3, the screen is divided into eight in the horizontal direction, area 1 is a counter 11, area 2 is a counter 12, area 3 is a counter 13, area 4 is a counter 14, and area 5 is a counter 15. , Area 6 is counter 16, area 7 is counter 17, area 8 is counter 1.
8 will be described. That is, the results of comparison and accumulation for each area are obtained by the counters 11 to 18.

A while shifting the sampling timing
FIG. 5 shows an example of D-converted data. The order in the figure is
The order of sampling is that the time has elapsed from the smaller number to the larger number. The delay is the amount of deviation of the sampling timing from the reference timing of sampling "0", which is within a range of ± 1 pixel.
Here, for example, when the data of the delay amount 0 is stored in the memory 2 and the comparison operation of the data of the delay amount 0 and the data of the delay amount ± 1 pixel is performed, the result becomes as shown in FIG. (“1” if matched, “0” if mismatched). Further, in the respective sections of the order 1 to 5, 6 to 10, 11 to 15, 16 to 20, 21 to 25, 26 to 30, 31 to 35, and 36 to 40 in FIG. When the number of 1 "is accumulated, the result is as shown in FIG. In FIG. 6, the first to fifth areas are area 1, the sixth to tenth areas are area 2, the eleventh to fifteenth areas are three, and 16 to 20.
The area is area 4, 21-25 The area is area 5, 26-3
The 0th is area 6, 31-35 is the area 7, 36-
The 40th corresponds to the area 8 and the counters 11 to 11 respectively.
18 outputs. That is, the correlation value is obtained for each area, and the microcomputer 7 receives this data string. FIG. 8 shows the correlation value of each area based on FIG. 7 with the delay amount on the horizontal axis. In FIG. 8, the correlation value is normalized by the maximum value.

Returning to FIG. 2, the microcomputer 7 (FIG. 1)
The length (ie, peak width) of the peak portion of the correlation value sequence of each area is determined (step 1006), and it is determined whether or not this peak width is within an allowable range (step 100).
7). The maximum value of this allowable range corresponds to one pixel period, and the minimum value may correspond to, for example, one tenth pixel period. In principle, the maximum value must be equal to or less than one pixel period, but the minimum value may be equal to or greater than 0, and may be determined to an appropriate value in consideration of the rounding of the signal waveform. In addition,
When the sampling timing is near the center of the one-pixel cycle width of the video signal, and the video signal data at that timing is written in the memory 2 as the reference data and the above-described peak portion is obtained, the length of the peak portion may be distorted. In the case where there is no delay amount, it is equivalent to one pixel period, and the length of the peak with the delay amount 0 as the center is substantially equal in the plus direction and the minus direction of the delay amount. Conversely, after the embodiment is executed and the sampling clock cycle is matched, that is, after the state of FIG.
If the reference timing is shifted so that the length of the peak portion is equivalent to one pixel period and the length of the peak is substantially equal in the plus direction and the minus direction with the delay amount 0 as the center, the sampling timing becomes Be the best point.

Returning to FIG. 2, if the peak width is within the allowable range in step 1007, a delay amount corresponding to the center of the peak width is obtained and assigned to array CENT [j] (step 1008). Here, the peak period is set at step 10
Areas that do not satisfy the allowable range in the determination of 07 are excluded from the calculation target. When steps 1006 to 1009 are performed for each area, the center value (delay amount) in the area where the peak width is within the allowable range is obtained.

In fact, FIG. 8 shows a case where the sampling clock cycle matches the pixel cycle of the input video signal. FIGS. 9 to 12 show the case where the sampling clock cycle and the pixel cycle of the input video signal do not match. 9 shows that the sampling clock cycle is longer than the pixel cycle of the input video signal, and the total number of sampling clocks is two short of the total number of pixels per line of the input video signal. FIG. 11 shows that the total number of sampling clocks is one less than the total number of pixels per line of the input video signal, and FIG. 12 shows that the total number of sampling clocks is one more than the total number of pixels per line of the input video signal. This is a case where the total number of sampling clocks is two more than the number of pixels.

FIGS. 8 to 12 show that the excess and deficiency of the total number of sampling clocks and the change of the central value are linked.
This relationship is quantified to determine whether the total number of sampling clocks is excessive or insufficient.

Returning to FIG. 2, the difference between the center values of adjacent areas is determined (step 1011). The difference between the leftmost area (for example, area 1) and the rightmost area (for example, area 8) is calculated (step 1012). Further, as described above, the area whose peak period does not satisfy the allowable range in the determination in step 1007 is excluded from the calculation target.

FIG. 13 shows the calculation process and the result.
13 is a table based on the results of FIGS. 8 to 12. For example, 2
Looking at the part where the number is insufficient, the sign of the value of the difference becomes negative when moving from area 2 to area 4 in FIG. When moving from area 6 to area 8, the value is also negative. Other difference values are positive. The sign of the difference is two for minus and four for plus. On the other hand, when looking at an excess portion, the sign of the value of the difference is positive when moving from area 8 to area 2 in FIG. Other difference values are negative. The sign of the difference is one plus and six minus. That is, a small code indicates a change point and corresponds to the excess or deficiency of the total number of sampling clocks.

Taking this idea into account, the description of the flow of FIG. 2 will be continued. In step 1015, the sign of the difference is determined, and the number of positive signs is substituted into the variable Posi (step 1).
016), and substitute the number of negative signs for the variable nega (step 1017). However, the difference value 0 is treated as positive. If the number of negative signs is 0, the total number of sampling clocks is not excessive or insufficient, that is, it is the same, so the process is terminated. If the number of negative signs is not 0, it is determined that the total number of sampling clocks is excessive or insufficient. (Step 1018). In step 1019, the number of positive signs is compared with the number of negative signs. If the number of codes is the same, an error is output because it is impossible to determine whether the number is excessive or insufficient. This is because the total number of sampling clocks is often too large or small, so that the determination cannot be made in the eight areas of the present embodiment. The details will be described later. Here, an error output is performed to avoid complicated explanation.

If the number of codes is not the same in step 1019, the smaller number of codes is determined (step 1019).
21) Then, if the number of positive signs is large, the number of negative signs is substituted for the variable dn (step 1022). If the number of negative signs is large, a value obtained by adding the minus sign to the number of positive signs is substituted for the variable dn. (Step 1023). Finally, a value obtained by adding dn to the value N already set in the frequency divider 50 of the PLL 5 is set. As described with reference to FIG. 13, a value for correcting excess or deficiency is assigned to dn, so that the frequency at which the PLL 5 oscillates matches the pixel period of the input video signal.

In the above method, the user may be requested to display a still image or an image for adjustment with a certain pattern, but it is not necessary to install special driver software or the like on a PC or WS. It can be easily adjusted.

It is assumed that the comparator 3 agrees if the difference between the comparison inputs is within ± 1 in consideration of the quantization error. The comparator 3 may be configured using, for example, full adders 30 and 31, as shown in FIG. FIG. 4 shows a case of 4 bits as an example, but it goes without saying that if a full adder is added, it is possible to cope with a larger arbitrary number of bits.

As described above, the sampling clock cycle can be automatically set to the optimum value according to the input analog video signal, and accurate sampling can be realized.

FIG. 14 is a block diagram showing a second embodiment of the sampling clock cycle matching method and apparatus according to the present invention, in which parts corresponding to those in FIG.

The feature of this embodiment is that the number of counters is reduced and the circuit configuration is simplified. As a result, the control circuit 104 is simplified, and the counter clock generation circuit becomes one system.

In order to obtain the correlation values of a plurality of areas in this configuration, the microcomputer 107 uses the counter clock generation circuit 12
You only need to set one clock generation period individually,
The rest is the same as in the first embodiment.

In this embodiment, since the correlation period can be arbitrarily selected, for example, even if there is an error output in step 1020 of FIG. It can easily cope with a large shortage. Further, the plurality of correlation sections may overlap each other.

As described above, the sampling clock cycle can be automatically set to the optimum value according to the input analog video signal with a simple configuration, and accurate sampling can be realized.

FIG. 15 is a block diagram showing a third embodiment of the sampling clock cycle matching method and apparatus according to the present invention, in which parts corresponding to those in FIG.

The feature of this embodiment is that the functions of the comparator and the counter are executed by the microcomputer 207, and the circuit configuration is simplified by eliminating the comparator and the counter circuit. Accordingly, the control circuit 104 is simplified, and only the memory write / read signal generation circuit 120 is used.

The digital video signal data that has been A / D converted by the A / D converter 1 is written into the memory 103 under the control of the memory write / read signal generation circuit.
Reads the above data based on the command from
07. The microcomputer 207 takes in the digital video signal in the above manner while changing the delay amount of the delay circuit 6. The captured data has, for example, the values shown in FIG. Of the data, the data of delay amount 0 is used as reference data,
FIG. 6 shows a comparison operation performed between the data sequence of the delay amount 0 and the data of the delay amount ± 1 pixel. This comparison operation corresponds to the operation of the comparator 3 in FIG. The results of this comparison operation are described in the order 1-5, 6-10, 11-15, 16
20th, 21st to 25th, 26th to 30th, 31st to 31st
FIG. 7 shows the result of accumulating the number of "1" in each of the 35th and 36th to 40th sections. FIG. 7 is a graph of FIG. 8 to FIG. Subsequent operations are the same as in the first embodiment, and description thereof will be omitted.

In this embodiment as well, the correlation period can be arbitrarily selected. For example, even if there is an error output in step 1020 in FIG. It can easily cope with a large shortage. Further, the plurality of correlation sections may overlap each other.

As described above, the sampling clock cycle can be automatically set to an optimum value according to the input analog video signal with a simple configuration, and accurate sampling can be realized.

FIG. 16 is a block diagram showing a fourth embodiment of the sampling clock cycle matching method and device according to the present invention, in which parts corresponding to those in FIG.

The feature of this embodiment resides in that the AD-converted video data is converted into serial-parallel data and taken in. FIG. 16 shows an example in which the number of parallel operations is two. In this case, even if the pixel period of the input video signal is short (that is, the frequency of the input video signal is high), these memories 202 and 302 that take in video data are used.
The operating frequency of such a circuit becomes 1/2 of the frequency of the input video signal, and the circuit can be operated stably. Also,
As in the third embodiment, hardware such as a comparator and a counter is omitted, so that the number of components is small and the cost can be reduced. Here, the number of parallel operations is described as two, but the present invention is not limited to this, and the number of parallel operations is two.
The above values may be used. Further, a data latch circuit (that is, a 1-bit memory) may be used as a memory, and higher-speed video signals can be handled. Of course, since data is taken in bit by bit, a plurality of frames are required to take in the data with the specific delay amount in FIG.

From the memories 202 and 302 to the microcomputer 307
Are serial-to-parallel converted, so they are parallel-serial again. Thereby, data equivalent to FIG. 5 can be generated. Subsequent operations are the same as in the third embodiment, and a description thereof will be omitted.

As described above, even if the input video signal frequency becomes high, the sampling clock cycle can be automatically set to an optimum value in accordance with the input analog video signal with a small hardware configuration, thereby realizing accurate sampling. it can.

In this embodiment, the correlation period can be arbitrarily selected. Therefore, for example, even if there is an error output in step 1020 of FIG. Can easily cope with a large value of the excess or deficiency. Further, the plurality of correlation sections may overlap each other. As described above, the sampling clock cycle can be automatically set to the optimum value according to the input analog video signal with a simple configuration, and accurate sampling can be realized.

FIGS. 17 to 21 show a fifth embodiment of the sampling clock cycle matching method and apparatus according to the present invention, which differs from the first embodiment in the combination of data to be compared and calculated. In the first to fourth embodiments, the data of the delay amount 0 shown in FIG. 5 is compared with the data of the delay amount ± 1 pixel, but in the present embodiment, the data of the delay amount is compared and calculated at a constant interval. For example, delay-1 data and delay-
A comparison operation is performed in such a manner that data of 0.85, data of delay amount -0.95 and data of delay amount -0.8..., And the result is as shown in FIG. Here, the result of the comparison between the data of the delay amount -1 and the delay amount -0.85 is shown in FIG.
The result of the comparison between the data of the delay amount -0.95 and the data of the delay amount -0.8 is shown in FIG.
Become. However, the above calculation naturally requires data having a delay amount of 1 or more. Although not particularly shown because it has been described with reference to FIG. 5, it is added that data having a delay amount of 1 or more also exists.

The results of the above comparison operation are described in the order of 1st to 5th, 6th to 6th.
10th, 11th to 15th, 16th to 20th, 21st to 2nd
Fifth, 26-30, 31-35, 36-40
When the number of “1” s is accumulated in each of the third sections, FIG.
It looks like 3. FIGS. 17 to 21 are graphs of FIG.
Becomes

Note that the circuit configuration for realizing the above function may be any of the configurations shown in FIGS. 1, 14, 15, and 16. If the delay amount of the delay circuit 6 is set so that the delay amounts can be compared at regular intervals. Good.

Further, FIGS. 17 to 21 differ from the first embodiment only in that the center between the valleys of the correlation values is set as the center value. Since sampling is performed at regular intervals, if there is a change point in the video signal during the sampling interval, the comparison result will be inconsistent, and the correlation value will be low. Conversely, since the valley portion corresponds to the signal change point, the center between the valley and the valley is a point where the sampling timing is exactly matched. Therefore, after the present embodiment is executed and the sampling clock period is matched, that is, after the state of FIG. 17 is reached, if the delay amount is set at the center between the valleys as described above, the sampling timing becomes the optimal sampling point. become.

The processing after obtaining the median value is the same as that in the first embodiment, and a detailed description thereof will be omitted. Although it is necessary to detect a valley in order to find the median, there are some valleys that are not completely valleys, such as area 3 in FIG. In this case, it is determined that the correlation value is lower than the peak value, and the valley is determined. In addition, for example, when there are a plurality of locations that can be determined to be valleys and a plurality of medians can exist as in area 3 in FIG. 18, the one with the smaller delay amount is selected.

The processing after the median is obtained is the same as that of the first embodiment, so that the detailed description will be omitted.

As described above, the sampling clock cycle can be automatically set to the optimum value according to the input analog video signal, and accurate sampling can be realized.

FIG. 24 is a block diagram showing a sixth embodiment of the sampling clock cycle matching method and apparatus according to the present invention, in which parts corresponding to those in FIG.

FIG. 24 compares two data obtained by shifting the delay amount by a fixed amount by using two AD converters, and has a feature that no memory is required for obtaining a correlation value.

24, a sampling clock delayed from the sampling clock of the AD converter 1 by the fixed delay amount dt of the delay circuit 106 is input, and the outputs of the AD converters 1 and 101 are compared. Input to the container 3. The control circuit 404 generates a count control signal to control the count period of the counters 11 to 18.

The whole operation may use either the method based on FIGS. 8 to 12 of the first embodiment or the method based on FIGS. 17 to 21 of the fifth embodiment. In the former case, the delay circuit 6
(Or delay circuit 106) is set to a reference value,
The delay circuit 106 (or the delay circuit 6) is set at 1
While increasing or decreasing by the number of pixels, the correlation value of each area (counter 11
-18) and then processed in the same manner as in the first embodiment. In the latter case, the delay amount between the delay circuit 6 and the delay circuit 106 is shifted by a fixed amount, and the delay amount between the delay circuit 6 and the delay circuit 106 is increased or decreased by one pixel while maintaining the fixed delay amount. The values (outputs of the counters 11 to 18) may be obtained and processed in the same manner as in the fifth embodiment. The details of each process have been described in the first embodiment and the fifth embodiment, and a description thereof will be omitted.

As described above, the sampling clock cycle can be automatically set to the optimum value according to the input analog video signal, and accurate sampling can be realized. It should be added that the above functions can be realized also with the configuration of FIG. 25. The processing up to the comparator 3 may be the same as that of the sixth embodiment, and the processing after the comparison result is the same as that of the second embodiment (FIG. 14). The details may be omitted since they may be the same.

FIG. 26 is a block diagram showing a seventh embodiment of the sampling clock cycle matching method and apparatus according to the present invention, in which parts corresponding to those in FIG. The overall operation of this embodiment is the same as that of the sixth embodiment, and is realized by using a sample-and-hold circuit instead of the AD converter.

FIG. 26 shows a comparison between data obtained by shifting the delay amount by a fixed amount using two sample-hold circuits (hereinafter referred to as S / H circuits). A feature that does not require a memory when obtaining a correlation value is shown. There is. The comparison input of the comparator 103 is an analog signal, and the output is a digital output of "1" when the comparison result matches, and "0" when the comparison result does not match.

The sampling clock delayed by the fixed delay amount dt of the delay circuit 106 from the dot clock of the S / H circuit 60 is input to the S / H circuit 106 of FIG. The output is input to the comparator 103. The control circuit 404 generates a count control signal to control the count period of the counters 11 to 18.

The whole operation may use either the method based on FIGS. 8 to 12 of the first embodiment or the method based on FIGS. 17 to 21 of the fifth embodiment, as described in the sixth embodiment. The description may be omitted because it may be the same as described above. It should be added that the above function can also be realized by the circuit configuration of FIG.
The processing after the comparator 103 is the same as in the sixth embodiment, and the detailed description is omitted.

Incidentally, FIGS. 1, 14 to 16, and 24
27, the output of the PLL circuit 5 is delayed by the delay circuit 6 or the delay circuit 106. However, the input horizontal synchronization signal Hsync is delayed by the delay circuit 6 or the delay circuit 106. Therefore, the sampling clock DotCK may be supplied to the PLL circuit 5 to generate the sampling clock DotCK. This is because if the frequency of the output signal of the PLL circuit 5 is high, the signal transfer becomes the ECL level and the general-purpose TTL
This is because a level-dependent delay circuit cannot be used, and an equivalent effect can be obtained by delaying the horizontal synchronization signal Hsync. However, since the delay of the horizontal synchronization signal Hsync changes the input signal of the PLL circuit 5, after changing the delay amount of the horizontal synchronization signal Hsync,
It is necessary to wait for the start of various processes until the output signal of the PLL circuit 5 is settled.

[0062]

As described above, according to the present invention,
The sampling clock cycle can be automatically set to an optimum value according to the input analog video signal, and accurate sampling can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment shown in FIG.

FIG. 3 is a diagram showing a correlation operation section (area) of the first embodiment shown in FIG. 1;

FIG. 4 is a block diagram showing a specific example of a comparator 3 of the first embodiment shown in FIG.

FIG. 5 is a diagram showing a specific example of video data sampled while shifting the sampling timing in the first embodiment shown in FIG. 1;

FIG. 6 is a diagram showing a specific example of a comparison operation result of the sampled video data shown in FIG. 5 in the first embodiment.

FIG. 7 is a diagram showing a specific example of the result obtained by cumulatively calculating the comparison calculation results of FIG. 6 for each area shown in FIG. 3 in the first embodiment.

FIG. 8 is a graph of FIG. 7 in a case where the total number of sampling clocks in the first embodiment is equal to the number of pixels per line of the input video signal.

FIG. 9 is a graph of FIG. 7 in the case where the total number of sampling clocks is two short of the number of pixels per line of the input video signal in the first embodiment.

FIG. 10 shows that in the first embodiment, the total number of sampling clocks is one more than the number of pixels per line of the input video signal.
FIG. 8 is a diagram in which FIG.

FIG. 11 shows a case where the total number of sampling clocks in the first embodiment is one more than the number of pixels per line of the input video signal.
It is the figure which made FIG. 7 in the case of an excessive number into a graph.

FIG. 12 shows a case where the total number of sampling clocks in the first embodiment is two times smaller than the number of pixels per line of the input video signal.
It is the figure which made FIG. 7 in the case of an excessive number into a graph.

13 is a diagram showing a concept of detecting the number of pixels based on the results of FIGS. 8 to 12. FIG.

FIG. 14 is a block diagram showing a second embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 15 is a block diagram showing a third embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 16 is a block diagram showing a fourth embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 17 is a graph of FIG. 23 in the case where the total number of sampling clocks in the fifth embodiment matches the number of pixels per line of the input video signal.

FIG. 18 shows that the total number of sampling clocks in the fifth embodiment is two times smaller than the number of pixels per line of the input video signal.
FIG. 24 is a graph of FIG. 23 in a case where the number is insufficient.

FIG. 19 shows that in the fifth embodiment, the total number of sampling clocks is one more than the number of pixels per line of the input video signal.
FIG. 24 is a graph of FIG. 23 in a case where the number is insufficient.

FIG. 20 shows that the total number of sampling clocks is one more than the number of pixels per line of the input video signal in the fifth embodiment.
FIG. 24 is a graph of FIG. 23 in the case of excess.

FIG. 21 shows a case where the total number of sampling clocks in the fifth embodiment is two times smaller than the number of pixels per line of the input video signal.
FIG. 24 is a graph of FIG. 23 in the case of excess.

FIG. 22 is a diagram showing a specific example of a comparison operation result of sampling video data in the fifth embodiment.

FIG. 23 is a diagram showing a specific example of the result obtained by cumulatively calculating the comparison calculation results of FIG. 22 for each area shown in FIG. 3 in the fifth embodiment.

FIG. 24 is a block diagram showing a sixth embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 25 is a block diagram showing another configuration of the sixth embodiment of the sampling clock cycle matching method and device according to the present invention.

FIG. 26 is a block diagram showing a seventh embodiment of a sampling clock cycle matching method and device according to the present invention.

FIG. 27 is a block diagram showing another configuration of the seventh embodiment of the sampling clock cycle matching method and device according to the present invention.

[Explanation of symbols]

1,101: AD converter, 2, 102, 202, 302: memory, 3,103: comparator, 4, 104, 204, 304, 404: control circuit, 5: PLL circuit, 6, 106: delay circuit, 7, 107, 207, 307 microcomputer, 11-18 counter, 20, 120, 220 memory write / read signal generation circuit, 50 frequency divider, 51 VCO 21-28, 121 counter clock generation circuit , 30, 31 ... full adder, 60, 106 ... sample and hold circuit, 409, 410, 411 ... memory.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazutaka Naka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref. Hitachi, Ltd. Visual Information Media Division (56) References JP-A-5-249942 (JP, A) JP-A-5-199481 (JP, A) JP-A-9-149291 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-5/42 H04N 5 / 14,5 / 66

Claims (4)

(57) [Claims] 1. A method of controlling a sampling clock cycle in a video information device having a sampling means for converting an analog video signal into a digital video signal, wherein the sampling means sets first, second,... .., The n-th digital video signal data stream is generated by sampling the analog video signal at the n sampling timings, and a first digital video signal data stream is generated. The correlation value with the i-th digital video signal data sequence (where i = 1, 2,..., N) is separately calculated for each correlation operation section obtained by dividing the screen horizontally into m pieces (m is 2 or more). And C1 (i), C2
(I),..., Cm (i), and a data sequence C1 (1), C1 (2),.
, C1 (n); C2 (1), C2 (2), ..., C2
(N) Cm (1), Cm (2),..., Cm (n) are generated, and the pixel cycle of the analog video signal and the sampling clock cycle of the sampling means are calculated from the m correlation value data strings. A method of controlling a sampling clock cycle, characterized by detecting a shift of the sampling clock and controlling a sampling clock cycle of the sampling means so as to eliminate the shift. 2. An image information apparatus having sampling means for converting an analog video signal into a digital video signal, wherein said sampling means has first, second,..., N-th sampling timings, The video signal is sampled at n sampling timings to generate first, second,..., N-th digital video signal data sequences, and the first digital video signal data sequence and the i-th digital video signal data Correlation values with columns (where i = 1, 2,..., N) are separately generated in each correlation operation section obtained by dividing the screen horizontally into m (m is 2 or more), and C1 (i ), C2
(I),..., Cm (i), and a data sequence C1 (1), C1 (2),.
, C1 (n); C2 (1), C2 (2), ..., C2
(N) Cm (1), Cm (2),..., Cm (n) are generated, and the pixel cycle of the analog video signal and the sampling clock cycle of the sampling means are calculated from the m correlation value data strings. The video information device detects a shift of the sampling means and controls a sampling clock cycle of the sampling means so as to eliminate the shift. 3. A method of controlling a sampling clock cycle in a video information device having a sampling means for converting an analog video signal into a digital video signal, wherein the sampling means comprises first, second,..., N-th ,.
(The k 1 or more integer) the n + k has a sampling timing of the first sampling the analog video signal at n + k-number of the sampling timing, the second, ..., the n, ...
, Generate an ( n + k ) th digital video signal data sequence, and generate an i-th digital video signal data sequence (where i = 1,
,..., N) and the j-th (j = i + k) digital video signal data sequence are represented by m (m
, C2 (i), C2 (i),..., Cm (i) are generated separately in each of the correlation calculation sections divided into 2), and m correlation value data strings C1 (1), C1 (2), ...
C1 (n); C2 (1), C2 (2),..., C2
(N) Cm (1), Cm (2),..., Cm (n) are generated, and the pixel cycle of the analog video signal and the sampling clock cycle of the sampling means are calculated from the m correlation value data strings. A method of controlling a sampling clock cycle, characterized by detecting a shift of the sampling clock and controlling a sampling clock cycle of the sampling means so as to eliminate the shift. 4. A video information apparatus having a sampling means for converting an analog video signal into a digital video signal, wherein the sampling means comprises first, second,..., N-th ,.
(The k 1 or more integer) the n + k has a sampling timing of the first sampling the analog video signal at n + k-number of the sampling timing, the second, ..., the n, ...
, Generate an ( n + k ) th digital video signal data sequence, and generate an i-th digital video signal data sequence (where i = 1,
,..., N) and the j-th (j = i + k) digital video signal data sequence are represented by m (m
, C2 (i), C2 (i),..., Cm (i) are generated separately in each of the correlation calculation sections divided into 2), and m correlation value data strings C1 (1), C1 (2), ...
C1 (n); C2 (1), C2 (2),..., C2
(N) Cm (1), Cm (2),..., Cm (n) are generated, and the pixel cycle of the analog video signal and the sampling clock cycle of the sampling means are calculated from the m correlation value data strings. The video information device detects a shift of the sampling means and controls a sampling clock cycle of the sampling means so as to eliminate the shift.