JP2003076731A - 共通のマッピングファイルを使用してシステムボードの各接続部間の正しいピン割当てを確実にする方法 - Google Patents

共通のマッピングファイルを使用してシステムボードの各接続部間の正しいピン割当てを確実にする方法

Info

Publication number
JP2003076731A
JP2003076731A JP2002213327A JP2002213327A JP2003076731A JP 2003076731 A JP2003076731 A JP 2003076731A JP 2002213327 A JP2002213327 A JP 2002213327A JP 2002213327 A JP2002213327 A JP 2002213327A JP 2003076731 A JP2003076731 A JP 2003076731A
Authority
JP
Japan
Prior art keywords
design
circuit board
circuit boards
printed circuit
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002213327A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003076731A5 (https=
Inventor
Michael John Erickson
マイケル・ジョン・エリクソン
Paul J Mantey
ポール・ジョン・マンティ
John S Atkinson
ジョン・エス・アトキンソン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2003076731A publication Critical patent/JP2003076731A/ja
Publication of JP2003076731A5 publication Critical patent/JP2003076731A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
JP2002213327A 2001-07-24 2002-07-23 共通のマッピングファイルを使用してシステムボードの各接続部間の正しいピン割当てを確実にする方法 Pending JP2003076731A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/911997 2001-07-24
US09/911,997 US6629307B2 (en) 2001-07-24 2001-07-24 Method for ensuring correct pin assignments between system board connections using common mapping files

Publications (2)

Publication Number Publication Date
JP2003076731A true JP2003076731A (ja) 2003-03-14
JP2003076731A5 JP2003076731A5 (https=) 2005-04-28

Family

ID=25431238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002213327A Pending JP2003076731A (ja) 2001-07-24 2002-07-23 共通のマッピングファイルを使用してシステムボードの各接続部間の正しいピン割当てを確実にする方法

Country Status (3)

Country Link
US (2) US6629307B2 (https=)
JP (1) JP2003076731A (https=)
DE (1) DE10230135B4 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008047644A1 (en) * 2006-10-11 2008-04-24 Zuken Inc. Electric information processing method for cad system, device thereof, program, and computer-readable storage medium
US7899494B2 (en) 2005-04-27 2011-03-01 Lg Electronics Inc. Mobile communications terminal using multi-functional socket and method thereof

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7039892B2 (en) * 2001-07-24 2006-05-02 Hewlett-Packard Development Company, L.P. Systems and methods for ensuring correct connectivity between circuit designs
US20070061764A1 (en) * 2005-09-15 2007-03-15 Interntional Business Machines Corporation Keyword-based connectivity verification
EP1930825A3 (en) * 2006-12-04 2011-06-29 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
EP1930830A3 (en) * 2006-12-04 2011-06-29 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method
US7904863B2 (en) * 2006-12-04 2011-03-08 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US8176457B2 (en) * 2006-12-04 2012-05-08 Fujitsu Limited Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to PLD
CN101196945B (zh) * 2006-12-04 2010-06-02 富士通株式会社 电路设计支持装置及方法、印刷电路板制造方法
US8255844B2 (en) * 2006-12-04 2012-08-28 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
DE102007026942B4 (de) * 2007-06-12 2010-04-15 Rohde & Schwarz Gmbh & Co. Kg Verfahren und Vorrichtung zum Entwerfen von Kabelbäumen
US8438524B1 (en) * 2009-12-30 2013-05-07 Cadence Design Systems, Inc. Hierarchical editing of printed circuit board pin assignment
CN102063554B (zh) * 2011-01-17 2012-10-03 浪新微电子系统（上海）有限公司 Pcb设计平台
US8261226B1 (en) * 2011-07-20 2012-09-04 International Business Machines Corporation Network flow based module bottom surface metal pin assignment
JP5989655B2 (ja) * 2011-10-20 2016-09-07 株式会社図研 マルチボード設計装置、マルチボード設計方法、プログラムおよびコンピューター読み取り可能な記録媒体
JP2014032584A (ja) * 2012-08-06 2014-02-20 Fujitsu Ltd 部品置換のための情報処理方法及び装置
CN103745050B (zh) * 2013-12-27 2016-09-14 北京亚科鸿禹电子有限公司 一种管脚映射方法和系统
CN104021258B (zh) * 2014-06-24 2017-08-25 浪潮电子信息产业股份有限公司 一种抑制平面谐振的pcb设计方法
DE102020121614B4 (de) * 2020-08-18 2022-05-25 Lisa Dräxlmaier GmbH Elektrische Verbindungsanordnung zum Anschließen von frei konfigurierbaren elektrischen Komponenten in einem Fahrzeug
CN121580939A (zh) * 2026-01-21 2026-02-27 巨霖科技(上海)有限公司 多板电路仿真方法、系统、计算机设备及存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3514264A1 (de) * 1985-04-19 1986-10-23 Wilhelm Sedlbauer GmbH Fabrik für Feinmechanik und Elektronik, 8000 München Vielfachschaltelement zum verbinden einer mehrzahl von mehrfachbussen
US4613941A (en) * 1985-07-02 1986-09-23 The United States Of America As Represented By The Secretary Of The Army Routing method in computer aided customization of a two level automated universal array
JPH02245840A (ja) * 1989-03-20 1990-10-01 Fujitsu Ltd 記憶装置
US5502621A (en) * 1994-03-31 1996-03-26 Hewlett-Packard Company Mirrored pin assignment for two sided multi-chip layout
US5841664A (en) * 1996-03-12 1998-11-24 Avant| Corporation Method for optimizing track assignment in a grid-based channel router
GB2318664B (en) * 1996-10-28 2000-08-23 Altera Corp Embedded logic analyzer for a programmable logic device
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
JP3654758B2 (ja) * 1997-12-02 2005-06-02 富士通株式会社 自動配線接続装置
US7039892B2 (en) * 2001-07-24 2006-05-02 Hewlett-Packard Development Company, L.P. Systems and methods for ensuring correct connectivity between circuit designs

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7899494B2 (en) 2005-04-27 2011-03-01 Lg Electronics Inc. Mobile communications terminal using multi-functional socket and method thereof
WO2008047644A1 (en) * 2006-10-11 2008-04-24 Zuken Inc. Electric information processing method for cad system, device thereof, program, and computer-readable storage medium
JPWO2008047644A1 (ja) * 2006-10-11 2010-02-25 株式会社図研 Ｃａｄシステムにおける電気情報処理方法、その装置、プログラムおよびコンピューター読み取り可能な記憶媒体
US8185849B2 (en) 2006-10-11 2012-05-22 Zuken Inc. Electric information processing method in CAD system, device thereof, program, and computer readable storage medium
JP5090362B2 (ja) * 2006-10-11 2012-12-05 株式会社図研 Ｃａｄシステムにおける電気情報処理装置、ｃａｄシステムにおける電気情報処理方法およびプログラム
US8650528B2 (en) 2006-10-11 2014-02-11 Zuken Inc. Electric information processing method in CAD system, device thereof, program, and computer-readable storage medium

Also Published As

Publication number Publication date
US20030023944A1 (en) 2003-01-30
US6898775B2 (en) 2005-05-24
US6629307B2 (en) 2003-09-30
DE10230135A1 (de) 2003-04-03
DE10230135B4 (de) 2006-04-20
US20040031012A1 (en) 2004-02-12

Similar Documents

Publication Publication Date Title
JP2003076731A (ja) 共通のマッピングファイルを使用してシステムボードの各接続部間の正しいピン割当てを確実にする方法
US7039892B2 (en) Systems and methods for ensuring correct connectivity between circuit designs
JP3891599B2 (ja) 集積回路レイアウト内への標準セルの自動挿入装置
EP0508075B1 (en) Automatic logic model generation from schematic data base
US7194726B2 (en) Method for automatically decomposing dynamic system models into submodels
JPH10232891A (ja) 電子設計自動化用ワークグループコンピューティング
JP2007527063A (ja) 構成データを生成するための方法及び装置
US20110246975A1 (en) Control architecture and process for porting application software for equipment on board an aircraft to a consumer standard computer hardware unit
US20020066068A1 (en) Printed circuit board design, testing, and manufacturing process
CN120805811A (zh) 一种异质集成芯粒系统规范化设计方法
US8782587B2 (en) Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
KR19990023204A (ko) 다수의 집적 회로의 배선 방법 및 시스템
CN117669460A (zh) 一种集成电路的交互文件生成方法以及装置
US8122416B2 (en) Arrangement verification apparatus
JP2872216B1 (ja) マクロの設計方法
KR102870245B1 (ko) 도시철도용 전장제어기기를 위한 소프트웨어 모델링 장치 및 이를 이용한 방법
JP2962292B2 (ja) レイアウト設計を考慮したｌｓｉ論理設計支援システム
JPH11184908A (ja) データベースを用いたプリント基板設計方法
JPH08153129A (ja) 再利用容易化装置
JP2003076739A (ja) 論理検証装置及び方法並びにプログラム
CN118917105A (zh) 一种工艺设计套件的验证方法及装置
CN118673847A (zh) 一种用于Post-Mask ECO的定制Spare Cell方法
CN121706694A (zh) 基于规则驱动的高速数字系统电路图设计方法及系统
JPH01232476A (ja) Ｃａｄ装置における論理データ管理方法
JPH10340283A (ja) Ｌｓｉ設計検証方法及び装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040616

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040616

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070123

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070703