JP2003076319A - Method for driving plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving method of a plasma display panel capable of displaying a high-quality picture having many number of gradation without making discharge cells perform erroneous discharge. SOLUTION: In this driving method, pulse widths of scanning pulses and pixel data pulses are made so that the earlier impression times of pulses of them in respective address processes of each sub-field are, the narrower pulse widths of them become.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method of driving a plasma display panel.

[0002]

2. Description of the Related Art In recent years, a thin type display device has been required in accordance with a large screen of a display device, and various thin type display devices have been put into practical use. The AC discharge type plasma display panel is drawing attention as one of the thin display devices. FIG. 1 is a diagram showing a schematic configuration of a plasma display device including the plasma display panel and a driving device for driving the plasma display panel.

In FIG. 1, a plasma display panel is shown.
The PDP 10 as a memory cell has m columns as data electrodes.
Electrode D₁~ D_mAnd are arranged to intersect each of these column electrodes.
N row electrodes X each₁~ X_nAnd row electrode Y₁~ Y_nTo
I have it. These row electrodes X ₁~ X_nAnd row electrode Y₁~ Y_n
Is a pair of row electrodes X_i(1 ≦ i ≦ n) and Y_iP for (1 ≤ i ≤ n)
It is responsible for the display line in DP. These column electrodes D
And the row electrodes X and Y are the discharge space filled with the discharge gas.
Are placed opposite each other across the
Discharge that plays a role in the pixel at the intersection of each row electrode pair and column electrode
It has a structure in which cells are formed. Discharge cell, discharge
Since it is an element that emits light by "lighting" and "off"
It can take only two states, "state", that is, the lowest brightness
Degree (light off state) and maximum brightness (lighting state) for two gradations
Express only.

The driving device 100 has a PDP 10 having such discharge cells as display cells for pixels,
In order to realize halftone luminance display corresponding to the input video signal, gradation driving using the subfield method is performed. In the sub-field method, the display period of one field is divided into a plurality of sub-fields, and each sub-field is assigned the number of times of light emission implementation corresponding to the weighting of the sub-field. For example, as shown in FIG. 2, the display period of one field is four subfields SF1 to S1.
It is divided into F4, and the number of times of performing light emission of SF1: 1 SF2: 2 SF3: 4 SF4: 8 is assigned to each.

Here, the input video signal is converted into 4-bit pixel data corresponding to each pixel. Each of the first to fourth bits of pixel data is a subfield SF1 to S1.
It corresponds to F4, respectively. In gradation driving by the subfield method, light emission is performed as described above in the subfield corresponding to the bit digit according to the logical level of each bit of the pixel data.

FIG. 3 is a diagram showing various driving pulses applied to the row electrode pairs and column electrodes of the PDP 10 by the driving device 100 in each subfield in order to perform the light emission driving as described above, and their application timings. is there. First, in the simultaneous reset process Rc shown in FIG.
0 indicates a positive reset pulse RP _X to the row electrodes X ₁ to
X _n, applies a negative reset pulse RP _Y to the row electrodes Y ₁ to Y _n. In response to the application of the reset pulses RP _x and RP _Y , all discharge cells of the PDP 10 are reset and discharged, and a predetermined amount of wall charge is uniformly formed in each discharge cell. As a result, all the discharge cells in the PDP 10 are initialized to the "lighting discharge cell state".

Next, in the address process Wc, the driving device
100 is obtained from the 4-bit pixel data as described above.
1 bit corresponding to the subfield of
Pixel data having a pulse voltage according to the logic level of
Generate a pulse. For example, in subfield SF1
Is the driving device 100 of the first bit of the pixel data.
Pixel data pulse having pulse voltage according to logic level
Generate At this time, the driving device 100 is
If the logic level of the eye is "1", the high voltage is "0".
Pixel with a low voltage (0 volt) pulse voltage
Generate a data pulse. Then, the drive device 100 is
This pixel data pulse is sequentially displayed in columns for each display line.
Electrode D₁~ D_mApply to. That is, as shown in FIG.
No, the driving device 100 is m in number corresponding to the first display line.
Pixel data pulse group DP composed of pixel data pulses of₁
The column electrode D₁~ D_mTo the second display line.
Pixel data pulse consisting of m pixel data pulses
Group DP₂The column electrode D₁~ D _mApply to. And so on
The driving device 100 corresponds to each of the 3rd to nth display lines.
Pixel data pulse group DP₃~ DP_nColumn electrode D₁
~ D_mApply to. Further, the drive device 100 is
The negative electrode is synchronized with the application timing of the elementary data pulse group DP.
Scan pulse SP is generated, and as shown in FIG.
Row electrode Y₁~ Y_nThe voltage is sequentially applied to. At this time, the scan pattern
The display line to which the loose SP is applied and the high-voltage pixel data
Discharge cell at the intersection with the column electrode to which the pulse is applied
Discharge (selective erase discharge) occurs in the
The wall charges that had been removed disappear. As a result,
Initially in the state of "lighting discharge cell state" in the step Rc
The discharged discharge cell changes to the "off discharge cell state"
To do. On the other hand, a low voltage is applied while the scan pulse SP is applied.
Select the above for the discharge cells to which the pixel data pulse of
Erase discharge does not occur, and at the above simultaneous reset process Rc
The initialized state, that is, the "lighted discharge cell state" is maintained.
Be done.

That is, by executing the address process Wc, each discharge cell in the PDP 10 is in one of the "lighted discharge cell state" and the "off discharge cell state" according to the pixel data corresponding to the input video signal. Is set to. Next, in the light emission sustaining process Ic, the driving apparatus 100 causes the sustaining pulse I having the positive polarity as shown in FIG.
P _X and IP _Y, is applied to only repeat the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n the number assigned to each sub-field as described above. At this time, the discharge cells in which the wall charges remain in the discharge space, that is, the "lighting discharge cell state"
Only the sustaining cells IP _X and I
Every time P _Y is applied, discharge (sustain discharge) occurs. That is,
Only the discharge cells in which the selective erasing discharge has not occurred in the addressing process Wc repeat the light emission associated with the sustain discharge for the number of times assigned to each subfield as described above, and maintain the light emitting state. .

Then, in the erase step E, the drive unit 10
0, the erase pulse EP as shown in FIG. 3 is applied to the row electrodes Y _{1 to} Y _n.
Simultaneously applied to. By applying the erase pulse EP,
Erase discharge is generated in all the discharge cells of the PDP 10, and the wall charges remaining in the discharge cells disappear. The simultaneous reset process Rc, address process Wc, light emission sustaining process I
A series of operations of c and erase step E are executed in each of the subfields SF1 to SF4 shown in FIG.
According to such driving, light emission due to the sustain discharge is generated the number of times corresponding to the luminance level of the input video signal during the display period of one field, and the intermediate luminance corresponding to the number of times of light emission is visually perceived. According to the grayscale driving based on the four subfields SF1 to SF4 as shown in FIG. 2, the intermediate brightness of "0" to "15" is expressed in 16 steps (1
6 gradations).

Here, if the number of subfields to be divided is increased, the number of gray levels that can be expressed also increases, and a higher quality display image can be obtained. Therefore, the pulse widths of the scan pulse SP and the pixel data pulse group DP shown in FIG. 3 are narrowed to shorten the time spent in the address process Wc, and the number of subfields is increased by utilizing the shortened time.

However, if the pulse widths of the scanning pulse SP and the pixel data pulse group DP are narrowed, the selective discharge becomes unstable as described above, so that the pulse width cannot be narrowed unnecessarily.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a driving method of a plasma display panel capable of displaying a high quality image with a large number of gradations without making selective discharge unstable. And

[0013]

According to a method of driving a plasma display panel of the present invention, a plurality of row electrodes corresponding to a display line and a plurality of column electrodes arranged to intersect with the row electrodes are provided at respective intersections. A driving method of a plasma display panel, wherein a plasma display panel forming a discharge cell for carrying out a pixel is driven for each of a plurality of subfields constituting one field of a video signal, wherein each of the subfields is driven by the video signal. Pixel data pulses based on one display line are sequentially applied to the column electrodes while scanning pulses are sequentially applied to the row electrodes at the same timing as the application timing of the pixel data pulses. One of the discharge cell state in which the discharge cell is selectively turned on and the discharge cell is turned on or off By setting the address process to be set and applying a sustaining pulse to each of the row electrodes a number of times corresponding to the weighting of the sub-fields, only the discharge cells in the lighting discharge cell state are repeatedly sustain-discharged to discharge cells. The pulse width of the scan pulse and the pixel data pulse whose application timing is early in the addressing step of each of the subfields is the scan pulse whose application timing is late in the addressing step. And narrower than the pulse width of the pixel data pulse.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a diagram showing a schematic configuration of a plasma display device including a driving unit for driving the plasma display panel based on the driving method according to the present invention. This plasma display device includes a PDP 10 as a plasma display panel, a drive control circuit 2, an A / D converter 3, a memory 4, an address driver 6,
The drive unit includes a first sustain driver 7 and a second sustain driver 8.

The PDP 10 includes m column electrodes D _{1 to} D _m ,
Includes these column electrodes D, respectively and intersect to each of n which are arranged in the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n. The row electrodes X _{1 to} X _n and the row electrodes Y _{1 to} Y _n are a pair of row electrodes X _i (1 ≦ i ≦ n) and Y _i (1 ≦ i ≦ n), respectively, which are the first display lines in the PDP 10. ~ Carries the nth display line. A discharge space filled with a discharge gas is formed between the column electrode D and the row electrodes X and Y, and a pixel is provided at the intersection of each row electrode pair and the column electrode including this discharge space. It has a structure in which discharge cells are formed.

The A / D converter 3 converts the input video signal into 4-bit pixel data PD corresponding to each pixel and supplies it to the memory 4. The memory 4 sequentially writes the pixel data PD supplied from the A / D converter 3 in accordance with the write signal supplied from the drive control circuit 2. And one screen,
That is, the pixel data PD corresponding to the pixels in the first row and the first column
Pixel data PD corresponding to the pixels from the _11th row to the nth row and the mth column
Each time the writing of (n × m) pixel data PD up to _nm is completed, the memory 4 performs the following read operation.

First, the memory 4 has a subfield which will be described later.
In SF4, the pixel data PD ₁₁~ PD_nmEach top
The 4th bit, which is the upper bit, is the pixel drive data bit
DB4₁₁~ DB4_nmAnd these one display line at a time
It is read and supplied to the address driver 6. Next, below
In the sub-field SF3, the memory 4
Data PD₁₁~ PD_nmSet the 3rd bit of each pixel
Tabbit DB3₁₁~ DB3_nmAnd display these as 1
It is read out by the IN portion and supplied to the address driver 6.
Next, in a subfield SF2 described later, the memory
4 is pixel data PD₁₁~ PD_nmThe second bit of each
Pixel drive data bit DB2₁₁~ DB2 _nmAnd these
Is read out one display line at a time to the address driver 6.
Supply. Then, in a subfield SF1 described later
The memory 4 stores the pixel data PD₁₁~ PD_nmEach top
The first bit, which is the lower bit, is the pixel drive data bit
DB1₁₁~ DB1_nmAnd these one display line at a time
It is read and supplied to the address driver 6.

The drive control circuit 2 sends various timing signals for gradation driving the PDP 10 according to the light emission drive format shown in FIG. 5, to the address driver 6, the first sustain driver 7 and the second sustain driver 8.
Supply to each. In the emission driving format shown in FIG. 5, the display period of one field is divided into four subfields SF1 to SF4, and the simultaneous reset process Rc, address process Wc, light emission sustaining process Ic and erase process E are divided in each subfield. Respectively.

FIG. 6 shows the address driver 6 and the first driver according to various timing signals supplied from the drive control circuit 2.
FIG. 6 is a diagram showing various drive pulses applied to the PDP 10 by the sustain driver 7 and the second sustain driver 8 and their application timings. 6, in the simultaneous reset process Rc to be executed in the first subfield SF1~SF4 respectively, the first sustain driver 7 applies the row electrodes X ₁ to X _n to generate a negative-going reset pulse RP _x. Further, at the same time as the reset pulse RP _x , the second sustain driver 8 causes the positive reset pulse R
P _Y is generated and applied to the row electrodes Y _{1 to} Y _n . Depending on the simultaneous application of these reset pulses RP _x and RP _Y , the PDP
A reset discharge is generated in all 10 discharge cells, and wall charges are formed in each discharge cell. As a result, all the discharge cells are initialized to the "lighting discharge cell state".

Next, in the address step Wc, the address driver 6 generates a pixel data pulse having a pulse voltage according to the pixel drive data bit DB supplied from the memory 4 and outputs it for one display line (m). Each) to the column electrodes D _{1 to} D _m . That is, subfield SF4
So from the memory 4 pixel drive data bits DB4 ₁₁ ~
Since DB4 _nm is supplied, in the address process Wc of SF4, the address driver 6 generates a pixel data pulse having a pulse voltage according to the logic level of each of the pixel drive data bits DB4 _{11 to} DB4 _nm . Then, the address driver 6 first applies the pixel data pulse group DP ₁ consisting of m pixel data pulses corresponding to the first display line to the column electrodes D _{1 to} D _m , and then to the second display line. A pixel data pulse group DP ₂ consisting of corresponding m pixel data pulses is applied to the column electrodes D _{1 to} D _m . In the same manner, the address driver 6, the pixel data pulse group corresponding to the third to n display lines DP ₃ to DP _n
Are sequentially applied to the column electrodes D _{1 to} D _m .

In the subfield SF3, the memory 4
From pixel drive data bit DB3 ₁₁~ DB3_nmSupplied by
Therefore, in this SF3 address process Wc,
The address driver 6 uses the pixel drive data bit DB3₁₁
~ DB3_nmHas pulse voltage according to each logic level
Generate a pixel data pulse. And the address driver
First, the aver 6 detects m pixels corresponding to the first display line.
Pixel data pulse group DP consisting of data pulses₁The train
Pole D₁~ D_mApplied to the second display line
Pixel data pulse group D consisting of m pixel data pulses
P₂The column electrode D₁~ D_mApply to. In the same way,
The dress driver 6 corresponds to each of the 3rd to nth display lines.
Pixel data pulse group DP₃~ DP_nColumn electrode D
₁~ D_mApply to.

In the subfield SF2, the memory 4
From pixel drive data bit DB2 ₁₁~ DB2_nmSupplied by
Therefore, in the address process Wc of SF2,
The address driver 6 uses the pixel drive data bit DB2₁₁
~ DB2_nmHas pulse voltage according to each logic level
Generate a pixel data pulse. And the address driver
First, the aver 6 detects m pixels corresponding to the first display line.
Pixel data pulse group DP consisting of data pulses₁The train
Pole D₁~ D_mApplied to the second display line
Pixel data pulse group D consisting of m pixel data pulses
P₂The column electrode D₁~ D_mApply to. In the same way,
The dress driver 6 corresponds to each of the 3rd to nth display lines.
Pixel data pulse group DP₃~ DP_nColumn electrode D
₁~ D_mApply to.

Further, in the subfield SF1, the memory 4
From pixel drive data bit DB1 ₁₁~ DB1_nmSupplied by
Therefore, in this address process Wc of SF1,
The address driver 6 uses the pixel drive data bit DB1₁₁
~ DB1_nmHas pulse voltage according to each logic level
Generate a pixel data pulse. And the address driver
First, the aver 6 detects m pixels corresponding to the first display line.
Pixel data pulse group DP consisting of data pulses₁The train
Pole D₁~ D_mApplied to the second display line
Pixel data pulse group D consisting of m pixel data pulses
P₂The column electrode D₁~ D_mApply to. In the same way,
The dress driver 6 corresponds to each of the 3rd to nth display lines.
Pixel data pulse group DP₃~ DP_nColumn electrode D
₁~ D_mApply to.

Further, in the address process Wc of each of the subfields SF1 to SF4, the second sustain driver 8 is used.
But the pixel data pulse groups DP ₁ to DP _n each the same timing, the DP ₁ to DP _n scan pulse SP generates each having the same pulse width, the row electrodes Y ₁ as shown in figure 6 To Y _n in sequence. Here, discharge (selective erase discharge) occurs only in the discharge cells at the intersections of the display lines to which the scan pulse SP is applied and the column electrodes to which the high-voltage pixel data pulse is applied. By the selective erasing discharge, the wall charges formed in the discharge cells disappear, and the discharge cells shift to the "extinguished discharge cell state". On the other hand, the selective erase discharge as described above does not occur in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the discharge cells are initialized in the simultaneous reset step Rc. That is, the "lighted discharge cell state" is maintained.

That is, according to the address process Wc, each discharge cell is set to either the "lighting discharge cell state" or the "off discharge cell state" according to the pixel data corresponding to the input video signal. . Then, the light emission sustain process Ic in each subfield, a first sustain driver 7 and second sustain driver 8 each, to the row electrodes X ₁ to X _n and Y ₁ to Y _n as is shown in FIG. 6 Then, sustain pulses IP _X and IP _Y of positive polarity are alternately applied. On this occasion,
Light emission sustaining process Ic of each of the subfields SF1 to SF4
The number (or period) of sustain pulses IP repeatedly applied in the above is SF1: 1 SF2: 2 SF3: 4 SF4: 8 when the number in the sustaining emission process Ic of the subfield SF1 is "1".

At this time, only the discharge cells in which the wall charges are still remaining, that is, the discharge cells in the "lighting discharge cell state" are sustain-discharged each time the sustain pulses IP _X and IP _Y are applied, The light emitting state associated with the sustain discharge is maintained for the number of times described above. Then, in the last erase step E of each subfield, the second sustain driver 8 applies the erase pulse EP as shown in FIG. 6 to the row electrodes Y _{1 to} Y _n . As a result, all discharge cells are erase-discharged all at once, and all wall charges remaining in each discharge cell are extinguished.

As described above, according to the driving shown in FIGS. 5 and 6, in the address process Wc in each subfield,
Only the discharge cells set to the "lighted discharge cell state" repeat the light emission accompanying the discharge as many times as described above in the light emission sustaining process Ic immediately after that. At this time, the discharge cells in the address process Wc in each subfield are " Which of the "lighted discharge cell state" and the "off discharge cell state" is set is determined by the pixel data PD. For example, when the first bit of the pixel data PD is a logic level "1", the subfield In the address process Wc of SF1, the discharge cell is set to the "off discharge cell state".
In the light emission sustaining process Ic of the subfield SF1, the sustain discharge is not generated, and the discharge cell remains in the off state. On the other hand, when the logic level of the first bit of the pixel data PD is "0", the address process W of the subfield SF1 is performed.
In c, the discharge cell is set to the "lighted discharge cell state". At this time, the emission sustaining process Ic of the subfield SF1
In the above, the sustain discharge is generated the number of times assigned to the subfield SF1 as described above, and the discharge cells maintain the light emitting state during this period. Similarly, in the address process Wc of each of the subfields SF2 to SF4, the discharge cells are in the "off discharge cell state" and the "lighted discharge cell state" according to the logic levels of the second bit to the fourth bit of the pixel data PD. Is set to either one of Then, only the discharge cells set to the "lighting discharge cell state" are sustain-discharged the number of times assigned as described above in the light emission sustaining process Ic of the subfield, and the light emitting state is maintained during this period. According to such driving, the intermediate brightness according to the total number of sustain discharge light emission performed in each of the subfields SF1 to SF4 in one field period is visually recognized.

Here, in the present invention, the pulse widths of the scan pulse SP and the pixel data pulse sequentially applied for each one display line within the address process Wc of each subfield are made narrower as they are applied first. There is. For example, in the address process Wc of the subfield SF4, the pulse width T ₄₁ of the pixel data pulse group DP ₁ applied to the row electrode Y ₁ and the column electrode D immediately after the simultaneous reset process Rc is , Narrower than the pulse width T _{42 of the} scan pulse SP and the pixel data pulse group DP ₂ applied to the row electrode Y ₂ next. And the subfield SF
In 4, the scan pulse SP applied to the row electrode Y _n and the pulse width T _{4n of the} pixel data pulse group DP _n are the longest after the execution of the simultaneous reset process Rc.

That is, in the subfield SF4, the row
Electrode Y₁, Y₂, Y₃, ..., Y_nScan applied in order
Pulse width of pulse SP and pixel data pulse group DP
T₄₁, T ₄₂, T₄₃, ..., T_4nIs T₄₁<T₄₂<T₄₃, ..., <T_4n There is a big and small relationship.

In the address step Wc of the subfield SF3, the pulse width of the scan pulse SP applied to the row electrode Y ₁ and the pulse width of the pixel data pulse group DP ₁ applied to the column electrode D immediately after the simultaneous reset step Rc. T ₃₁ is narrower than the pulse width T _{32 of the} scan pulse SP and the pixel data pulse group DP ₂ applied next to the row electrode Y ₂ . In the subfield SF3, the scan pulse SP and the pulse width T _{3n of the} pixel data pulse group DP _n applied to the row electrode Y _n are the widest after the execution of the simultaneous reset process Rc.

That is, in the subfield SF3, the rows are
Electrode Y₁, Y₂, Y₃, ..., Y_nScan applied in order
Pulse width of pulse SP and pixel data pulse group DP
T₃₁, T ₃₂, T₃₃, ..., T_3nIs T₃₁<T₃₂<T₃₃, ..., <T_3n There is a big and small relationship.

In the address step Wc of the subfield SF2, the pulse width of the scan pulse SP applied to the row electrode Y ₁ and the pulse width of the pixel data pulse group DP ₁ applied to the column electrode D immediately after the simultaneous reset step Rc. T ₂₁ is narrower than the pulse width T _{22 of the} scan pulse SP and the pixel data pulse group DP ₂ applied to the row electrode Y ₂ next. In the sub-field SF2, the pulse width T _2n of the scan pulse SP and the pixel data pulse group DP _n applied to the row electrode Y _n is the longest after the execution of the simultaneous reset process Rc.

That is, in the subfield SF2, the row
Electrode Y₁, Y₂, Y₃, ..., Y_nScan applied in order
Pulse width of pulse SP and pixel data pulse group DP
T_{twenty one}, T _{twenty two}, T_{twenty three}, ..., T_2nIs T_{twenty one}<T_{twenty two}<T_{twenty three}, ..., <T_2n There is a relationship.

In the address process Wc of the subfield SF1, the scan pulse SP applied to the row electrode Y ₁ and the pixel data pulse group DP applied to the column electrodes D _{1 to} D _m immediately after the simultaneous reset process Rc. The pulse width T _{11 of 1} is narrower than the pulse width T _{12 of the} scan pulse SP and the pixel data pulse group DP ₂ applied to the row electrode Y ₂ next. Then, in the subfield SF1, the scan pulse SP applied to the row electrode Y _n is latest after the execution of the simultaneous reset step Rc.
And the pulse width T _{1n of the} pixel data pulse group DP _n is the widest.

That is, in the subfield SF1, the row
Electrode Y₁, Y₂, Y₃, ..., Y_nScan applied in order
Pulse width of pulse SP and pixel data pulse group DP
T₁₁, T ₁₂, T₁₃, ..., T_1nIs T₁₁<T₁₂<T₁₃, ..., <T_1n There is a big and small relationship.

That is, when repeated sustaining discharges are generated in the light emission sustaining process Ic of each subfield, charged particles are formed in the discharge cells, so that the discharge cells are in a state in which discharge is likely to occur. In other words, if the charged particles are sufficiently formed in the discharge cell, even if the pulse widths of the scan pulse and the pixel data pulse are narrow, the discharge cell surely causes the selective discharge in response to the application of these drive pulses. You can However, the charged particles gradually decrease over time.

Therefore, in view of this point, in the present invention, the pulse widths of the scan pulse and the pixel data pulse to be applied within the address process of each subfield are made narrower as the application time is earlier. As a result, the time spent in the address process is shortened while the selective discharge is surely generated. Further, in the present invention, the pulse widths of the scan pulse and the pixel data pulse to be applied in the address process of each subfield except the head subfield of one field are applied in the light emission sustaining process Ic of the immediately preceding subfield. The larger the number of sustain pulses, the narrower the pulse. At this time, in the light emission drive format shown in FIG. 5, the number of sustain pulses applied in the light emission sustaining step Ic of the subfield SF4 is the largest, and decreases in the order of SF3, SF2, and SF1.

Therefore, the pulse width T _3r of the scan pulse SP applied to the row electrode Y _r in the address step Wc of the subfield SF3 and the pulse width T _2r of the scan pulse SP applied to the row electrode Y _r in the address step Wc of SF2. , And the pulse width T _1r of the scanning pulse SP applied to the row electrode Y _r in the address process Wc of SF1 has a natural size relation of T _3r <T _2r <T _1r r: 1 to n.

For example, as shown in FIG. 6, the scanning pulse SP applied to the row electrode Y ₁ and the pulse width T ₃₁ of the pixel data pulse group DP ₁ in the address process Wc of the subfield SF3 are determined by the address process of the subfield SF2. Wc
, The pulse width is narrower than the scanning pulse SP applied to the row electrode Y ₁ and the pulse width T _{21 of the} pixel data pulse group DP ₁ .
The pulse width T ₂₁ is narrower than the scan pulse SP applied to the row electrode Y ₁ and the pulse width T _{11 of the} pixel data pulse group DP ₁ in the address step Wc of the subfield SF1. Applying Similarly, the pulse width T ₃₂ subfields SF3 in the address process Wc row electrodes Y ₂ scan pulse SP and the pixel data pulse group DP ₂ is applied to the In, in the address process Wc of the subfield SF2 to the row electrodes Y ₂ Scan pulse SP and pixel data pulse group DP ₂
Is narrower than the pulse width T _{22 of} . Also, this pulse width T ₂₂ is
This is narrower than the scan pulse SP applied to the row electrode Y ₂ and the pulse width T _{12 of the} pixel data pulse group DP ₂ in the address step Wc of the subfield SF1.

That is, as the number of sustain discharges generated in the light emission sustaining process Ic increases, the amount of charged particles generated by the sustain discharges increases, so that each discharge cell is in a state where discharge is likely to occur. Therefore, at this time,
Even if the pulse widths of the scan pulse SP and the pixel data pulse are narrowed, the selective discharge is stably generated. Therefore,
Focusing on this point, the pulse widths of the scan pulse and the pixel data pulse to be applied in the address process of each subfield except for the first subfield are set to the sustain pulse applied in the light emission sustaining process Ic of the immediately preceding subfield. The larger the number, the narrower it became. As a result, while the selective discharge is surely generated, the time spent in the address process is further shortened.

The subfield immediately before the first subfield SF4 is, as shown in FIG. 7, the last subfield SF in the field immediately before this field.
It becomes 1. However, since the preliminary period AU for changing the driving sequence is provided after the subfield SF1, most of the charged particles formed in the light emission sustaining process Ic of the subfield SF1 disappear within the preliminary period AU. I will end up. Therefore, as shown in FIG. 6, the pulse widths T ₄₁ , T ₄₂ , ... Of the scanning pulse SP and the pixel data pulse applied in the address step Wc of the leading subfield SF4.
., T _{4m for} each of the address steps W of subfield SF3
The pulse widths of the scan pulse SP and the pixel data pulse applied at c are made wider than the pulse widths T ₃₁ , T ₃₂ , ..., T _3m .

As described above, in the present invention, 1) the charged particles formed by the sustain discharge decrease with the passage of time. 2) As the number of sustain discharges increases, the amount of charged particles remaining in the discharge cell increases. 3) If the amount of charged particles remaining in the discharge cell is large, the selective discharge is stably generated even if the pulse widths of the scan pulse and the pixel data pulse are narrowed.

Paying attention to the above point, the pulse widths of the scan pulse and the pixel data pulse applied within the address process are narrowed as the application time is earlier, and the number of sustain pulses applied immediately before each address process is reduced. The more the number, the narrower it was. Therefore, according to the present invention, the time spent in each address process can be shortened as much as the pulse widths of the scan pulse and the pixel data pulse are narrowed as described above.

The driving method of the plasma display panel according to the present invention can also be applied to a plasma display device for gradation driving the plasma display panel according to an emission driving format other than the emission driving format shown in FIG. FIG. 8 is a diagram showing another configuration example of the plasma display device for driving the plasma display panel in gradation according to the emission drive format shown in FIG. In the light emission drive format shown in FIG. 9, the display period of one field is divided into subfields SF1 to SF1.
It is divided into 8 subfields, SF8, and in each subfield, the simultaneous reset process R as described above is performed.
c, address step Wc, light emission sustaining step Ic and erasing step E
Are executed respectively.

The plasma display device shown in FIG.
It is composed of a PDP 10 as a plasma display panel and a drive unit for driving the PDP 10 according to an input video signal. In addition, the drive unit includes the drive control circuit 12, A /
D converter 13, memory 14, address driver 16, first sustain driver 17, second sustain driver 1
8 and a data conversion circuit 30.

The PDP 10 includes m column electrodes D _{1 to} D _m as data electrodes, and n row electrodes X _{1 to} X _n and row electrodes Y ₁ arranged so as to intersect with the respective column electrodes. ~ Y _n
Is equipped with. These row electrodes X _{1 to} X _n and row electrodes Y ₁ to
Y _n serves as a display line in the PDP with a pair of row electrodes X _i (1 ≦ i ≦ n) and Y _i (1 ≦ i ≦ n). The column electrode D and the row electrodes X and Y are arranged so as to face each other with a discharge space filled with a discharge gas interposed therebetween, and a pixel is provided at the intersection of each row electrode pair and the column electrode including this discharge space. The structure is such that a discharge cell that plays a role in

The A / D converter 3 converts the input video signal into each pixel.
Data converted to 8-bit pixel data PD corresponding to
It is supplied to the conversion circuit 30. FIG. 10 shows the data conversion circuit 3
It is a figure which shows the internal structure of 0. In FIG. 10, the first data
The data conversion circuit 32 has 8 bits, which is "0" to "255" 2
The pixel data PD capable of expressing the brightness of 56 gradations is
Brightens from "0" to "128" according to the conversion characteristics shown in FIG.
8-bit brightness suppression pixel data PD _PConversion to
To do. Then, the first data conversion circuit 32 is
Suppressed pixel data PD_PIs supplied to the multi-gradation processing circuit 33.
It

The multi-gradation processing circuit 33 performs multi-gradation processing such as error diffusion processing and dither processing on the 8-bit brightness suppression pixel data PD _P. As a result, the multi-gradation processing circuit 33 obtains multi-gradation pixel data PD _S by compressing the number of bits to 4 bits while maintaining the number of gradation representations of visual luminance to be approximately 256 gradations. . 12
FIG. 6 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

As shown in FIG. 12, such multi-gradation is realized.
The processing circuit 33 includes an error diffusion processing circuit 330 and a dither processing.
It comprises a logic circuit 350. First, the error diffusion processing circuit
The data separation circuit 331 in 330 uses the first data
8-bit brightness suppression pixel supplied from the digital conversion circuit 32
Data PD_PLower 2 bits of error data, upper 6 bits
Data is separated as display data. The adder 332 is
The error data and the delay output from the delay circuit 334.
And the multiplication output of the coefficient multiplier 335.
The value is supplied to the delay circuit 336. The delay circuit 336 adds
The added value supplied from the calculator 332 is used as the pixel data P
The delay time D is the same as the sampling period of D
Delay and add this to the delayed addition signal AD ₁As the above coefficient power
It is supplied to the calculator 335 and the delay circuit 337, respectively. Coefficient multiplication
The calculator 335 uses the delayed addition signal AD₁A predetermined coefficient value K₁
(For example, "7/16") is multiplied and the multiplication result is added to the above.
It is supplied to the calculator 332. The delay circuit 337 is configured to add the delay
Arithmetic signal AD₁(1 horizontal scanning period-the above delay time D x
4) Delay addition signal AD delayed by a certain time₂
Is supplied to the delay circuit 338. The delay circuit 338 is
Such delayed addition signal AD₂Is delayed by the above delay time D
Delayed addition signal AD₃As coefficient multiplier 3
39. Also, the delay circuit 338 is configured to add such delay
Arithmetic signal AD₂The delay time D × 2
Delayed addition signal AD_FourAs coefficient multiplier
Supply to 340. In addition, the delay circuit 338 is used to
Delayed addition signal AD₂For only the above delay time D × 3
Delayed addition signal AD_FiveAs coefficient multiplier
341. The coefficient multiplier 339 uses the delay addition described above.
Signal AD₃A predetermined coefficient value K₂(For example, "3/16")
The obtained multiplication result is supplied to the adder 342. Coefficient multiplication
The device 340 receives the delayed addition signal AD_FourA predetermined coefficient value K
₃Add the multiplication result obtained by multiplying (eg, "5/16")
To the container 342. The coefficient multiplier 341 uses the delay adder
Arithmetic signal AD_FiveA predetermined coefficient value K_FourMultiply (for example, "1/16")
The multiplication result thus obtained is supplied to the adder 342. Adder
342 is each of the coefficient multipliers 339, 340 and 341
The addition signal obtained by adding the multiplication results supplied from each
Is supplied to the delay circuit 334. The delay circuit 334 is
The added signal is delayed by the delay time D.
And supply it to the adder 332. The adder 332 is
Error data supplied from the data separation circuit 331,
The delay output from the delay circuit 334 and the coefficient multiplier 335
If there is no carry in the addition result with the multiplication output, the logical level
Carry of logic level "1" if there is a carry "0" or carry.
Out signal C_OIs generated and supplied to the adder 333. Addition
The calculator 333 is supplied from the data separation circuit 331.
The display data includes the carry-out signal C_OAdded
Output as 6-bit error diffusion processed pixel data ED
Force

The operation of the error diffusion processing circuit 330 will be described below by taking the case where the error diffusion processing pixel data ED corresponding to the pixel G (j, k) of the PDP 10 as shown in FIG. 13 is obtained as an example. First, the pixel G (j,
pixel G (j, k-1) on the left side of k) and pixel G (j-1, k-
1), the pixel G (j-1, k) directly above, and the pixel G (j-1, k) diagonally above right.
k + 1) each error data corresponding to each, that is, the error data corresponding to the pixel G (j, k-1): delay addition signal AD ₁ error data corresponding to the pixel G (j-1, k + 1) : Error data corresponding to delayed addition signal AD ₃ pixel G (j-1, k): Error data corresponding to delayed addition signal AD ₄ pixel G (j-1, k-1): Delay addition signal AD ₅ The adder 332 performs weighting with the predetermined coefficient values K _{1 to} K _{4 as} described above. Furthermore,
The adder 332 adds error data corresponding to the lower 2 bits of the brightness suppression pixel data PD _P , that is, the pixel G (j, k), to the addition result. Then, the adder 333
Is the error diffusion of the carryout signal C _O obtained by the addition of the adder 332 and the upper 6 bits of the luminance suppression pixel data PD _P , that is, the display data in the pixel G (j, k). Output as processed pixel data ED.

That is, in the error diffusion processing circuit 330,
The upper 6 bits of the brightness suppression pixel data PD _P are regarded as display data, and the lower 2 bits are regarded as error data. Then, the error diffusion processing circuit 330 causes the peripheral pixels G (j, k-1), G (j-1, k +).
1), G (j-1, k), and G (j-1, k-1) weighted addition of the error data obtained above are reflected in the display data to obtain error diffusion processed pixel data. You get it as an ED. By this operation, the luminance of the lower 2 bits in the original pixel {G (j, k)} is pseudo-expressed by the peripheral pixels, and therefore, the number of bits less than 8 bits, that is, the display data of 6 bits is displayed. Thus, it is possible to express the luminance gradation equivalent to that of the pixel data PD of 8 bits.
It should be noted that if the coefficient value of the error diffusion is constantly added to each pixel, noise due to the error diffusion pattern may be visually confirmed and the image quality is deteriorated. Therefore, as in the case of the dither coefficient described later, the error diffusion coefficients K _{1 to} K ₄ to be assigned to each of the four pixels may be changed for each field.

The dither processing circuit 350 shown in FIG.
Performs dither processing on the error diffusion processing pixel data ED supplied from the error diffusion processing circuit 330. This dither processing is intended to represent one intermediate brightness by a plurality of adjacent pixels. For example, four pixels that are adjacent to each other in the left, right, top, and bottom are set as one set, and four dither coefficients a to d having different coefficient values are assigned and added to each pixel data corresponding to each pixel of this one set. . According to such dither processing, four different combinations of intermediate display levels are generated in four pixels. However, if the dither pattern consisting of the dither coefficients a to d is constantly added to each pixel, noise due to this dither pattern may be visually confirmed and the image quality is deteriorated.

Therefore, in the dither processing circuit 350, the dither coefficient a to be assigned to each of the four pixels.
.About.d is changed for each field. Figure 1
4 is a diagram showing an internal configuration of the dither processing circuit 350. In FIG. 14, a dither coefficient generation circuit 352
Are adjacent to each other as shown in FIG.
A pixel G (j, k), a pixel G (j, k + 1), a pixel G (j + 1, k), and a dither coefficient a to be assigned to each pixel G (j + 1, k + 1),
b, c, d are generated and these are supplied to the adder 351. At this time, the dither coefficient generation circuit 352 changes the dither coefficients a to d to be assigned to each of these four pixels for each field as shown in FIG.

That is, in the first first field, pixel G (j, k): dither coefficient a pixel G (j, k + 1): dither coefficient b pixel G (j + 1, k): dither coefficient c Pixel G (j + 1, k + 1): dither coefficient d In the next second field, pixel G (j, k): dither coefficient b pixel G (j, k + 1): dither coefficient a pixel G ( j + 1, k): dither coefficient d pixel G (j + 1, k + 1): dither coefficient c In the next third field, pixel G (j, k): dither coefficient d pixel G (j, k) +1): dither coefficient c pixel G (j + 1, k): dither coefficient b pixel G (j + 1, k + 1): dither coefficient a And in the fourth field, pixel G (j, k) : Dither coefficient c pixel G (j, k + 1): dither coefficient d pixel G (j + 1, k): dither coefficient a pixel G (j + 1, k + 1): dither coefficient b Generate the dither coefficients a to d and repeat the operation in each of the first to fourth fields. To. That is, when the dither coefficient generating operation in the fourth field is completed, the operation returns to the operation in the first field and the above operation is repeated.

The adder 351 shown in FIG. 14 has a pixel G (j, k), a pixel G (j, k + 1), a pixel G (j + 1, k), and a pixel G.
Error diffusion processed pixel data ED corresponding to each (j + 1, k + 1)
, The dither coefficients a to d are respectively added, and the dither-added pixel data obtained at this time is added to the upper bit extraction circuit 35.
Supply to 3. For example, in the first field shown in FIG. 15, the adder 351 has the error diffusion processed pixel data ED + corresponding to the pixel G (j, k).
Error diffusion processing pixel data ED corresponding to dither coefficient a and pixel G (j, k + 1)
+ Dither coefficient b, error diffusion processing pixel data ED corresponding to pixel G (j + 1, k)
+ Dither coefficient c, error diffusion processed pixel data E corresponding to pixel G (j + 1, k + 1)
Each D + dither coefficient d 1 is supplied to the upper bit extraction circuit 353 as dither addition pixel data.

The high-order bit extraction circuit 353 extracts the high-order 4 bits of the dither-added pixel data, and supplies this as multi-gradation pixel data PD _S to the second data conversion circuit 34 shown in FIG. To do. The second data conversion circuit 34 converts the 4-bit multi-gradation pixel data PD _S as described above into 8-bit pixel drive data GD according to the conversion table shown in FIG. 16 and supplies it to the memory 14.

The memory 14 sequentially writes the pixel drive data GD according to the write signal supplied from the drive control circuit 12. Then, for one screen, that is, from the pixel drive data GD ₁₁ corresponding to the pixels in the first row and the first column to the pixel drive data GD _nm corresponding to the pixels in the nth row and the mth column (n
(Xm) each time writing is completed, the memory 14
The following read operation is performed.

First, the memory 14 stores the pixel drive data GD.
₁₁ to GD _nm each capture the first bit is the least significant bit pixel driving data bits DB1 ₁₁ ~DB1 _nm, address process Wc of the subfield SF1 shown them in Figure 9
At, the display lines are read one by one and supplied to the address driver 16. Next, the memory 14 regards the second bit of each of the pixel drive data GD _{11 to} GD _nm as pixel drive data bits DB2 _{11 to} DB2 _nm, and in the address step Wc of the subfield SF2 shown in FIG.
One display line is read and supplied to the address driver 16. Thereafter, similarly, the memory 14 separates the third bit to the eighth bit of the 8-bit pixel drive data GD and separates the pixel drive data bit DB3 for each bit digit.
To DB8 are shown in subfields SF3 to SF shown in FIG. 9, respectively.
At 8, the display lines are read one by one and supplied to the address driver 16.

The drive control circuit 12 generates various timing signals for gradation driving the PDP 10 according to the light emission drive format shown in FIG.
Sustain driver 17 and second sustain driver 1
8 Supply to each. FIG. 17 shows various drive pulses applied to the PDP 10 by the address driver 16, the first sustain driver 17 and the second sustain driver 18 according to various timing signals supplied from the drive control circuit 12, and their application timings. It is a figure.

In the simultaneous reset process Rc executed at the beginning of each subfield in FIG. 17, the first sustain driver 17 generates a negative reset pulse RP _x and applies it to the row electrodes X _{1 to} X _n . Further, at the same time as the reset pulse RP _x , the second sustain driver 18
Generates a reset pulse RP _Y of positive polarity to generate the row electrode Y ₁
~ Y _n . These reset pulses RP _x and RP
_In response to the simultaneous application of _Y, a reset discharge is generated in all the discharge cells of PDP 10, and wall charges are formed in each discharge cell. As a result, all the discharge cells are initialized to the "lighting discharge cell state".

In the address process Wc of each subfield, first, the address driver 16 generates a pixel data pulse having a pulse voltage according to the pixel drive data bit DB supplied from the memory 14. For example, in the subfield SF1, the pixel drive data bit DB1 is supplied from the memory 14, so that the address driver 1
6 generates a pixel data pulse having a pulse voltage according to the logic level of the pixel drive data bit DB1. At this time, the address driver 16 generates a pixel data pulse having a high voltage when the logic level of the pixel drive data bit DB is "1" and a low voltage (0 volt) when the logic level is "0". . Then, the address driver 16
Pixel data pulse groups DP ₁ , DP 2, ..., DP _n obtained by grouping the pixel data pulses for one display line are sequentially applied to the column electrodes D _{1 to} D _m .

Further, in the address process Wc, the second
The sustain driver 18 uses the pixel data pulse group D
A negative polarity scanning pulse SP is generated at the same timing as the application timing of each of P _{1 to} DP _n , and this is sequentially applied to the row electrodes Y ₁ to Y _n as shown in FIG. Here, selective erase discharge is generated only in the discharge cells at the intersections of the display lines to which the scan pulse SP is applied and the column electrodes to which the high-voltage pixel data pulse is applied. By the selective erasing discharge, the wall charges formed in the discharge cells disappear, and the discharge cells shift to the "extinguished discharge cell state".
On the other hand, the selective erase discharge as described above does not occur in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied, and the simultaneous reset process R
The state initialized in c, that is, the "lighting discharge cell state" is maintained.

That is, according to the address process Wc, each discharge cell is set to one of the "lighting discharge cell state" and the "off discharge cell state" according to the pixel data corresponding to the input video signal. . Next, in the light emission sustaining process Ic in each subfield, the first sustain driver 17
And the second sustain driver 18 has row electrodes X ₁ to
A sustain pulse I having a positive polarity alternately with respect to X _n and Y _{1 to} Y _n
Apply P _X and IP _Y. At this time, the subfield SF
The number (or period) of sustain pulses IP repeatedly applied in each of the emission sustaining steps Ic of 1 to SF8 is SF1: 1 SF2: 6 when the number of sustaining pulses IP in the subfield SF1 is "1". SF3: 16 SF4: 24 SF5: 35 SF6: 46 SF7: 57 SF8: 70.

By this operation, only the discharge cells in which the wall charge remains, that is, the discharge cells in the "lighting discharge cell state" are sustain-discharged each time the sustain pulses IP _X and IP _Y are applied. The light emission state associated with the sustain discharge is maintained for the number of times described above. Then, in the last erase step E of each subfield, the second sustain driver 1
8 shows the erase pulse EP as shown in FIG.
Applied to _{1 to} Y _n . As a result, all discharge cells are erase-discharged all at once, and all wall charges remaining in each discharge cell are extinguished.

As described above, according to the driving based on the light emission driving format shown in FIG. 9, only the discharge cells set to the "lighting discharge cell state" in the address process Wc in each subfield have the light emission sustaining process immediately thereafter. In Ic, the light emission state associated with the discharge is maintained as many times as described above. At this time, in the plasma display device shown in FIG.
In accordance with the logic level of each bit of the pixel drive data GD as shown in FIG. 5, the discharge cells are "lighted discharge cell state" and "at the discharge step in the subfield address process Wc corresponding to the bit digit.
It is set to either one of the extinguished discharge cell state. That is, when the bit in the pixel drive data GD is the logic level "1", as shown by the black circle in FIG. The selective erasing discharge is generated in the address process Wc of the corresponding subfield, so that the selective erasing discharge sets the discharge cell to the "off discharge cell state" while the bit in the pixel drive data GD is at the logical level ". If it is "0", the selective erase discharge is not generated in the address process Wc of the subfield corresponding to the bit digit. Therefore, the discharge cell maintains the "lighted discharge cell state", and the white circle in FIG. As shown in FIG. 7, the sustaining discharge is repeatedly generated in the light emitting sustaining process Ic of the subfield corresponding to the bit digit, and the light emission accompanying this discharge is repeated. Then, by the sum of the number of emissions that are performed in the subfield SF1~SF8 each light emission sustain process Ic, it is the variety of intermediate brightness are stepwise representation.

Here, the bit patterns that can be taken as the pixel drive data GD consisting of 8 bits are only 9 patterns as shown in FIG. Therefore, according to the driving using the 9 patterns of pixel drive data GD, the emission luminance ratio visually perceived in one field period is {0, 1, 7, 23, 47, 82, 128, 185, 255}. An intermediate luminance display for 9 gradations is performed.

The pixel data PD can express halftones of 256 gradations with 8 bits.
Therefore, in order to realize halftone luminance display close to 256 gradations even by driving 9 gradations as described above, the multi-gradation processing circuit 33 performs multi-gradation processing such as error diffusion and dither processing. I am doing it. By the way, in the drive using the nine types of pixel drive data GD shown in FIG. 16, the discharge cells always perform sustain discharge light emission in the first subfield SF1 except for the case of the brightness "0". Then, until the selective erasing discharge is generated in the subfields after the subfield SF2, as indicated by white circles, the subfields for performing the sustain discharge light emission are continuous. At this time, once the selective erasing discharge is generated in one subfield, the selective erasing discharge is continuously generated in each of the subsequent subfields as shown by the black circles to maintain the discharge cells in the "off discharge cell state". I am letting you.

That is, in one field display period, a continuous light emission state in which sustain discharge light emission as shown by white circles continues and a subfield in which selective erase discharge as shown by black circles continuously occurs are turned off. There are continuous states and. At this time, the number of times the discharge cell transits from the above-mentioned continuous light emission state to the continuous extinction state within one field display period is one or less, and once it transits to the continuous extinction state, light emission continues within this one-field display period. It never returns to the state. That is, FIG.
As shown in FIG. 9, in the nine kinds of light emission drive patterns corresponding to the nine kinds of pixel drive data GD, the light emission continuation state (white circle) and the extinction continuation state (black circle) are reversed in one field period. There is no pattern. Therefore, according to such driving, the occurrence of false contours that occurs when such inverted light emission patterns appear in two areas adjacent to each other in the display screen is suppressed.

At this time, when carrying out such driving, FIG.
As shown in FIG. 7, in the address process Wc of each subfield, the pulse widths of the scanning pulse SP and the pixel data pulse applied to the PDP 10 are narrowed as the application timing is earlier. That is, as shown in FIG. 17, in the subfield SF1, the row electrodes Y ₁ , Y ₂ , Y ₃ , ...
,, pulse widths T ₁₁ , T ₁₂ , T ₁₃ , ..., T of the scanning pulse SP and the pixel data pulse group DP applied in the order of Y _n
1n has a magnitude relation of T ₁₁ <T ₁₂ <T ₁₃ , ..., <T _1n .

In the subfield SF2, the pulse widths T ₂₁ , T of the scanning pulse SP and the pixel data pulse group DP applied in the order of the row electrodes Y ₁ , Y ₂ , Y ₃ , ..., Y _n.
22 , T ₂₃ , ..., T _2n have a magnitude relationship of T ₂₁ <T ₂₂ <T ₂₃ , ..., <T _2n .

[0071] Furthermore, within the sub-field SF3, the row electrodes _{Y 1, Y 2, Y 3} , ····, Y n becomes the scan pulse SP and the pixel data pulse group DP is sequentially applied to the pulse width T _31, T
₃₂ , T ₃₃ , ..., T _3n have a magnitude relationship such that T ₃₁ <T ₃₂ <T ₃₃ , ..., <T _3n .

Further, in the subfield SF4, the pulse widths T ₄₁ , T of the scanning pulse SP and the pixel data pulse group DP applied in the order of the row electrodes Y ₁ , Y ₂ , Y ₃ , ..., Y _{n.
, 42} , T ₄₃ , ..., T _4n are in a relationship of T ₄₁ <T ₄₂ <T ₄₃ , ..., <T _4n .

[0073] Furthermore, within the sub-fields SF5, the row electrodes _{Y 1, Y 2, Y 3} , ····, Y n becomes the pulse width of the scanning pulse SP and the pixel data pulse group DP is sequentially applied to T _51, T
_{, 52} , T ₅₃ , ..., T _5n have a magnitude relationship such that T ₅₁ <T ₅₂ <T ₅₃ , ..., <T _5n .

In the subfield SF6, the pulse widths T ₆₁ , T of the scanning pulse SP and the pixel data pulse group DP applied in the order of the row electrodes Y ₁ , Y ₂ , Y ₃ , ..., Y _{n.
, 62} , T ₆₃ , ..., T _6n have a magnitude relationship of T ₆₁ <T ₆₂ <T ₆₃ , ..., <T _6n .

In the subfield SF7, the pulse widths T ₇₁ , T of the scanning pulse SP and the pixel data pulse group DP applied in the order of the row electrodes Y ₁ , Y ₂ , Y ₃ , ..., Y _n.
72 , T ₇₃ , ..., T _7n have a magnitude relationship such that T ₇₁ <T ₇₂ <T ₇₃ , ..., <T _7n .

Further, in the sub-field SF8, the pulse widths T ₈₁ , T of the scanning pulse SP and the pixel data pulse group DP applied in the order of the row electrodes Y ₁ , Y ₂ , Y ₃ , ..., Y _{n.
82, T 83, ····, T} 8n _{is, T 81 <T 82 <T} 83, ····, in magnitude relation of <T _8n.

Further, the pulse widths of the scan pulse and the pixel data pulse applied in the address process of each subfield are made narrower as the total number of sustain pulses applied from the beginning of one field to immediately before that subfield increases. ing. Here, according to the driving using the nine kinds of pixel drive data GD as shown in FIG. 16, the sustain discharge is always performed in each subfield consecutive from the first subfield SF1 except when the brightness level "0" is expressed. Therefore, in one field,
The total number of sustain pulses applied until immediately before the address process of the subfield is the largest in the last subfield SF8, and the smallest in the first subfield SF1. Therefore, as shown in FIG. 17, the pulse widths T _{1r to} T _8r of the scan pulse SP and the pixel data pulse group DP _r applied to the row electrode Y _r in the address process Wc of each of the subfields SF 1 to SF 8 are T _8r <T. _7r <T _6r <T _5r <T _4r <T _3r <T _2r <T _1r r: 1 to n are natural numbers.

That is, as the number of sustain discharges performed immediately before the addressing process increases, the number of charged particles in the discharge cell increases, and the discharge cell easily discharges. Even if the pulse width of the pixel data pulse is narrowed, stable selective discharge can be generated. Therefore, as described above, the pulse widths of the scan pulse and the pixel data pulse applied in the rear subfield are made narrower than the pulse widths of the scan pulse and the pixel data pulse applied in the address step of the first subfield of one field. This further reduces the time spent in the address process.

Further, in the plasma display device shown in FIG. 8, instead of the emission drive format shown in FIG.
It is also possible to adopt the light emission drive format shown in (1) to implement gradation drive for the PDP 10. In the emission drive format shown in FIG. 18, subfields SF1 to
The point that the address process Wc and the light emission sustaining process Ic are executed in each SF8 is similar to the case of the light emission drive format shown in FIG. However, FIG.
In the light emission drive format shown in FIG. 8, the simultaneous reset process Rc as described above is executed only in the first subfield SF1, and the erase process E is executed only in the last subfield SF8.

FIG. 19 shows various driving pulses applied to the PDP 10 by the address driver 16, the first sustain driver 17 and the second sustain driver 18 of FIG. 8 so as to carry out the driving according to the light emission driving format shown in FIG. FIG. 4 is a diagram showing the application timing thereof. 19, in the simultaneous reset process Rc to be executed only in the first subfield SF1, the first sustain driver 17 applies the row electrodes X ₁ to X _n to generate a negative-going reset pulse RP _x. Further, at the same time as the reset pulse RP _x , the second sustain driver 18 generates a positive reset pulse RP _Y and applies it to the row electrodes Y _{1 to} Y _n . In response to the simultaneous application of these reset pulses RP _x and RP _Y , reset discharge is generated in all the discharge cells of PDP 10, and wall charges are formed in each discharge cell. As a result, all the discharge cells are initialized to the "lighting discharge cell state".

Next, in the address process Wc of each of the subfields SF1 to SF8, the address driver 16 causes the pixel data pulse groups DP ₁ , DP ₂ , DP ₃ ,.
.., DP _n are sequentially applied to the column electrodes D _{1 to} D _{m as shown} in FIG. At this time, the second sustain driver 18 generates the negative scanning pulse SP at the same timing as that of each of the pixel data pulse groups DP _{1 to} DP _n to generate the row electrodes Y ₁ to.
The voltage is sequentially applied to Y _n . Here, the scan pulse S
Selective erase discharge is generated only in the discharge cells at the intersections of the display lines to which P is applied and the column electrodes to which the high-voltage pixel data pulse is applied. By the selective erasing discharge, the wall charges formed in the discharge cells disappear, and the discharge cells shift to the "extinguished discharge cell state". On the other hand, the selective erase discharge as described above does not occur in the discharge cells to which the scan pulse SP is applied but the low-voltage pixel data pulse is applied. Therefore, at this time, the discharge cell maintains the state up to immediately before. That is, the discharge cells that were in the "lighting discharge cell state" until immediately before the scan pulse SP was applied are set to the "lighting discharge cell state" as they are, and the discharge cells that were in the "extinction discharge cell state" remain the "off discharge discharge". It is set to "cell state".

Next, in the light emission sustaining process Ic of each of the subfields SF1 to SF8, the first sustain driver 17 is
As shown in FIG. 19, the second sustain driver 18 and the second sustain driver 18 alternately apply positive sustain pulses IP _X and IP _Y to the row electrodes X _{1 to} X _n and Y _{1 to} Y _n , respectively. At this time, the number of sustain pulses IP repeatedly applied in the emission sustaining process Ic of each of the subfields SF1 to SF8.
(Or period) is the light emission sustaining process I of the subfield SF1.
When the number of times in c is set to "1", it is SF1: 1 SF2: 6 SF3: 16 SF4: 24 SF5: 35 SF6: 46 SF7: 57 SF8: 70.

By this operation, only the discharge cells in which the wall charges remain, that is, the discharge cells in the "lighting discharge cell state" are sustain-discharged each time the sustain pulses IP _X and IP _Y are applied. The light emission state associated with the sustain discharge is maintained for the number of times described above. Then, in the erase process E executed only in the last subfield SF8,
The second sustain driver 18 applies the erase pulse EP as shown in FIG. 19 to the row electrodes Y _{1 to} Y _n . As a result, all discharge cells are erase-discharged all at once, and all wall charges remaining in each discharge cell are extinguished.

FIG. 20 shows the data conversion circuit 30 when the drive according to the light emission drive format shown in FIG. 18 is performed.
FIG. 3 is a diagram showing a data conversion table used in the second data conversion circuit 34 and a light emission drive pattern in one field period. According to the pixel drive data GD obtained by such a data conversion table, the selective erase discharge is generated only in the address process Wc of one subfield of the subfields SF1 to SF8, as indicated by the black circles in FIG. It is caused. At this time, the wall charge is formed in the discharge cells and the discharge cells can be transited from the "extinguished discharge cell state" to the "lit discharge cell state" by the simultaneous reset process Rc in the first subfield SF1. Only. Therefore, the subfields SF1 to SF
The discharge cell maintains the "lighted discharge cell state" until the selective erasing discharge is generated in one subfield (indicated by a black circle) of the eight. Then, in the light emission sustaining process Ic of each of the subfields (shown by white circles) existing during this period, the discharge cells repeatedly perform light emission accompanying the sustain discharge. Therefore, according to the driving shown in FIGS. 18 to 20, the light emission pattern in the one-field display period is as shown in FIG.
It becomes the same as the case of adopting the light emission drive format as shown in, and the intermediate brightness display for 9 gradations with the light emission brightness ratio of {0, 1, 7, 23, 47, 82, 128, 185, 255} is made. It

However, in the driving shown in FIGS. 18 to 20, the number of reset discharges performed in one field display period is one. That is, the contrast of the screen can be improved as compared with the case where the driving shown in FIGS. 9 and 16 is performed, because the number of reset discharges accompanied by light emission irrelevant to the display content is reduced. At this time, as in the above-described embodiment (driving shown in FIG. 17), the pulse widths of the scanning pulse and the pixel data pulse are narrowed as shown in FIG. There is. Further, similar to the driving shown in FIG. 17, as the number of sustain pulses applied until immediately before each address process (from the beginning of one field) increases, the scan pulse and the pixel to be applied in the address process of the subfield. The pulse width of the data pulse is narrowed.

The pixel drive data GD shown in FIG.
According to the above, selective erase discharge is generated only in any one of the subfields SF1 to SF8. However, when the amount of charged particles remaining in the discharge cells is small, this selective erase discharge is normal. May not occur. Therefore, as the conversion table used in the second data conversion circuit 34, the one shown in FIG. 21 may be used instead of the one shown in FIG.

Note that "*" shown in FIG. 21 indicates that either the logic level "1" or "0" may be used, and the triangular mark indicates that such "*" is the logic level "1". It shows that selective erase discharge is generated only in the case. According to the pixel drive data GD shown in FIG. 21, the selective erase discharge is carried out at least in the address process Wc of each of two consecutive subfields. In short, even if the first selective erasing discharge is incomplete, charged particles are generated even from this incomplete selective erasing discharge, so that the second selective erasing discharge can be normally performed. .

Further, in the above embodiment, the pulse widths of the scanning pulse and the pixel data pulse are shown in FIG. 6, FIG. 17 and FIG.
As shown in FIG. 9, the display line is gradually changed for each display line, but it may be changed for each display line. For example, the address process Wc of the subfield SF1
Then, the pulse widths of the scanning pulses SP applied to the row electrodes Y _{1 to} Y ₃ are set to the same pulse width T ₁₁ and the row electrode Y ₄
Scan pulse SP each pulse width to be applied to to Y ₆ T ₁₁
The pulse width T ₁₂ is wider than that. And after that, 3
The pulse width of the scan pulse SP is widened for each display line.

Further, in the embodiments shown in FIGS. 6, 17 and 19, the pulse widths of the scanning pulse and the pixel data pulse are changed every subfield, but they are changed every plural subfields. It may be done. For example, the scan pulse S applied to the row electrode Y _r in the address process Wc of each of the subfields SF1 to SF8.
P and the pulse width T _{1r to} T _8r of the pixel data pulse are set as _follows : T _8r = T _7r <T _6r = T _5r <T _4r = T _3r <T _2r = T _1r r: 2 subfields like natural numbers 1 to n It changes every time.

[0090]

As described above in detail, in the present invention,
The pulse widths of the scan pulse and the pixel data pulse applied in the address process of each subfield are made narrower as the application time is earlier. Therefore, according to the present invention, the time spent in the address process can be shortened while guaranteeing stable selective discharge. Therefore, if the number of subfields is increased by the shortened time, the number of gray scales increases. It is possible to display a high quality image.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a plasma display device.

FIG. 2 is a diagram showing an example of a light emission drive format based on a subfield method.

FIG. 3 is a diagram showing various drive pulses applied by the drive device 100 shown in FIG. 1 to a column electrode and a row electrode of the PDP 10 in one subfield, and their application timings.

FIG. 4 is a diagram showing a schematic configuration of a plasma display device for driving a plasma display panel according to a driving method of the present invention.

5 is a diagram showing an example of a light emission drive format used in the drive control circuit 2 of the plasma display device shown in FIG.

6 is a diagram showing various drive pulses applied to the column electrodes and row electrodes of the PDP 10 according to the light emission drive format shown in FIG. 5, and their application timings.

FIG. 7 is a diagram showing timings of a subfield SF1, a preliminary period AU, and a subfield SF4.

FIG. 8 is a diagram showing another configuration of the plasma display device for driving the plasma display panel according to the driving method of the present invention.

9 is a diagram showing an example of a light emission drive format used in the drive control circuit 12 of the plasma display device shown in FIG.

10 is a diagram showing an internal configuration of a data conversion circuit 30 in the plasma display device shown in FIG.

11 is a diagram showing conversion characteristics in the first data conversion circuit 32. FIG.

FIG. 12 is a diagram showing an internal configuration of a multi-gradation processing circuit 33.

FIG. 13 is a diagram for explaining the operation of the error diffusion processing circuit 330.

FIG. 14 is a diagram showing an internal configuration of a dither processing circuit 350.

FIG. 15 is a diagram for explaining the operation of the dither processing circuit 350.

FIG. 16 is a diagram showing an example of a conversion table of a second data conversion circuit 34 and a light emission pattern.

17 is a diagram showing various drive pulses applied to the column electrodes and row electrodes of the PDP 10 according to the light emission drive format shown in FIG. 9, and their application timings.

18 is a diagram showing another example of a light emission drive format used in the drive control circuit 12 in the plasma display device shown in FIG.

19 is a diagram showing various drive pulses applied to the column electrodes and row electrodes of the PDP 10 according to the light emission drive format shown in FIG. 18, and their application timings.

FIG. 20 is a diagram showing another example of the conversion table of the second data conversion circuit 34 and a light emission pattern.

FIG. 21 is a diagram showing another example of the conversion table of the second data conversion circuit 34 and a light emission pattern.

[Explanation of symbols for main parts]

2,12 Drive control circuit 6,16 address driver 7,17 1st sustain driver 8,18 Second sustain driver 10 PDP 30 data conversion circuit

Continued front page    F-term (reference) 5C080 AA05 BB05 CC03 DD01 DD07                       DD08 EE19 EE29 FF12 GG08                       GG12 GG17 HH04 HH05 HH06                       JJ02 JJ04 JJ05

Claims (6)

[Claims] 1. An image of a plasma display panel in which discharge cells for forming pixels are formed at respective intersections of a plurality of row electrodes corresponding to a display line and a plurality of column electrodes arranged to intersect with the row electrodes. A driving method of a plasma display panel is driven for each of a plurality of sub-fields constituting one field of a signal, wherein each of the sub-fields sequentially outputs pixel data pulses based on the video signal for one display line, the column electrodes. The scanning pulse is sequentially applied to each of the row electrodes at the same timing as the application timing of each of the pixel data pulses while being applied to each of the row electrodes, thereby selectively selectively discharging each of the discharge cells to turn on the discharge cells. And an address step to be set to one of a discharge cell state and an off discharge cell state, and a weight of the subfield to each of the row electrodes. A sustaining step of repeatedly sustaining and discharging only the discharge cells in the lighting discharge cell state by repeatedly applying sustaining pulses a number of times corresponding to the number of times of light emission to cause the discharge cells to emit light, each of the subfields. The pulse widths of the scan pulse and the pixel data pulse whose application timing is early in the address step are narrower than the pulse widths of the scan pulse and the pixel data pulse whose application timing is late in the address step. A driving method of a characteristic plasma display panel. 2. The plasma display panel according to claim 1, wherein the pulse widths of the scan pulse and the pixel data pulse are changed according to the number of sustain pulses applied immediately before the addressing step. Driving method. 3. The pulse widths of the scan pulse and the pixel data pulse applied in the addressing step as the number of sustaining pulses applied in the light emission sustaining step of the one subfield immediately before the addressing step increases. The method for driving a plasma display panel according to claim 2, wherein the width is narrowed. 4. The pulse widths of the scan pulse and the pixel data pulse are increased as the number of sustain pulses applied in the light emission sustaining process of each of the subfields from the beginning of one field to immediately before the addressing process is increased. The driving method of the plasma display panel according to claim 1, wherein the driving method is narrowed. 5. A reset for initializing only all of the discharge cells to one of the lit discharge cell state and the extinguished discharge cell state prior to the addressing process only in the first subfield within the display period of one field. The method of driving a plasma display panel according to claim 1, further comprising a step, wherein the selective discharge is generated only in the address step in any one of the subfields of the subfields. 6. The number of the sub-fields constituting one field is N, and the number of the sub-fields in each of the n (n is an integer of 0 to N) consecutive from the beginning of the display period of one field is the same. 2. The method of driving a plasma display panel according to claim 1, wherein the intermediate discharge display of N + 1 gradation is performed by causing the sustain discharge only in the light emission sustaining process.