JP2005055807A - Ac type plasma display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an AC type plasma display device of a sustaining block driving system which simplifies the scale of a scan driving circuit or optimizes software control and with which the reduction of a pseudo-artifact level by the number of multiple sub-fields and the high luminance by the extension of sustaining light emission periods are possible and to provide its driving method. <P>SOLUTION: The AC type plasma display device 100 has sustaining block groups 21A to 21D, one unit of which consists of a connection group commonly connected with a plurality of sustaining electrodes 5 and scan driver groups 111A to 111H for applying a discharge voltage to the scan electrodes 4 in the respective sustaining blocks 21A to 21D. The number of the scan drivers 111A to 111H is set to integer times the number of the sustaining blocks 21A to 21D. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an AC drive type plasma display device using a plasma display panel (PDP) and having an electrode connection (matrix) structure, and a driving method thereof.

  A PDP that can be made large and thin is a display panel module that utilizes light emission associated with gas discharge and excitation light emission of a phosphor by ultraviolet light, and a three-electrode discharge structure in which three electrodes are provided per cell. The shape with is mainly used.

  A plasma display device is configured by providing a driving circuit for driving the PDP.

  FIG. 7 is a cross-sectional view schematically showing a three-electrode discharge structure in a PDP discharge cell. In the discharge cell 200, a pair of scan electrodes 202 and a sustain electrode 203 are formed on the front substrate 201 in a substantially parallel manner, and the scan electrode 202 and the sustain electrode 203 are covered with a dielectric layer 204 and a protective layer 205. ing. An address electrode 207 is formed on the rear substrate 206 facing the front substrate 201 so as to be orthogonal to the scan electrode 202 and the sustain electrode 203, and a dielectric layer 208 is formed thereon. ing. Further, a phosphor layer 209 is formed on the dielectric layer 208.

  In such a discharge cell 200, when a pulse voltage (writing pulse) higher than the discharge start voltage Vf is applied between the scan electrode 202 and the address electrode 207, discharge occurs. At that time, negative charges are accumulated on the surface of the phosphor layer 209 on the address electrode 207 to which a positive voltage is applied, and positive charges are accumulated on the surface in the vicinity of the protective layer 205 on the scan electrode 202 side to which a negative voltage is applied. Is accumulated. At the same time, negative charges are accumulated on the surface in the vicinity of the protective layer 205 on the side of the sustain electrode 203 to which a positive voltage is applied, as with the address electrode 207.

  Here, charges accumulated on the surfaces of the protective layer 205 and the phosphor layer 209 are referred to as wall charges, and a voltage induced by the wall charges is referred to as a wall voltage Vw. In addition, generating a wall charge by generating a discharge by applying a write pulse is called an address discharge, and a period of address discharge for a certain unit line is called an address period.

  In a state where positive charges are accumulated on the scan electrode 202 side and negative charges are accumulated on the sustain electrode 203 and address electrode 207 side, a pulsed high voltage Vi is applied between the scan electrode 202 and the sustain electrode 203, and the wall voltage Vw is applied. When the sum of the voltage Vi (= cell voltage Vc) exceeds the discharge start voltage Vf, discharge occurs. Once the discharge is started, the wall charges having positive and negative polarities are always re-accumulated in the electrodes from the case of the previous discharge, so that the periodic pulse voltage that alternately inverts to the scan electrode 202 and the sustain electrode 203 The discharge is maintained while applying. This discharge is called a sustain discharge, and the period during which the sustain discharge is performed is called a sustain period.

  When the applied voltage Vi is set lower than the discharge start voltage Vf and there is no wall voltage (wall charge), the cell voltage Vc = Vw + Vi = Vi <Vf, and the sustain discharge does not occur. In this manner, the selective discharge can be realized by determining the presence or absence of the subsequent sustain discharge depending on the presence or absence of the wall voltage Vw generated by the address discharge.

  FIG. 8 is a block diagram schematically showing the configuration of a conventional plasma display device. The PDP 210 includes a plurality of scan electrodes 202, a plurality of sustain electrodes 203, and a plurality of address electrodes 207. The plurality of address electrodes 207 are arranged in the vertical direction on the screen, and the plurality of scan electrodes 202 and the plurality of sustain electrodes 203 are arranged horizontally on the screen. They are arranged in pairs in the direction. Further, the plurality of sustain electrodes 203 are all made common to have the same potential. A discharge cell 200 is formed at the intersection of the scan electrode 202, the sustain electrode 203, and the address electrode 207, and functions as a pixel on the display screen.

  Further, the scan circuit 230 in the drive circuit 220 for driving the PDP 210 drives the plurality of scan electrodes 202 in order, the sustain circuit 240 drives the plurality of sustain electrodes 203 in common, and the address circuit 250 responds to the video data. The plurality of address electrodes 207 are simultaneously driven for one line.

  The PDP 210 and its drive circuit 220 constitute an AC type plasma display device 260.

  Here, an address / light-separation (ADS) driving method, which is a driving method for driving an AC plasma display device, will be described with reference to FIG.

  The TV signal generally displays images by superimposing 60 images per second, and an image is formed at a rate of about once every 16.6 msec. The time corresponding to 16.6 msec is defined as 1 TV field.

  As shown in FIG. 9, the 1TV field is divided into a plurality of subfields SF1, SF2 to SFN, and each subfield includes an address period Tadr and sustain discharge periods Tsus1, Tsus2 to TsusN. In the address period Tadr, the scan pulses corresponding to the number of lines to be displayed are sequentially scanned.

  FIG. 10 is an example of operation waveforms in the address period Tadr for the electrodes in the ADS drive method. As shown in FIG. 10, the address electrode 207 sets the data to be displayed on each line to the H level or the L level within the scan pulse width Tsc of each line in the address period Tadr. The address voltages corresponding to the H / L level are about 60 / 0V, respectively. Wall charges are accumulated in each pixel space on each line to which an H level voltage is applied to the address electrode 207. In the case of the L level, wall charges are not accumulated. In the pixel in which the wall charges are accumulated, the discharge is started and maintained in the subsequent sustain period Tsusi (i = 1 to N).

In the sustain discharge periods Tsus1, Tsus2 to TsusN of each subfield, the weighting ratio is a power of 2 (1 (= 2 ⁰ ): 2 (= 2 ¹ ): 4 (= 2 ² ): ˜: 2 ^{(N− 1)} It is set to be). By selectively combining the light emission times of the subfields, a multi-gradation display of 1 to 2 ^N stages is performed. For example, when N = 8, one TV field is composed of eight subfields, and 2 ⁸ = 256 gradation display is possible.

  However, in the ADS driving method, it is necessary to secure an address period Tadr of a certain period in each subfield, and at least (subfield number × Tadr) period does not emit light.

  The more subfields are added to increase the number of gradations and the higher the resolution display such as HD is, the more the non-light emission period increases, and the light emission time for one TV field decreases, resulting in a problem that luminance cannot be secured. . For example, in the case of driving to divide the screen up and down by the NTSC signal, the scanning pulse Tsc is set to about 8 μsec, and the address period Tadr = 8 × 480/2 = 1.92 (msec). When 6-bit multi-gradation display is used, the entire address period is 1.92 × 6 = 11.52 (msec), and the ratio of the light emission time to 1TV field 16.6 (msec) is (16.6-11. 52) /16.6=30.6%.

  Therefore, as one of means for ensuring high brightness, a maintenance block driving method as shown in Patent Document 1 has been proposed. In this method, all lines are divided for each sustain block to be scanned / maintained, and the address and the timing of sustain light emission are shifted for each sustain block. Hereinafter, an example of the ADS drive method in which the maintenance block is divided will be described.

  FIG. 11 is a block diagram schematically showing the configuration of the plasma display device. The PDP 210 includes a plurality of scan electrodes 202, a plurality of sustain electrodes 203, and a plurality of address electrodes 207. The plurality of address electrodes 207 are arranged in the vertical direction on the screen, and the plurality of scan electrodes 202 and the plurality of sustain electrodes 203 are arranged horizontally on the screen. They are arranged in pairs in the direction. A discharge cell 200 is formed at the intersection of the scan electrode 202, the sustain electrode 203 and the address electrode 207, and functions as a pixel on the display screen.

  Further, the entire lines of the scan electrode 202 and the sustain electrode 203 are divided into, for example, four sustain blocks from the first sustain block to the fourth sustain block, and the scan circuit 280 in the drive circuit 270 can be driven for each sustain block. Includes scan circuits 281a to 281d for each sustain block, and the sustain circuit 290 includes sustain circuits 291a to 291d for each sustain block. The address circuit 300 drives the plurality of address electrodes 207 for one line at a time according to the video data.

  The PDP 210 and its driving circuit 270 described above constitute an AC type plasma display device 310.

  FIG. 12 is a diagram showing an example of the timing for operating the drive voltages of the scan electrode 202, the sustain electrode 203, and the address electrode 207 in the plasma display device shown in FIG.

  First, in the first subfield SF1, after the initialization Init is performed on each sustain block of the first sustain block to the fourth sustain block, the address period Tadr of the first block is started and the sustain period Tsus is started. Continue. Next, after the lapse of a predetermined time from the start of the sustain period Tsus of the first sustain block, the sustain period Tsus of the second sustain block is started when about half of the sustain period Tsus of the first sustain block ends. 2. The address period Tadr of the sustain block is started. Then, after the address period Tadr of the second sustain block ends, the sustain period Tsus of the second sustain block is started. Thereafter, similarly to the second sustain block, the address period Tadr and the sustain period Tsus of the third and fourth sustain blocks are started. Similarly, after the second subfield SF2, the initialization Init, the address period Tadr, and the sustain period Tsus are sequentially executed with the timing shifted for each sustain block.

  Here, in the sustain block driving described above, the address period Tadr for each sustain block is a value obtained by dividing the time required to address all the lines by the number of sustain blocks to be divided. For example, in the example of FIG. Tadr is 1/4 of the time for all lines. Then, the address time can be shortened by the ADS operation for each sustain block, the sustain period can be advanced, the number of subfields can be increased, or the sustain period can be extended to increase the luminance.

In the above example, the sustain block drive divided into four has been described, but the number of sustain block divisions is not limited to four.
JP 2001-265281 A

  However, in the configuration shown in FIGS. 11 and 12, since the address electrode 207 is shared, if the last line M in the first subfield SF1 does not complete the address, the line 1 in the second subfield is The address cannot start. In other words, it is impossible in the ADS driving method to drive the sustain block such as starting the address of the first line in the next subfield ahead of the timing of addressing the last line in the previous subfield. It is.

  In addition, when sustain block division drive is used for the ADS drive method and the address period in the sustain block is shortened, the number of subfields is increased to reduce the pseudo contour level, or the sustain light emission period is increased to improve the luminance. In other words, the number of lines per unit maintaining block and the number of scan driver outputs used do not necessarily match, depending on the circuit scale, the number of lines, the number of subfields, and the luminance specification. Even if they do not match, it suffices to provide an unused output stage to drive the scan driver. However, in such a case, the number of necessary scan drivers increases, resulting in high costs.

  When the scan driver performs a scan operation across different sustain blocks, it is necessary to switch scan operation pulse signals such as clocks and shift pulses having different phases at a certain time. Adding an arbitration circuit for that purpose complicates the circuit configuration, increasing the circuit scale or increasing the burden of software processing. In addition, lines with different output sources are mixed in the maintenance block, which may cause display unevenness and noise.

  The present invention has been made in view of the above problems, and in an AC type plasma display device having a matrix structure having a plurality of sustain blocks and a scan driver for applying a discharge voltage to the scan electrodes of each sustain block, It is an object of the present invention to realize an AC type plasma display device capable of reducing cost by simplification or optimizing software control.

  To achieve the above object, an AC type plasma display apparatus according to the present invention includes a plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes, and a plurality of address electrodes, S scan drivers, and N sustain drivers. A plurality of sustain electrodes divided into N sustain blocks and connected to a sustain driver, and the plurality of scan electrodes divided into S blocks and a scan driver. The number of scan drivers is connected, and the number S of scan drivers is an integral multiple of the number N of sustain blocks.

  In order to achieve the above object, a driving method for an AC plasma display apparatus according to the present invention is a driving method for an AC plasma display apparatus according to the present invention, in which each field of a video signal is divided into a plurality of sub-fields. In each subfield using field drive, (1) discharge cell initialization step, (2) scan voltage waveforms including scan pulses whose phases are shifted to a plurality of scan electrodes in each sustain block are sequentially applied. And a selective writing step of applying a write pulse corresponding to the video signal to the address electrode at the timing of applying the scan pulse, and (3) applying periodically inverted periodic voltage pulses to the scan electrode and the sustain electrode. Are set in the order of the sustain emission process to be applied to the scan electrode, the sustain electrode, and the add The timing of the drive voltage pulse applied to the scan electrodes, characterized in that to sequentially shifting at regular time intervals for each maintenance block.

  According to the AC plasma display apparatus and the driving method thereof according to the present invention, a discharge voltage is applied to a plurality of sustain blocks each having a connection group in which a plurality of sustain electrodes are commonly connected, and to each scan electrode of each sustain block. In the matrix type AC plasma display device having a scan driver, the shift operation of the scan driver can be completed within the sustain block by making the number of scan drivers an integral multiple of the number of sustain blocks. Cost reduction by simplification or optimization of software control can be achieved.

  Furthermore, regarding an image display device including a plasma display that is currently undergoing significant technological innovation, if the present invention that reduces power consumption is used, it will be friendly to the global environment.

  Hereinafter, an AC type plasma display apparatus and a driving method thereof according to an embodiment of the present invention will be described.

(Embodiment 1)
FIG. 1 is a block diagram schematically showing an example of the configuration of an AC type plasma display apparatus according to Embodiment 1 of the present invention, and FIG. 2 shows a PDP used in the AC type plasma display apparatus shown in FIG. It is a cross-sectional perspective view which shows schematic structure of these.

  The AC type plasma display apparatus 100 has a configuration including a PDP 1 and a drive circuit 101 for driving the PDP 1.

  The front plate 2 of the PDP 1 includes a display electrode 6 formed of a scan electrode 4 and a sustain electrode 5 formed on one main surface of a transparent and insulating substrate 3 such as glass on the front side, and the display electrode. 6, and a protective layer 8 made of, for example, MgO that covers the dielectric layer 7. The scan electrode 4 and the sustain electrode 5 have a structure in which metal electrodes, for example, bus electrodes 4b and 5b made of Ag are stacked on the transparent electrodes 4a and 5a for the purpose of reducing electric resistance.

  The back plate 9 includes an address electrode 11 formed on one main surface of an insulating substrate 10 such as glass on the back side, a dielectric layer 12 covering the address electrode 11, and the dielectric layer 12. In this structure, the barrier ribs 13 are located at positions corresponding to the adjacent address electrodes 11 and the phosphor layers 14R, 14G, and 14B between the barrier ribs 13.

  The front plate 2 and the back plate 9 are configured such that the display electrodes 6 and the address electrodes 11 face each other across the partition wall 13 and the periphery outside the image display area is sealed with a sealing member. The discharge space 15 formed between the front plate 2 and the back plate 9 is filled with, for example, 5% Ne-Xe discharge gas at a pressure of 66.5 kPa (500 Torr). The intersection between the display electrode 6 and the address electrode 11 in the discharge space 15 operates as a discharge cell 16 (unit light emitting region).

  The drive circuit 101 includes a scan circuit 110, a sustain circuit 120, and an address circuit 130. The scan circuit 110 includes a scan driver group 111 having scan drivers 111A to 111H, and a timing arbitration circuit that controls sustain block driving. 112. Further, the sustain circuit 120 shares the M number of sustain electrodes 5 for every N sustain blocks, for example, and is driven by each of the sustain drivers 121A to 121D. The address circuit 130 is a driver circuit that drives the L address electrodes 11, and simultaneously, for each line, video data converted for each subfield is written as a write pulse in accordance with the scan pulse applied to the scan electrode 4. Output.

  Scan electrode 4 from line 1 to line M1, scan electrode 4 from line (M1 + 1) to line M2, scan electrode 4 from line (M2 + 1) to line M3, scan electrode 4 from line (M3 + 1) to line M4 Are respectively connected to the scan drivers (111A + 111B), (111C + 111D), (111E + 111F), and (111G + 111H). The scan driver 111A and the scan driver 111B, the scan driver 111C and the scan driver 111D, the scan driver 111E and the scan driver 111F, and the scan driver 111G and the scan driver 111H are cascade-connected. On the other hand, the sustain electrode 5 from line 1 to line M1, the sustain electrode 5 from line (M1 + 1) to line M2, the sustain electrode 5 from line (M2 + 1) to line M3, and the sustain electrode from line (M3 + 1) to line M4 The electrodes 5 are connected to the sustain drivers 121A, 121B, 121C, and 121D, respectively, and are connected in common within the sustain driver.

  That is, as many sustain block drive units as the number of sustain drivers are formed, the drive unit including the sustain driver 121A is the first sustain block 21A, the drive unit including the sustain driver 121B is the second sustain block 21B, and the sustain driver. The drive unit including 121C is the third sustain block 21C, and the drive unit including the sustain driver 121D is the fourth sustain block 21D. A scan driver that applies a discharge voltage to the scan electrodes of each sustain block, that is, a scan driver (111A + 111B) for the first sustain block 21A, a scan driver (111C + 111D) for the second sustain block 21B, and a third A scan driver (111E + 111F) is connected to the sustain block 21C, and a scan driver (111G + 111H) is connected to the fourth sustain block 21D.

  The address circuit 130 converts data given serially for each subfield into parallel data, and drives the plurality of address electrodes 11 based on the parallel data.

  In the first sustain block 21A, the scan circuit 110 applies an initialization pulse, a write pulse, and a sustain pulse to the scan electrodes 4 from the line 1 to the line M1 in accordance with the discharge control timing signal output from the timing arbitration circuit 112. . Similar pulses are applied to the second sustain block 21B, the third sustain block 21C, and the fourth sustain block 21D, respectively.

  In each of the first sustain blocks 21A, the sustain driver 121A drives the sustain electrodes 5 from the line 1 to the line M1 according to the discharge control timing signal. Similar pulses are applied to the second sustain block 21B, the third sustain block 21C, and the fourth sustain block 21D, respectively.

  Here, the relationship between the scan driver configuration and the maintenance block configuration will be described. Assuming that the total number of lines M (constant) of the entire screen and the number of scan driver outputs SO (constant), the number S of scan drivers is “S = M / SO”. Further, the number of lines NBL per unit sustain block is “NBL = M / NB” with respect to the number of sustain blocks to be driven NB. If the total output number of the scan driver is equal to the total number of lines, “S × SO = NB × NBL” is established. If the minimum drive line of the sustain block is set as the scan driver output number SO, it can be expressed as “NBL = a × SO + b”. However, a is an integer and 0 ≦ b <SO. Then, the number S of scan drivers necessary for driving all M lines can be expressed as “S = NB × NBL / SO = NB × (a + b / SO)” from the relational expression described above.

  Here, in the above formula, the following two cases are conceivable.

  (1) When b ≠ 0, S is a real number, and there is a possibility that the scan driver output may straddle between different sustain blocks. For example, a new timing arbitration that places an interval in the scan pulse shift operation in the scan circuit 110 A circuit is required and the circuit configuration becomes complicated, or the burden of software processing such as complicated control of scan operation pulses for driving the scan drivers 111A to 111H increases.

  (2) When b = 0, S and NB are directly proportional, and S is an integer. That is, the number of scan drivers becomes an integral multiple of the number of sustain blocks, and the scan pulse shift in the sustain block is completed in the sustain block drive, thereby minimizing the number of scan drivers, and the configuration of the scan circuit 110 and timing control by software Can be simplified and the cost can be reduced. In addition, it is possible to eliminate the possibility of screen problems such as display variations due to the scanning operation of the scan drivers 111A to 111H.

  FIG. 3 is a diagram for explaining the difference in configuration in the cases (1) and (2), and is an example in which the number of lines is 19. In FIG. 3, a configuration A composed of scan drivers 111A to 111H and a configuration B composed of scan drivers 111A ′ to 111J ′ are considered. When driving with the four sustain blocks of the sustain blocks 21A to 21D, for example, the first sustain block 21A and the second sustain block 21B have different addresses and timing of sustain light emission. In the case of Configuration B, the scan driver 111C ′ scans across the first sustain block 21A and the second sustain block 21B. At this time, it is necessary for the scan driver 111C ′ to switch scan operation pulse signals such as clocks and shift pulses having different phases at a certain point in time during a series of scan operation periods. Adding a timing arbitration circuit for that purpose complicates the circuit configuration, increasing the circuit scale or increasing the burden of software processing. In addition, lines with different output sources are mixed in the maintenance block, which may cause display unevenness and noise. As in the configuration A, when the number of scan driver output stages is proportional to the number of line units for driving the sustain block, that is, when the number of drive blocks to be driven and the number of scan drivers are an integral multiple, scanning is performed in each of the sustain blocks of the sustain blocks The shift operation is completed, and the configuration of the scan circuit 110 can be simplified, the control can be optimized, and the cost can be reduced.

(Embodiment 2)
A second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a timing diagram showing an example of a driving method of the scan electrode 4, the sustain electrode 5, and the address electrode 11 in the plasma display device shown in FIG.

  As shown in FIG. 4, each field is divided into a plurality of subfields. Each subfield includes an initialization period 31 in which a setup operation for adjusting wall charges is performed, an address period 32 in which address discharge is performed, and a sustain period 33 in which sustain discharge is performed. Each subfield has a different sustain period 33. By changing the lighting period of each subfield, for example, gradation display of 256 gradations is performed.

  In the initializing period 31, a weak initializing discharge occurs, and a weak wall voltage is accumulated on each wall surface of the discharge cell 16. In the address period 32, a write pulse that is turned on or off according to the video signal is applied to each address electrode 11 by the address circuit 130, and in synchronization with this write pulse, the scan drivers 111A to 111H of the configuration A shown in FIG. Scan pulses are sequentially applied to the scan electrodes 4 by the scan drivers 111A ′ to 111J ′ of the configuration B.

  At this time, the voltage between the address electrode 11 and the scan electrode 4 corresponding to the discharge cell 16 to be displayed is a voltage obtained by adding the write pulse voltage and the scan pulse voltage, and the scan electrode 4 and the address in the initialization period 31. The wall voltage accumulated in each of the electrodes 11 is further added. Therefore, an address discharge occurs between the address electrode 11 and the scan electrode 4, and a wall voltage is selectively accumulated in each electrode.

  Next, in the sustain period 33, a sustain pulse is applied to the scan electrode 4 by the scan drivers 111 </ b> A to 111 </ b> H or the scan drivers 111 </ b> A ′ to 111 </ b> J ′. At this time, the voltage between the scan electrode 4 and the sustain electrode 5 in the discharge cell 16 in which the address discharge has occurred is the sustain pulse voltage Vsus between the scan electrode 4 and the sustain electrode 5 accumulated in the address period 32. The wall voltage is added. Therefore, a sustain discharge occurs between the scan electrode 4 and the sustain electrode 5 in the discharge cell 16 in which the address discharge has occurred. In the discharge cell 16 in which the sustain discharge has occurred, the polarity is opposite to that in the previous discharge. The wall voltage is accumulated. Thereafter, the sustain discharge is performed while the sustain pulses alternately inverted are periodically applied to the scan electrode 4 and the sustain electrode 5. Similarly in the second subfield and thereafter, the address discharge is selectively performed and the sustain discharge is performed.

  Next, it is maintained by the scan circuit 110 including the scan drivers 111A to 111H of the configuration A or the scan drivers 111A ′ to 111J ′ of the configuration B shown in FIG. 3, the sustain circuit 120 including the sustain drivers 121A to 121D, and the address circuit 130. The discharge timing is controlled for each block as follows.

  That is, first, in the first subfield SF1, the initialization period 31 is started for each of the maintenance blocks 21A, 21B, 21C, and 21D. Thereafter, the address period 32 of the first sustain block 21A is started, and then the sustain period 33 is started. The initialization period 31 of the second maintenance block 21B is started at a certain time interval from the first maintenance block 21A. Similarly, in the case of the third sustain block 21C and the fourth sustain block 21D, the initialization period 31 is started at regular time intervals.

  Next, a predetermined time has elapsed from the start of the maintenance period 33 of the first maintenance block 21A so that the maintenance period 33 of the second maintenance block 21B is started when half or more of the maintenance period 33 of the first maintenance block 21A has ended. After the elapse, the address period 32 of the second sustain block 21B is started, and after the address period 32 of the second sustain block 21B is ended, the sustain period 33 of the second sustain block 21B is started. Thereafter, similarly to the second sustain block 21B, the initialization period 31, the address period 32, and the sustain period 33 of the third sustain block 21C and the fourth sustain block 21D are started in order.

  In the second subfield SF2, the initialization period 31 of the first sustain block 21A starts after the sustain period 33 of the first subfield SF1 of the second sustain block 21B ends. Thereafter, the address period 32 of the first sustain block 21A is started, and after the address period 32 of the first sustain block 21A is ended, the sustain period 33 of the first sustain block 21A is started. When the address period 32 of the first sustain block 21A ends, the initialization period 31 of the second sustain block 21B starts. After the end of the initialization period 31 of the second sustain block 21B, the address period 32 of the second sustain block 21B is started, and after the address period 32 of the second sustain block 21B ends, the sustain period 33 of the second sustain block 21B. Is started. Thereafter, similarly to the second sustain block 21B, the initialization period 31, the address period 32, and the sustain period 33 of the third and fourth sustain blocks 21C and 21D are started.

  Here, FIG. 4 illustrates an example of the timing at which the drive voltages of the address electrodes 11, the scan electrodes 4, and the sustain electrodes 5 are applied when another sustain block performs address discharge during the sustain period of a certain sustain block. For example, in the first subfield SF1, the address period 32 of the second sustain block 21B is set in the sustain period 33 of the first sustain block 21A. At this time, the sustain pulse is applied to the scan electrode 4 and the sustain electrode 5 in the sustain period 33 of the first sustain block 21A. On the other hand, during the sustain period 33 of the first sustain block 21A, the scan electrode 4 is 0V and the sustain electrode 5 is in the sustain voltage peak voltage period, corresponding to the scan pulse applied to each scan electrode 4, A write pulse is applied to the address electrode 11 of the second sustain block 21B.

  Accordingly, even in the configuration in which the address electrode 11 is used in common for each of the sustain blocks 21A, 21B, 21C, and 21D, the inter-sustain block interference of the drive pulse applied to each electrode is eliminated, so that the sustain discharge and the address are performed. The discharge can be performed stably in parallel. Further, the time can be effectively utilized in the second and subsequent subfields by devising a similar method of adding drive pulses. Here, when the number of lines per unit sustain block and the number of scan driver output stages are proportional, that is, when the number of sustain blocks to be driven and the number of scan drivers are an integral multiple, scanning is performed in each sustain block of the sustain blocks 21A to 21D. The shift operation is completed, the circuit scale and software processing are simplified, and interference between maintenance blocks due to the scanning operation straddling can be eliminated. In such a sustain block driving method, the ratio of the sustain period 33 in one field is increased to increase the brightness, or the number of subfields is increased by shortening the time, which is effective in improving the number of gradations and reducing the pseudo contour. Demonstrate.

(Embodiment 3)
Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 shows a method of distributing the number of lines of each sustain block according to the time width of the scan pulse.

  The write characteristic described below is that an address discharge is generated between the scan electrode 4 and the address electrode 11 by the write pulse applied to the address electrode 11 at an appropriate timing with respect to the scan pulse applied to the scan electrode 4. This means whether wall charges among the scan electrode 4, the sustain electrode 5, and the address electrode 11 are accumulated with a predetermined charge amount. Good write characteristics refer to a state in which address discharge is reliably generated within a certain time and wall charges hold a predetermined accumulation amount and have a predetermined wall voltage, and write characteristics are poor. This refers to a state in which the generated time variation is large and a predetermined wall charge cannot be held.

  In the sustain block drive, the number of lines of each sustain block that is simultaneously driven by ADS is a small value with respect to the total number of lines, and the configuration lines are initialized in each sustain block. Although the writing characteristic is rarely distributed in the display screen, in the case of a PDP having a very bad writing characteristic, there is a tendency that writing becomes more difficult as the maintenance block has a slower scanning order. As one of the factors, apart from the wall charges between the scan electrode 4, the sustain electrode 5 and the address electrode 11 generated by the initialization at the start of the field, the space charge (priming particles) floating in the discharge space decreases with time. It is considered that the probability of occurrence of writing, that is, address discharge is lowered.

  In such a case, in each of the first sustain block 21A to the fourth sustain block 21D according to the first and second embodiments of the present invention, the first sustain block 21A with the earlier scanning order has relatively good write characteristics, and the scan The address discharge is reliably generated within a certain time with the width of the pulse 41A. On the other hand, in the line (M3 + 1) to the line M4 of the fourth sustain block 21D that is scanned late, the probability that the address discharge will occur within the predetermined time is low with the width of the scan pulse 41A. Thus, it is necessary to reliably generate an address discharge by widening the pulse width. That is, the scan pulse 41A in the first sustain block 21A is set to a time width that ensures address discharge, and the fourth sustain block 41D has a time width wider than the scan pulse 141A so that the address discharge is surely generated. By setting, it is possible to absorb variations in write characteristics.

  When the number of lines in each of the sustain blocks 21A to 21D is the same, for example, the length of the address period itself is different in the address period 42A of the first sustain block 21A and the address period 42D of the fourth sustain block 21D. On the other hand, the sustain block driving method is contradictory because the number of subfields or the sustain period can be increased if the address period is as constant and short as possible. Therefore, in each of the sustain blocks 21A to 21D, for example, by setting the number of constituent lines so that the address periods are the same, it is possible to take advantage of the sustain block drive. Note that the number of individual scan drivers for each of the maintenance blocks 21A to 21D may be one.

  In addition, when setting the number of subfields that may slightly change the address period, the subfield order in the sustain block is improved according to the write characteristics that are improved by the priming effect by the sustain discharge each time the subfields are overlapped. As the value becomes higher, the address period may be shortened.

(Embodiment 4)
Embodiment 4 of the present invention will be described with reference to FIG. FIG. 6 is a diagram showing the relationship between the total address time and the subfield period when driving with the above-described four sustain blocks according to the fourth embodiment of the present invention.

  As shown in the first to third embodiments of the present invention, when each sustain block of the first sustain block 21A, the second sustain block 21B, the third sustain block 21C, and the fourth sustain block 21D is individually ADS-driven. In FIG. 6, all address periods 51 in which video data is selectively written to all pixels of all lines M are an initialization period 31 and an address period 32 ((address period 52 for one line) × (number of lines per sustain block). )) And the number of maintenance blocks.

  Here, the time relationship between the address period 51 of the fourth sustain block 21D of the first subfield and the address period 51 of the first sustain block 21A of the second subfield will be described. When the timing for writing the last line M4 of the fourth sustain block 21D of the first subfield is completed before the initialization period 31 of the first sustain block 21A of the second subfield is started, all lines M are written. The address periods 52 of the two do not overlap on the time axis. That is, if all the address periods 51 are shorter than the first subfield period 53, the ADS drive can be performed for each of the first sustain block 21A, the second sustain block 21B, the third sustain block 21C, and the fourth sustain block 21D. .

  Even if the address period 51 written to the last line M4 of the fourth sustain block 21D of the first subfield overlaps with the initialization period 31 of the first sustain block 21A of the second subfield, the initialization pulses of each other This can be avoided by adjusting the timing so that the write pulses do not overlap. Further, by making the maintenance allocation period 55, which is the sum of the maintenance period 33 and the maintenance suspension period 54, constant in each subfield, the above effect can be enhanced. Even when the sustain period 33 of each subfield is weighted, the above effect can be maintained by adjusting the pause period 54 to make the maintenance allocation period 55 constant.

  Even if the maintenance allocation period 55 is not constant in each subfield and the maintenance period 33 of each subfield has a weight of, for example, a power of 2, it is independent in each maintenance block as long as the condition indicated by the present invention is satisfied. ADS driving can be performed.

  The same effect can be obtained not only in this example but also in the address periods 51 between the sustain blocks adjacent in the scanning order.

  On the other hand, if the condition indicated by the present invention is not satisfied, for example, the initialization period 31 of the first sustain block 21A of the second subfield starts after the start or after the address period 52 of line 1 When the timing for writing the last line M4 of the fourth sustain block 21D is completed, the address electrode 13 must be time-division driven in the subfield.

  Therefore, in the fourth embodiment of the present invention, the predetermined time interval for shifting the application timing of each pulse between the sustain blocks is shortened to eliminate the overlapping time of the initialization period 31 minutes, and each of the sustain blocks 21A, 21B, When each address period 32 is set continuously in 21C and 21D, the initialization period 31 and the address period 32 overlap on the time axis, but the application timing of each other pulse is adjusted within the overlap period. To avoid mutual interference.

  In addition, in the case of erasing write driving in which the sustain light emission is stopped by writing a write pulse corresponding to video data to the address electrode 11, only the first initialization of one field is set, so the number of subfields and the address are increased. This is advantageous in that there is no overlapping period between the period 32 and the initialization period 31.

  In the first to fourth embodiments of the present invention, the example in which the plurality of scan electrodes 4 and the sustain electrodes 5 are divided into four groups is shown, but the number of divisions is not particularly limited to this example, and is divided into two, six, Other division numbers such as division and 8-division may be used. In addition, the minimum number of lines of the scan electrode 4 and the sustain electrode 5 included in one group is preferably, for example, 16 or more from the viewpoint of the circuit configuration and the like. In addition, for example, in the case of an AC type plasma display device with a 480-line VGA (Video Graphics Array) specification, it is preferable that the number of lines in one group is 30 by dividing into six. In this case, there is a high probability that a similar image enters each group, the drive patterns in each group are the same, and the life of the drive circuit can be extended.

  In the above example, the number of scan drivers is twice the number of sustain blocks, but the same effect can be obtained if the number of sustain blocks is an integer multiple.

  The descriptions of the first subfield and the second subfield in Embodiments 1 to 4 of the present invention are not limited to those subfields, and the same applies to the third subfield and thereafter. be able to. Moreover, you may use combining the driving method shown in Embodiment 2-4 of this invention.

  In addition, although not illustrated, the present invention shown in Embodiments 1 to 4 can be variously modified without departing from the gist thereof.

  As described above, the present invention provides a matrix structure AC having a plurality of sustain blocks each having a connection group in which a plurality of sustain electrodes are commonly connected, and a scan driver that applies a discharge voltage to the scan electrodes of each sustain block. By reducing the number of scan drivers to an integral multiple of the number of maintenance blocks for a plasma display device, the shift operation of the scan driver is completed within the maintenance block, thereby reducing costs by simplifying the scan circuit configuration or controlling the software. It is possible to provide a plasma display device that can optimize the above.

  Further, by reducing power consumption, a plasma display device that is friendly to the global environment can be provided.

1 is a block diagram showing a schematic configuration of an AC type plasma display device according to Embodiment 1 of the present invention. Cross-sectional perspective view showing schematic configuration of plasma display panel The figure for demonstrating the difference in the scan driver structure with respect to a maintenance block group FIG. 5 is a timing chart showing an example of a driving method of scan electrodes, sustain electrodes, and address electrodes of an AC type plasma display apparatus according to Embodiment 2 of the present invention. The figure which shows distribution of the line number of each sustain block corresponding to the time width of the scan pulse of the AC type plasma display apparatus by Embodiment 3 of this invention. Correlation diagram between total address time and subfield period in sustain block driving of AC type plasma display apparatus according to Embodiment 4 of the present invention Sectional drawing which shows typically the 3 electrode discharge structure in the discharge cell of a plasma display panel Block diagram showing a schematic configuration of a conventional plasma display device Diagram for explaining the ADS drive system The figure which shows an example of the operation waveform with respect to each electrode in an ADS drive system A block diagram showing a schematic configuration of a plasma display device in an ADS drive system in which a maintenance block is divided The figure which shows an example of the timing chart of the ADS drive system which carried out the maintenance block division | segmentation

Explanation of symbols

1 Plasma display panel (PDP)
4 Scan electrode 5 Sustain electrode 11 Address electrode 21A, 21B, 21C, 21D Maintenance block 111A, 111B, 111C, 111D, 111E, 111F, 111G, 111H Scan driver 121A, 121B, 121C, 121D Sustain driver

Claims (12)

A plasma display panel having a plurality of scan electrodes, a plurality of sustain electrodes, and a plurality of address electrodes, and a drive circuit having S scan drivers and N sustain drivers, wherein the plurality of sustain electrodes are N The plurality of scan electrodes are divided into S blocks and connected to the sustain driver, and the plurality of scan electrodes are divided into S blocks and connected to the scan driver, and the number of scan drivers S is an integer of the number of sustain blocks N AC type plasma display device characterized by being doubled. The AC type plasma display apparatus according to claim 1, wherein the number of sustain electrodes in the sustain block is the same in all the sustain blocks. 3. The AC type plasma display apparatus according to claim 1, wherein the sustain electrodes in the sustain block are selected so as not to be adjacent to each other in the plasma display panel. 2. The AC type plasma display apparatus according to claim 1, wherein the number N of sustain blocks is a power of two. 5. The driving method for an AC type plasma display device according to claim 1, wherein subfield driving is performed by dividing each field of a video signal into a plurality of fields, and (1) a discharge cell in each subfield. (2) A scan voltage waveform including a scan pulse whose phase is shifted is sequentially applied to a plurality of scan electrodes in each sustain block, and is applied to the address electrode at the timing of applying the scan pulse. And a selective writing step of applying a writing pulse corresponding to the video signal, and (3) a sustain light emitting step of applying alternately inverted periodic voltage pulses to the scan electrode and the sustain electrode, and The timing of the drive voltage pulse applied to the scan electrode, sustain electrode and address electrode is maintained. The driving method of the AC type plasma display device, characterized in that to sequentially shifting at a predetermined time interval and. 6. The AC according to claim 5, wherein the initialization step is set only in the first subfield, and is an erase write for stopping the sustain light emission step continued from the previous subfield in the selective write step. Type plasma display device driving method. 6. The method of driving an AC type plasma display apparatus according to claim 5, wherein a period of the selective writing process is shortened in the order of subfields. 6. The method of driving an AC type plasma display apparatus according to claim 5, wherein the number of sustain electrodes constituting the sustain block is changed in accordance with the time width of the scan pulse. 9. The driving method of an AC type plasma display apparatus according to claim 8, wherein the time width of the scan pulse is widened in the order of scanning, and the number of sustain electrodes per sustain block is reduced. The time interval for shifting the timing of the drive voltage pulse applied to each sustain block is such that the selective writing process of the sustain block to be scanned is completed before the selective writing process of the sustain block to be scanned next is started. 6. The method of driving an AC type plasma display apparatus according to claim 5, wherein the time interval is long. 6. The method of driving an AC type plasma display apparatus according to claim 5, wherein the sustain light emission process is divided into a light emission period and a rest period, and a required time of the sustain light emission process is made constant in each subfield. 12. The driving method for an AC type plasma display device, wherein at least one driving method is used in combination among the driving methods for the AC type plasma display device according to claim 5.

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