JPH05313599A - Gradation drive system for display plate - Google Patents

Abstract

PURPOSE:To improve a display ratio in one field and to reduce the size of a circuit by dividing one cycle of a write period into the number of sub fields, allocating divided respective periods as the write periods of respective sub fields and displaying from the sub field with a short display hold period successively. CONSTITUTION:The display periods of respective sub fields are shown by T, T/2, T/4, T/8, T/16, T/32, T/64, T/128 and the display of 256 gradation are performed by the combination of selected sub fields. One period F of one field is not divided to the divided sub fields and further a no display period from the end of respective sub fields to the start of the next sub field becomes short. Then, a data signal in a driving basic signal is delayed till the write timing of respective sub fields. That is, regarding the sub field F1 operating first as a reference, the data signals exist till the display start of the sub fields of F2-F8 are stored.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gray scale driving method for a display panel, and more particularly to a driving method for a memory type display panel.

[0002]

2. Description of the Related Art In a gradation driving method for a memory type display panel such as a plasma display and an electroluminescent display, one field display period having a period of about 18 msec or less is divided into a plurality of subfield periods according to the number of gradations. A method is known in which the luminance is divided into subfields and the light emission luminance in each subfield is set to a different value, and the average luminance of each pixel is changed by changing the combination of the subfields to emit light for gradation display. ..

FIG. 4 is an example of a time chart of a conventional gradation driving method. Where F is one field period, F
Reference numerals 1'-F8 'indicate subfield periods, S1-Sm indicate m operation lines, and the operation is sequentially repeated from S1 to Sm. T'represents the light emitting period in the subfield F1 ', and the light emitting period in the subfield F2' is T '/ 2,
F3 'is T' / 4, and hereinafter F4 'to F8' are T '/ 8, T' / 16, T '/ 32, T' / 64, T ', respectively.
The light emission period is set to / 128. These F1 '~
By combining the subfields of F8 ', 1
It is possible to create 256 types of average luminance in the field period F. By the way, the drive from the start to the end of light emission in each subfield is temporally divided into three periods. The first is a write period, the second is a sustain period, and the third is an erase period.

FIG. 5 shows an example of drive waveforms of an AC memory type plasma display. This is an example of a plasma display (FIG. 3) having a three-electrode structure that is driven by one pixel and three types of display pulses. The sustain pulse, scan pulse, and data pulse in FIG. 5 are voltages applied to the sustain electrode 6, scan electrode 5, and data electrode 3 in FIG. 3, respectively. In the scan pulse 1 ', Pw represents a write pulse, Psus represents a sustain pulse, and P _E represents an erase pulse. That is, by applying Pw and the data pulse at the same time, discharge is generated and light emission is achieved. By repeatedly applying the sustain pulse and Psus before the electric charges generated by this discharge recombine and disappear, the discharge is repeated. Sustain pulse and Psu
The discharge maintained by s continues until P _E is applied and the charge is neutralized. Therefore, the application period of Pw and the data pulse is the write period, the sustain period is just before the application of P _E after the write period, and the erase period is the application period of P _E. P
w is sequentially applied to each scan electrode in a time division manner, and a data pulse is applied to the data electrode in accordance with the application of Pw to select discharge / non-discharge for each display cell.

[0005]

In this conventional gradation driving method, the display period in one field (F) is T '=
Even if it is set to F1 'and displayed in all subfields, (255/128) T' ≈ F (= 8T ')
2T 'is the maximum. That is, the display rate of 25% is the highest in terms of time.

Further, in order to write data in each subfield, it is necessary to transfer the display data to the drive circuit at the write timing. However, in the basic signal for driving, the data signal of the number of subfields (8 in the conventional example) is parallelly arranged as data for each display cell, and sequentially from the display cell in the upper line to the display cell in the lower line on the display screen. It is generally sent in a time-sharing manner. Therefore, in order to match the data signal timing of the driving basic signal with the data timing of each subfield, a frame memory for storing the data of the entire screen is required, which increases the circuit scale.

[0007]

In the gradation driving method for a display panel of the present invention, one cycle of the writing period is divided into the number of subfields, and each divided period is applied as the writing period of each subfield. In addition, the display is sequentially performed from the subfield having the shortest display maintenance period.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a time chart according to the driving method of the present invention.
FIG. 2 shows an example of the drive waveform. In FIG. 1, T,
T / 2, T / 4, T / 8, T / 16, T / 32, T / 6
4, T / 128 represents the display period of each subfield as in the conventional technique, and 256 gradations can be displayed depending on the combination of the selected subfields. The difference from the prior art is that one cycle F of the field is not divided into the sub-fields, and the non-display period from the end of each sub-field to the start of the next sub-field is shortened.

By the way, T _H1 in the drive waveform of FIG.
T _H2 , T _H3 , ... _Are values obtained by dividing the field period F by the number of scanning lines. Further, T _{W1 to} T _{W8, which} is obtained by dividing these T _H1 , T _H2 , T _H3 , ... In eight, is the period of the sustain pulse and also each writing period of the subfields F1 to F8. The display process of writing, maintaining and erasing is similar to that of the prior art.

By the way, the scanning pulse 1 is the drive waveform of the scanning line S1, and in this scanning pulse 1, T _H1 is the display period of the subfield F1, and from the writing pulse P _W1 to the erasing pulse P _E1 in T _W 1. Up to this display period. Since PE1 of the subfield F1 is contained within T _H1 , the display of the subfield F2 starts at the next T _H2 . At the same T _H2 , which is also the display period of the subfield F1 in the scan pulse 2, since the write pulse period is T _W1 , the write pulse P of the scan pulse 1 is obtained.
It does not overlap with _W2 . In the same manner, the display of subfields is sequentially shifted to the scanning pulses 3, 4 ...

Here, the non-display period from the subfield of the current display to the subfield of the next display is from the application of the erase pulse of the subfield of the current display to the application of the write pulse of the subfield of the next display. Is the period. When the erase pulse of the subfield of the current display exists at T _Hx , the write pulse of the subfield of the next display can be applied to T _{H (x + 1)} , so that T _H1 and T _H2 during this non-display period. It is possible to suppress each cycle within twice. By the way, in order to write data in each subfield, it is necessary to transfer the display data to the drive circuit at the write timing.

The present invention can be realized by delaying the data signal of the driving basic signal described above until the writing timing of each subfield. That is, it suffices to store the data signals existing until the display starts in each of the subfields F2 to F8 with reference to the first operating subfield F1. Moreover, since the sub-fields having a short display sustain period are sequentially displayed, the capacity of the element for storing the data signal can be reduced.

[0013]

As described above, according to the present invention, one cycle of the writing period is divided into the number of subfields, each divided period is assigned as the writing period of each subfield, and the subfield having a short display sustain period is used. Since the display is sequentially performed from 1), there is an effect that the display rate in one field is improved and the circuit scale of the data signal control unit, particularly the memory circuit unit is reduced.

[Brief description of drawings]

FIG. 1 is a time chart of an embodiment of the present invention.

FIG. 2 is a drive waveform according to an embodiment of the present invention.

FIG. 3 is a structural diagram of an AC memory type plasma display having a three-electrode structure.

FIG. 4 is a time chart of a conventional AC memory type plasma display.

FIG. 5 is a drive waveform of a conventional IC memory type plasma display.

[Explanation of symbols]

 1 Front Glass Plate 2, 7 Dielectric Film 3 Data Electrode 4 Partition 5 Scanning Electrode 6 Sustaining Electrode 8 Rear Glass Plate

Claims (1)

[Claims] 1. A drive of a display panel having a plurality of write electrode groups and a plurality of sustain electrode groups orthogonal to the write electrode groups, wherein the intersection of the write electrodes and the sustain electrodes emits light, and writing of display is performed by a line. In a driving method that sequentially performs time division operation, has a plurality of display periods with different display sustain periods, and performs gradation display by a combination of selection / non-selection of each display period,
One cycle of the write period is divided into the number of display periods having different display sustain periods, the divided write periods are allocated to the write voltage application periods of each display period, and the display period is sequentially displayed from the short display sustain period. A gradation driving method for a display plate characterized by being carried out.