JP2007003706A - Pixel circuit, display device, and driving method of pixel circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pixel circuit that can prevent variance in luminance during high-luminance display without impairing signal write response during low-luminance display, and to provide a display device and a driving method of the pixel circuit. <P>SOLUTION: The pixel circuit 101 includes a TFT 111 and an organic EL light emitting element 113 arranged in series between a power source potential line VCCL and a reference potential GND, a TFT 112 connected between a signal line SGL and the gate of the TFT 111, and a capacitor C111 connected between the gate of the TFT 111 and the power source potential line VCCL. A one-field period is provided with N (8 or 10) sub-field SF periods to perform N-bit (2<SP>N</SP>gray scale) display, and a scan driver 104 generates signals of the N subfields SF1 to SFN; when the scan driver 104 preforms the selection, a high-level or low-level signal is applied from a data driver 103 to a signal line SGL and the signals are input to pixels in the timing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a pixel circuit having an electro-optic element whose luminance is controlled by a signal line including an active matrix display device such as an organic EL (Electroluminescence) display device and an LCD (Liquid Crystal Display device), a display device, and driving of the pixel circuit It is about the method.

In an active matrix display device, an electro-optical element such as a liquid crystal cell or an organic EL element is used as a display element of a pixel.
Among them, the organic EL element has a structure in which a layer made of an organic material, that is, an organic layer is sandwiched between electrodes.
In this organic EL element, by applying a voltage to the element, electrons from the cathode and holes from the anode are injected into the organic layer. As a result, the electrons and holes are recombined to generate light. This organic EL element has the following features.

(1) Since a luminance of several hundred to several tens of thousands of cd / m ² can be obtained by driving at a low voltage of 10 V or less, power consumption can be reduced.
(2) Since it is a self-luminous element, the contrast of the image is high and the response speed is fast, so that the visibility is good and it is also suitable for displaying moving images.
(3) It is an all solid state element having a simple structure, and the element can be made highly reliable and thin.

  An organic EL display device using an organic EL element having these features as a pixel display element (hereinafter referred to as an organic EL display) is considered promising as a next-generation flat panel display.

  By the way, as a driving method of the organic EL display, there are a simple matrix method and an active matrix method. Among these methods, the active matrix method has the following features.

(1) An active matrix system that can hold light emission of an organic EL element in each pixel for one frame period is suitable for high definition and high luminance of an organic EL display.
(2) Since a peripheral circuit using a thin film transistor can be formed over a substrate (panel), the interface with the outside of the panel can be simplified and the function of the panel can be enhanced.

In this active matrix organic EL display, a polysilicon thin film transistor (TFT) using polysilicon as an active layer is generally used as a transistor as an active element.
This is because the polysilicon TFT has a high driving capability and can be designed to have a small pixel size, which is advantageous for high definition.

By the way, it is well known that the polysilicon TFT has the above-mentioned features, but has a large variation in characteristics.
Therefore, in the case of using a polysilicon TFT, it is a big problem in an active matrix type organic EL display using a polysilicon TFT to suppress the characteristic variation and to compensate for the TFT characteristic variation in a circuit. This is due to the following reason.

  That is, in a liquid crystal display using a liquid crystal cell as a pixel display element, the luminance data of each pixel is controlled by a voltage value, whereas in an organic EL display, the luminance data of each pixel is controlled by a current value. It is because the structure to control is taken.

  FIG. 1 is a circuit diagram illustrating a configuration example of a pixel circuit of an active matrix organic EL display (see, for example, Patent Documents 1 and 2).

As shown in FIG. 1, the pixel circuit 10 arranged in a matrix has a p-channel TFT 11, an n-channel TFT 12, a capacitor C <b> 11, and a light emitting element 13 composed of an organic EL element (OLED).
The TFT 11 of each pixel circuit 10 has a source connected to the power supply potential line VCCL and a gate connected to the drain of the TFT 12. The organic EL light emitting element 13 has an anode connected to the drain of the TFT 11 and a cathode connected to a reference potential (for example, ground potential) GND.
The TFT 12 of each pixel circuit 10 has a source connected to the signal line SGL of the corresponding column and a gate connected to the scanning line SCNL of the corresponding row.
The capacitor C11 has one end connected to the power supply potential line VCCL and the other end connected to the drain of the TFT 12.

  Since organic EL elements often have rectifying properties, they are sometimes referred to as OLEDs (Organic Light Emitting Diodes). In FIG. 1 and others, diode symbols are used as light emitting elements. However, it does not necessarily require rectification.

In the pixel circuit 10 having such a configuration, a pixel to which luminance data is written is selected via a scanning line by a scan driver 3 (not shown), whereby the TFT 12 of the pixel circuit 10 is turned on.
At this time, the luminance data is supplied as a voltage from the data driver 2 through the signal line SGL, and is written into the capacitor C11 that holds the data voltage through the TFT 12.
The luminance data written in the capacitor C11 is held for one field period. The held data voltage is applied to the gate of the TFT 11.
Thereby, TFT11 drives the organic EL light emitting element 13 with an electric current according to holding | maintenance data. At this time, the gradation expression of the organic EL light emitting element 13 is performed by modulating the gate-source voltage Vdata (<0) of the TFT 11 held by the capacitor C11.

  In general, the luminance Loled of the organic EL element is proportional to the current Ioled flowing through the element. Therefore, the following equation (1) is established between the luminance Loled of the organic EL light emitting element 13 and the current Ioled.

(Equation 1)
Loled∝Ioled = k (Vdata−Vth) ² (1)

In Equation (1), k = 1/2 · μ · Cox · W / L. Here, μ is the carrier mobility of the TFT 11, Cox is the gate capacitance per unit area of the TFT 11, W is the gate width of the TFT 11, and L is the gate length of the TFT 11.
Therefore, it can be seen that the variation in mobility μ and threshold voltage Vth (<0) of the TFT 11 directly affects the luminance variation of the organic EL light emitting element 13.

  In this case, for example, even if the same potential Vdata is written to different pixels, the threshold voltage Vth of the TFT 11 varies from pixel to pixel. As a result, the current Ioled flowing through the light emitting element (OLED) 13 varies greatly from pixel to pixel and is completely different from the desired value. As a result, the display cannot be expected to have high image quality.

  A number of pixel circuits have been proposed in order to improve this problem. A typical example is shown in FIG. 2 (see, for example, Patent Document 3 or Patent Document 4).

The pixel circuit 20 in FIG. 2 includes a p-channel TFT 21, n-channel TFTs 22 to 24, capacitors C21 and C22, and an organic EL light emitting element 25 that is a light emitting element. In FIG. 3, SGL indicates a signal line, SCNL indicates a scanning line, AZL indicates an auto-zero line, and DRVL indicates a drive line.
The operation of the pixel circuit 20 will be described below with reference to the timing chart shown in FIG.

  As shown in FIGS. 3A and 3B, the drive line DRVL and the auto-zero line AZL are set to the high level, and the TFTs 22 and 23 are turned on. At this time, since the TFT 21 is connected to the light emitting element (OLED) 25 in a diode-connected state, a current flows through the TFT 21.

  Next, as shown in FIG. 3A, the drive line DRVL is set to low level, and the TFT 22 is turned off. At this time, as shown in FIG. 3C, the scanning line SCNL is at a high level and the TFT 24 is turned on, and the signal line SGL is supplied with the reference potential Vref as shown in FIG. 3D. Since the current flowing through the TFT 21 is cut off, the gate potential Vg of the TFT 21 rises as shown in FIG. 3E, but when the potential rises to VDD− | Vth |, the TFT 21 becomes non-conductive. Potential stabilizes. Hereinafter, this operation may be referred to as “auto-zero operation”.

  As shown in FIGS. 3B and 3D, the auto zero line AZL is set to the low level to turn off the TFT 23, and the potential of the signal line SGL is set to a potential lower than Vref by ΔVdata. This change in signal line potential lowers the gate potential of the TFT 21 by ΔVg through the capacitor C21, as shown in FIG.

  As shown in FIGS. 3A and 3C, when the TFT 24 is turned off by setting the scanning line SCNL to a low level and the TFT 22 is turned on by setting the drive line DRVL to a high level, the TFT 21 and the light emitting element (OLED) 25 are turned on. Current flows, and the light emitting element 25 starts to emit light.

  If the parasitic capacitance can be ignored, ΔVg and the gate potential Vg of the TFT 21 are as follows.

(Equation 2)
ΔVg = ΔVdata × C1 / (C1 + C2) (2)

(Equation 3)
Vg = V _CC − | Vth | −ΔVdata × C1 / (C1 + C2) (3)

  Here, C1 indicates the capacitance value of the capacitor C21, and C2 indicates the capacitance value of the capacitor C22.

  On the other hand, if the current flowing through the light emitting element (OLED) 25 during light emission is Ioled, the current value is controlled by the TFT 21 connected in series with the light emitting element 25. Assuming that the TFT 21 operates in the saturation region, the following relationship is obtained using the well-known MOS transistor equation and the above equation (3).

(Equation 4)
Ioled = μCoxW / L / 2 (V _CC −Vg− | Vth |) ²
= ΜCoxW / L / 2 (ΔVdata × C1 / (C1 + C2)) ²
... (4)

  Here, μ represents carrier mobility, Cox represents gate capacitance per unit area, W represents gate width, and L represents gate length.

According to the equation (4), Ioled is controlled by ΔVdata given from the outside regardless of the threshold value Vth of the TFT 21. In other words, by using the pixel circuit 20 of FIG. 2, it is possible to realize a display device that is relatively unaffected by the threshold value Vth that varies from pixel to pixel and that has relatively high current uniformity and consequently luminance uniformity.
USP 5,684,365 JP-A-8-234683 USP 6,229,506 Fig. 1 of JP-T-2002-514320. 3

  As described above, when the pixel circuit 10 as shown in FIG. 1 is used, the uniformity of luminance between pixels is impaired due to variations in the threshold voltage Vth of the transistor, and a high-quality display device can be configured. Have difficulty.

  On the other hand, if the pixel circuit of FIG. 2 is used, a display device with relatively high luminance uniformity can be realized, but this has the following problems.

  The first problem is that the gate amplitude ΔVg of the driving transistor decreases according to the equation (2) with respect to the data amplitude ΔVdata driven from the outside. Conversely, in order to obtain the same ΔVg, it is necessary to give a large ΔVdata, which is undesirable from the viewpoint of power consumption and noise.

The second problem is that the above description of the operation relating to the pixel circuit 20 of FIG. 3 is ideal, and in practice, the influence of variations in Vth of the TFT 21 that drives the light emitting element (OLED) 25 is not eliminated. .
This is because the auto zero line AZL and the gate node of the TFT 21 are coupled by the gate capacitance of the TFT 23, and the channel charge of the TFT 23 becomes the gate of the TFT 21 in the process in which the auto zero line AZL transitions to a high level and the TFT 23 becomes nonconductive. This is because it flows into the node. The reason for this will be described next.

That is, the gate potential of the TFT 21 should ideally be VCC− | Vth | after the completion of the auto zero operation, but actually becomes a slightly higher potential due to the inflow of the charge, and the inflow amount of the charge is It varies depending on the value of Vth. This is because the gate potential of the TFT 21 immediately before the end of the auto-zero operation is approximately VCC− | Vth |. Therefore, this potential is higher as | Vth | is smaller, for example.
On the other hand, when the auto zero operation ends, when the potential of the auto zero line AZL rises and the TFT 23 switches to non-conduction, the higher the source potential, that is, the gate potential of the TFT 21, the more delayed the timing at which the TFT 23 becomes non-conducting. Will flow into the gate of the TFT 21. As a result, the gate potential of the TFT 21 after completion of the auto-zero operation is affected by | Vth |, and thus the above-described equations (3) and (4) are not strictly established and are affected by Vth which varies from pixel to pixel. become.

  In addition, the variation in mobility due to the variation in crystal grain size of the laser anneal polysilicon during the production of the low-temperature polysilicon TFT cannot be removed. For this reason, in-plane luminance variation occurs. In particular, in-plane luminance variation occurs when the luminance is higher than when the luminance is low.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a pixel circuit that can prevent variations in luminance at high luminance and does not impair signal write response at low luminance, and a display device. Another object is to provide a method for driving a pixel circuit.

  A first aspect of the present invention is a pixel circuit that drives an electro-optical element whose luminance changes according to a flowing current, and includes a signal line to which a voltage signal corresponding to at least luminance information is supplied, and at least a first control line And the first reference potential and the second reference potential, the node, and the electro-optic element connected in series between the first reference potential and the second reference potential, and depending on the potential of the node The first switch that is turned on and off is connected between the signal line and the node, and is turned on and off by the first control line, and between the node and a predetermined potential. And a capacitor for holding a voltage signal input through the second switch, wherein one field is divided into N (where N is a positive integer) subfields and N different sections are set. , Each sub The second switch is controlled to be turned on and off for each field, and a voltage signal is input, and the first switch is turned on and off in accordance with the input signal to perform N-bit gradation display. .

  A display device according to a second aspect of the present invention includes a plurality of pixel circuits arranged in a matrix, and a signal that is wired for each column with respect to the matrix arrangement of the pixel circuits and to which a voltage signal corresponding to luminance information is supplied. A line, at least a first control line wired for each row with respect to the matrix arrangement of the pixel circuit, a first driver for propagating the desired voltage signal to the signal line, and the first control line A second driver for applying a signal for turning on and off the switch at a predetermined timing, and a first reference potential and a second reference potential. Is connected in series with the electro-optic element between the first reference potential and the second reference potential, and is turned on and off according to the potential of the node. Switch and above A second switch connected between the signal line and the node and turned on and off by the first control line, and a voltage signal connected between the node and the predetermined potential and inputted through the second switch. Each of the first and second drivers is divided into N (N is a positive integer) subfields, and N different divisions are set. For each field, the second switch of the pixel circuit is controlled to be turned on / off to input a voltage signal, and the first switch is turned on / off according to the input signal to perform N-bit gradation display. The first control line and the signal line are driven.

  Preferably, the second switch after the division in which the first horizontal scanning period of each subfield is equally divided into N and N divisions are set, and the address periods are set in different divisions for each subfield. The ON / OFF period is controlled to be 1 / N times or K / N times the length of one horizontal scanning period (where K is an integer of 2 or more) so that N-bit gradation display is performed.

  Preferably, the on / off timing of the second switch in the subfield in one horizontal scanning period is different in all the lines in the arrangement order of the subfields expressing the gradation of each pixel circuit, and When the timing chart is time on the horizontal axis and the line number on the vertical axis, the drive timing in which the subfields are arranged so that the on / off timing is the least sparse is taken.

  Preferably, a line memory for storing signal data for performing gradation display of the pixel circuit is provided.

  Preferably, in one field period, the line memory for storing signal data for performing gradation display of the pixel circuit and the display data are replaced in one field period for performing gradation display of the pixel circuit. Field memory.

  Preferably, the pixel circuit includes an erasing section that erases the potential of the node as a predetermined potential after inputting a voltage signal for each of the subfields.

  Preferably, a current supply circuit capable of supplying a constant current to the electro-optic element through the first switch is provided.

  Preferably, the current supply circuit can replicate a predetermined current value and supplies a replicated current.

  According to a third aspect of the present invention, there is provided an electro-optical element whose luminance is changed by a flowing current, a signal line to which a voltage signal corresponding to at least luminance information is supplied, at least a first control line, and a first reference potential. The first reference potential is connected in series with the electro-optic element between the second reference potential, the node, the first reference potential, and the second reference potential, and is turned on and off according to the potential of the node. And a second switch connected between the signal line and the node, and turned on and off by the first control line, and connected between the node and a predetermined potential. A driving method of a pixel circuit including a capacitor for holding a voltage signal input through a switch, wherein one field is divided into N (N is a positive integer) subfields and N different sections are set. And each sub On the second switch for each Rudo, enter the voltage signal off controls, on the first switch in response to an input signal, turns off, and drives to perform N-bit gradation display.

According to the present invention, in the pixel circuit for writing luminance data, the second switch of the pixel circuit is turned on for a predetermined period by being selected by the first control line.
At this time, a voltage signal indicating a high level or a low level is supplied via the signal line and is held in the capacitor through the second switch.
The data voltage held in the capacitor turns on or off the first switch through the node.
As a result, the electro-optic element is driven with current according to the retained data.
The first and second switches that are turned on and off when the electro-optic element is driven function as simple on / off switches.
In the gradation expression of the electro-optic element, for example, N subfield periods are provided in one field period to enable N-bit gradation display.
At this time, signals of N subfields are generated in a divided manner. When a pixel circuit is selected, a high-level or low-level signal is applied to the signal line, and the signal is taken into the pixel. It is done at the timing.

According to the present invention, there is no luminance variation at high luminance, and in particular, the image quality during white display is improved.
In addition, since an arbitrary luminance reference can be set, it can be set to eliminate a luminance variation deviation when a panel application, for example, the background corresponds to gray display.
Further, since voltage signal driving is possible, there is an advantage that the number of connection points to the signal line can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 4 is a diagram schematically showing the configuration of the active matrix organic EL display according to the first embodiment.
FIG. 5 is a circuit diagram showing a configuration example of the pixel circuit of the active matrix organic EL display according to the first embodiment.

The active matrix organic EL display 100 includes a pixel array unit 102 in which pixel circuits 101 are arranged in an m × n matrix, a data driver (DDRV) 103 as a first driver, and a scan as a second driver. A driver (SDRV) 104 is included.
Then, n columns of signal lines SGL101 to SGL10n that are selectively driven by the data driver (DDRV) 103 with respect to the matrix arrangement of the pixel circuit 101 are wired for each pixel column, and are selectively selected by the scan driver (SDRV) 104. Scan lines SCNL101 to SCNL10m as the first control lines for m rows driven in the same manner are wired for each pixel row.

Further, as shown in FIG. 5, the pixel circuit 101 includes p-channel TFTs 111 and 112, a capacitor C111, and a light emitting element 113 including an organic EL element (OLED).
The TFT 111 of each pixel circuit 101 has a source connected to the power supply potential line VCCL and a gate connected to the drain of the TFT 112. The organic EL light emitting device 113 has an anode connected to the drain of the TFT 111 and a cathode connected to a reference potential (for example, ground potential) GND.
The TFT 112 of each pixel circuit 101 is connected to the signal lines SGL101 to SGL10n in the columns corresponding to the sources, and to the scanning lines SCNL101 to SCNL10m in the rows corresponding to the gates.
The capacitor C111 has one end (first electrode) connected to the power supply potential line VCCL and the other end (second electrode) connected to the drain of the TFT 112.

The two TFTs 111 and 112 in the pixel circuit 101 of the present embodiment are made of low-temperature polysilicon TFTs, are operated not in the saturation region but in the linear region, and are driven so as to function as simple switches.
That is, the pixel circuit 101 is configured to include a selector switch circuit made of a low-pitched polysilicon TFT, thereby reducing the number of pins (PIN) of the source IC that generates the signal potential.

The pixel circuit 101 of this embodiment is driven and controlled by the data driver 103 and the scan driver 104 so as to display a plurality of times in one field period.
Further, as will be described in detail later, the data driver 103 includes a selector switch, and the selector switch is selected two or more times among the divided fields in the multiple-time display of the pixel circuit 101, and the signal driver 103 Signal writing is performed via the line SGL.

The scan driver 104 as a vertical scanning circuit employs a data latch type shift register system.
As shown in the timing chart of FIG. 6, the scan timing of the scan driver 104 is provided with, for example, eight sub-field (SF) periods in one field period (16.7 ms), 8-bit (256 gradations) display is enabled.
At this time, the scan driver 104 generates signals of eight sub fields (Sub Field) SF1 to SF8 (Field division selection), and the signal line when the scan driver (vertical scanning circuit) 104 performs the previous selection. A high-level (for example, 10 V) or low-level (0 V) signal is applied to the SGL from the data driver (selector) 103, and the signal is taken into the pixel at that timing.

  FIG. 7 is a diagram illustrating a configuration example of the display panel according to the first embodiment.

As shown in FIG. 7, a pixel array section 102, a data driver (DDRV) 103, and a scan driver (SDRV) 104 are formed on the display panel 200.
The data driver 103 is connected to a source IC 301 formed on the chip 300 via a data interface.
In the pixel array unit 102 in FIG. 7, the number of pixels of the panel is, for example, 960 (RGB) × 240 (line) in the vertical direction.

The data driver 103 includes a level shifter 1031 and a 2-selector switch unit 1032.
In the present embodiment, the generated signal of 0 / 5V amplitude from the source IC 301 is level-shifted to a signal of 0 / 10V amplitude by the level shifter 1031 of the data driver 130 existing in the vicinity of the panel input unit, and the selector switch unit 1032 is further switched. By selecting through the sub-fields, time-division distribution is performed on the eight subfields SF.

FIG. 8 is a diagram illustrating a timing example of the switching signals S1 and S2 for switching a plurality of selector switches of the selector switch unit 103.
The selector switch unit 1031 shown in FIG. 7 shows only three selector switches SW1, SW2, and SW3.

When the switch SW1 in FIG. 7 receives the switching signal S1, the switch SW1 propagates the level-shifted signal of 10V or 0V to the signal line SGL101-B corresponding to the B signal, and corresponds to the R signal when receiving the switching signal S2. A 10V signal or a 0V signal level-shifted is propagated to the signal line SGL102-R.
When the switch SW2 receives the switching signal S1, the switch SW2 propagates the level-shifted 10V signal or 0V signal to the signal line SGL103-G corresponding to the G signal, and when receiving the switching signal S2, the signal line SGL104 corresponding to the B signal. A 10V signal or a 0V signal level-shifted to -B is propagated.
When the switch SW3 receives the switching signal S1, the switch SW3 propagates the level-shifted 10V signal or 0V signal to the signal line SGL105-R corresponding to the R signal, and when receiving the switching signal S2, the signal line SGL106 corresponding to the G signal. A 10V signal or a 0V signal level-shifted to -G is propagated.

  By performing such time-division gradation display, the number of signal lines from the source IC 301 can be handled by the number divided (divided) by the divided number for a normal organic EL display. The number of pins can be reduced.

As described above, in the present embodiment, when driving and displaying the optical element 113 of the pixel circuit 101, one field is divided into a plurality of subfields SF, and subfields having different light emission periods (different lengths) are used. Time-division gradation display is employed in which gradation display is performed by selecting (ON, OFF) SF to emit light.
In the present embodiment, when this time-division gradation display is performed, data output is performed according to an address display simultaneous driving method (AWD) instead of a line sequential writing method.

The reason why the AWD method is adopted instead of the line sequential writing method will be described below.
First, the line sequential writing method will be described with reference to FIGS.

  FIG. 9 is a diagram showing scan line drive timing in the case of eight lines of the line sequential writing method. FIG. 10 is a diagram illustrating an output form of data in the line sequential writing method. FIG. 11 is a diagram illustrating a scanning state when the line sequential writing method is employed.

Here, the case of 8-gray display in which one field is divided into three subfields SF1, SF2, and SF3 each having a different period, and the case of 8-line driving is taken as an example.
In the case of line sequential, as shown in FIG. 9 and FIG. 10, data is sequentially output from the LSB to the MSB, and the order of writing is line sequential, that is, the subfield SF1 of line L1 to line L8 is written. Write subfield SF2 of line L8 and write subfield SF3 of line L1 to line L8.
However, in this case, as shown in FIG. 9, there is a period during which writing cannot be performed.
In order to suppress deterioration of the light emitting element 113 made of an organic EL element, it is necessary to suppress the amount of current flowing at a time. In order to suppress the amount of current, the light emission period may be made long. However, if all the periods other than the write time are set to the light emission period, the write time becomes insufficient.
For example, in the case of 240 lines and 8SF (256 gradations), the writing time is 0.27 μs.
When the writing time is prioritized, the display period decreases. For example, in the case of 240 lines and 8SF (256 gradations) and a writing time of 6 μs, the ratio of the display period is about 64%, and the current flowing at a time increases.

  Therefore, in the present embodiment, as shown in FIGS. 12 and 13, data is output using the AWD method.

  FIG. 12 is a diagram showing scan line drive timing in the case of 8 lines of the AWD system. FIG. 13 is a diagram illustrating an output form of AWD data.

In this case as well, in the case of 8-gradation display in which one field is divided into three subfields SF1, SF2, and SF3 each having a different period, the case of 8-line driving is taken as an example.
In the AWD system, writing is not line sequential, and data is also performed in a random order, for example, subfield SF1 of line L1, then subfield SF2 of line L8, and then subfield SF3 of line L6.

As described above, in the organic EL display 100 of the present embodiment, sub-field gradation expression is performed.
Specifically, for each line, each field is divided into N (where N is a positive integer) subfield SF, and the first 1H period (where H is a horizontal scanning period) of each subfield is N. The period of the sustain pulse WS by the scan driver 104 in the discharge sustaining period of the capacitor C111 after the division in which the N divisions are equally divided and the address period is set in a different division for each subfield is set to 1H period. N-bit gradation display is performed with 1 / N times the length or K / N times (where K is an integer greater than or equal to 2).
In addition, regarding the arrangement order of the subfields expressing the gradation of each pixel, the discharge start timing of the subfield SF in the 1H period is different for all lines, and the so-called timing chart is time on the horizontal axis and the line on the vertical axis. In the case of the number (see FIGS. 12 and 13), the drive timing in which the subfields are arranged so that the discharge start timing of the capacitor C111 is sparse is taken.

By adopting the drive timing according to the above AWD method, the writing period can be arranged without wasting the whole period.
For example, in the case of 240 lines and 8SF (256 gradations), the writing time is 8.7 μs (= 16.7 ms / 8SF / 240 lines).

Such drive timing corresponding to the AWD system is held in a table (not shown) in advance as an AWD time sequence, for example.
Hereinafter, an example of a method for creating an ADW time sequence will be described. Here, a case where one field is divided into 10 subfields including γ correction for 2 bits will be described.

1) A 1H period is determined by dividing (dividing) one field (16.7 ms) by the number of scan lines (in this example, 240 lines). That is, 16.7 ms / 240 = 69.5 μs is set as the 1H period.

2) Divide (divide) 1H (69.5 μs) by the number of subfields (10SF in this example) to determine the writing time. That is, 69.5 μs / 10 = 6.95 μs is set as the writing time.

3) As shown in FIG. 14, 1H period is allocated in the writing period of each subfield.

4) The write timing of each subfield SF is set so as not to violate the write period of the allocated subfield SF.

5) The creation of the AWD time sequence table is completed by shifting the writing sequence of each line by 1H.

  Next, the operation according to the above configuration will be described.

In the organic EL display having the above-described configuration, in the pixel circuit 101 that writes luminance data, a pixel row including this pixel is selected by the scan driver 104 via the scanning line SCNL. TFT 112 is turned on.
At this time, a voltage indicating a high level (10 V) or a low level (0 V) is supplied from the data driver 103 via the signal line SGL and is held in the capacitor C111 through the TFT 112.
The data voltage held in the capacitor C111 is applied to the gate of the TFT 111.
Thereby, the TFT 111 is turned on or off according to the retained data, and the organic EL light emitting element 13 is driven by current.
The TFTs 111 and 112 that are turned on and off when the organic EL light emitting element 113 is driven function as a simple on / off switch.
That is, in the present embodiment, the gradation expression of the organic EL light emitting element 113 is not performed by modulating the gate-source voltage of the TFT 111 held by the capacitor C111, but is performed as follows.

In the present embodiment, the scan timing of the scan driver 104 is, for example, by providing eight subfield SF periods in one field period (16.7 ms), and displaying 8-bit (256 gradations). It is possible.
At this time, signals of eight subfields SF1 to SF8 (Field division selection) are generated in the scan driver 104, and when the scan driver 104 performs the previous selection, the signal line SGL is set to the high level from the data driver 103. A signal of (for example, 10V) or low level (0V) is applied, and the signal is taken into the pixel at that timing.

  As described above, in the first embodiment, the gradation expression of the organic EL light emitting element 113 is time-division gradation display, and data output is performed according to the AWD method instead of the line sequential writing method, and each pixel circuit is displayed. 101, since the TFT 111 disposed in the current supply path to the organic EL light emitting element 113 functions only as an on / off switch, the mobility 111 of the TFT 111 that affects the luminance variation of the organic EL light emitting element 113, Regardless of variations in the threshold value Vth, it is possible to drive the organic EL light emitting element 113 stably while suppressing the occurrence of luminance unevenness.

  As described above, according to the first embodiment, the pixel circuit 101 includes the TFT 111 and the organic EL light emitting device 113 arranged in series between the power supply potential line VCCL and the reference potential (for example, the ground potential GND). , The TFT 112 connected between the signal line SGL and the gate of the TFT 111, and the capacitor C111 connected between the gate of the TFT 111 and the power supply potential line VCCL. The scan timing of the scan driver 104 is, for example, one field N (for example, 8 or 10) subfield SF periods are provided in the period (16.7 ms) to enable N-bit (256 gradations in the case of 8 bits) display, and the scan driver 104 has, for example, N sub-fields. Generate signals of fields SF1 to SFN, and scan driver 104 selects the previous When performing, a high level (for example, 10V) or low level (0V) signal is applied to the signal line SGL from the data driver 103, and the signal is taken into the pixel at that timing, so that the following effects are obtained. be able to.

In each pixel circuit 101, the TFT 111 arranged in the current supply path to the organic EL light emitting element 113 can function only as an on / off switch. As a result, the luminance variation of the organic EL light emitting element 113 is affected. Regardless of variations in the mobility μ and the threshold value Vth of the TFT 111 that gives the luminance, it is possible to drive the organic EL element 113 stably while suppressing the occurrence of uneven brightness. Therefore, luminance variations at high luminance can be prevented without impairing signal write response at low luminance. As a result, a high-quality image can be displayed.
Further, the configuration of the pixel circuit can be made very simple without providing a TFT for threshold correction or the like. As a result, the number of control lines such as scan lines can be kept to a minimum, the load on the control system can be reduced, and the display panel can be narrowed.

In other words, according to the first embodiment, there is no luminance variation at high luminance, and the image quality of the organic EL light emitting element (OLED) during white display is improved.
In addition, since any luminance reference can be set, it can be set to eliminate the luminance variation deviation in the panel application (for example, the background corresponds to gray display).
Further, since voltage signal driving is used, the number of connection points to the signal line can be reduced. In the current driving circuit, it is necessary to pass a current during the horizontal selection period, so that the signal line changeover switch cannot be used. In order to reduce the number of connection terminals, it is desirable to store electric charge in the capacitance of the signal line.

  Note that the pixel circuit 101 in FIG. 5 is an example, and the present invention is not limited to this. For example, as described above, since the TFTs 111 and 112 are merely switches, it is obvious that all or a part of them can be constituted by n-channel TFTs or other switching elements.

Second Embodiment
FIG. 15 is a diagram schematically illustrating the configuration of an active matrix organic EL display (display device) according to the second embodiment of the present invention.
FIG. 16 is a circuit diagram showing a pixel circuit of an active matrix organic EL display according to the second embodiment.
FIG. 17 is a diagram including a display panel configuration example of an active matrix organic EL display (display device) according to the second embodiment of the present invention.

The organic EL display 100A of the second embodiment is different from the organic EL display 100 of the first embodiment described above in that a voltage signal (10V or 0V) is applied to one subfield SF in the pixel circuit 101A of each line. Is captured through the TFT 112 and held in the capacitor C111, and then the potential of the node ND111 connected to the gate of the TFT 111 and the capacitor C111 is erased (erase) each time, thereby realizing stable gradation display. .
Specifically, in the organic EL display 100A, erase (erase) lines ESL101 to ESL10m are wired for each pixel row, and an erase driver (EDRV) that selectively applies an erase signal ES to each of the erase lines ESL101 to ESL10m. ) 105 is provided.
In each pixel circuit 101A, an erasing p-channel TFT 114 is provided, the source of the TFT 114 is connected to the power supply potential VCCL, and the drain is connected to the node ND111 to which the gate of the TFT 111 and the second electrode of the capacitor C111 are connected. The gate is connected to the erase line ESL wired in the corresponding row.

FIG. 18 is a diagram showing the timing of the erase signal ES.
The example of FIG. 18 is an example when one field is divided into 10 subfields SF.
In this embodiment, the voltage signal (10 V or 0 V) is taken into one subfield SF through the TFT 112 and held in the capacitor C111 regardless of the number of divisions in one field, and then the gate of the TFT 111 and the capacitor C111 are connected each time. The stable gradation display is realized by erasing the potential of the node ND111.

In the second embodiment, R, G, and B independent line memories for storing signal data for performing gradation display of an arbitrary single pixel a plurality of times in one field period, and the plurality of times An IC chip 300A including a field memory for exchanging display data within one field period for performing gradation display of an arbitrary unit pixel is disposed outside the panel.
Here, the line memory outputs the signal data by controlling the source IC with the data rearranged according to the AWD method in the field memory. At this time, since RGB can be output independently, the number of connected PINs and the number of wirings are drastically reduced.
That is, the number of pins of the source IC 300A that generates a data signal by time division can be reduced by providing a memory for each signal line, for example, an 8-bit data signal formed by a TFT. This 8-bit data consists of RGB independent serial data from the field memory. As a result, as for the number of signal lines from the source IC 300A, the number of GB corresponding to the bit can be achieved with respect to a normal organic EL display, and the minimum number of input / output pins is sufficient.

  The other configuration is the same as that of the first embodiment. According to the second embodiment, the number of TFTs 114 is increased by one in each pixel circuit, and the number of erase lines ESL as control lines is increased. The effect similar to that of the first embodiment described above can be obtained without significantly affecting the narrowing of the frame, and more stable gradation display can be realized.

  Note that the pixel circuit 101A in FIG. 16 is an example, and the present invention is not limited to this. For example, as described above, since the TFT 111, TFT 112, and TFT 114 are merely switches, it is obvious that all or a part of them can be constituted by n-channel TFTs or other switching elements.

<Third Embodiment>
FIG. 19 is a diagram showing an outline of a configuration of an active matrix organic EL display (display device) according to the third embodiment of the present invention.
FIG. 20 is a circuit diagram showing a pixel circuit of an active matrix organic EL display according to the third embodiment.
FIG. 21 is a diagram including a display panel configuration example of an active matrix type organic EL display (display device) according to the third embodiment of the present invention.

The organic EL display 100B according to the third embodiment is different from the organic EL display 100A according to the second embodiment described above in that the constant current is replicated in the pixel circuit 101B of each line, and the replicated current is driven. The organic EL light-emitting element 113 is configured to be supplied to the organic EL light-emitting element 113 through the TFT 111, the characteristic deterioration of the organic EL light-emitting element 113 occurs, and the decrease in luminance is suppressed.
Specifically, in the organic EL display 100B, reference current supply lines IRFL101 to IRFL10n are wired for each pixel column, and a current driver that selectively applies a reference current Iref to each reference current supply line IRFL101 to IRFL10n ( IDRV) 106 is provided.
Further, a copy driver (CDRV) 107 is provided for wiring current replication lines (cure copy lines) CCL101 to CCL10m for each pixel row and selectively applying a current copy signal CS to each of the current replication lines CCL101 to CCL10m. Yes.
In each pixel circuit 101B, as shown in FIG. 20, a current copy circuit 120 is provided between the source of the TFT 111 as a drive switch and the power supply potential ship VCCL.

  As shown in FIG. 20, the current copy circuit 120 includes a p-channel TFT 121, n-channel TFTs 122 and 123, a capacitor C121, and nodes ND121 and ND122.

The source of the TFT 121 is connected to the power supply potential line VCCL, the drain is connected to the node ND121, and the gate is connected to the node ND122.
One end (first electrode) of the capacitor C121 is connected to the power supply potential line VCCL, and the other end (second electrode) is connected to the node ND122.
The source of the TFT 122 is connected to the reference current supply line IRFL, and the drain is connected to the node ND121. The source of the TFT 123 is connected to the node ND121, and the drain is connected to the node ND122. The gates of the TFTs 122 and 123 are commonly connected to the current copy line CCL.
The output node ND121 of the current copy circuit 120 is connected to the source of the TFT 111 that forms the drive switch of the pixel circuit 101B.

In the pixel circuit 101B having such a configuration, first, the copy driver 107 applies a high-level current copy signal CS to the current copy line CCL for a predetermined period. As a result, the TFTs 122 and 123 of the current copy circuit 120 are turned on.
At this time, the reference current Iref is supplied to the corresponding reference current supply line IRFL, and this reference current Iref is copied to the capacitor C121 through the TFTs 122 and 123 of the current copy circuit 120 (retained and copied as charges). ).
When the predetermined period elapses, the copy copy signal CS is switched to a low level by the copy driver 107. As a result, the TFTs 122 and 123 of the current copy circuit 120 are turned off, and the reference current Iref is held in the capacitor C121 to be copied.
Accordingly, the node ND122 is held at a predetermined potential, applied to the gate of the TFT 121, and a constant current is supplied to the source side of the TFT 111 through the node ND121.
After that, by the same driving as in the first and second embodiments, for example, signals of eight subfields SF1 to SF8 (Field division selection) are generated in the scan driver 104, and the scan driver 104 performs the previous selection. Sometimes, a high level (for example, 10 V) or low level (0 V) signal is applied from the data driver 103 to the signal line SGL, and the signal is taken into the pixel at that timing.
Note that a voltage signal (10 V or 0 V) is taken into one subfield SF through the TFT 112 and held in the capacitor C111, and then the potential of the node ND111 connected to the gate of the TFT 111 and the capacitor C111 is erased each time.

In the third embodiment, R, G, and B independent line memories for storing signal data for performing gradation display of an arbitrary single pixel a plurality of times in one field period, and the plurality of times An IC chip 300B including a field memory for switching display data within one field period for performing gradation display of an arbitrary unit pixel is disposed outside the panel.
Here, the line memory outputs the signal data by controlling the source IC with the data rearranged according to the AWD method in the field memory. At this time, since RGB can be output independently, the number of connected PINs and the number of wirings are drastically reduced.

  According to the third embodiment, not only the same effects as those of the first and second embodiments described above can be obtained, but also the characteristics of the organic EL light emitting device 113 are deteriorated and the luminance is lowered. Can be suppressed, and a higher quality image can be obtained.

<Fourth embodiment>
FIG. 22 is a diagram including a display panel configuration example of an active matrix organic EL display (display device) according to the fourth embodiment of the present invention.

  The difference between the organic EL display 100C of the fourth embodiment and the organic EL display 100A of the second embodiment is that signal data for gradation display of an arbitrary single pixel is accumulated a plurality of times in one field period. R, G, and B independent line memories are arranged not on the external IC chip but on the input side of the data driver 104 of the panel 200C, and the gradation display of arbitrary unit pixels is performed multiple times on the IC chip 300C. In other words, a field memory for replacing display data within one field period is included.

  In the fourth embodiment, in order to reduce the operating frequency of the horizontal scanning drive circuit in the data driver using TFT (thin film transistor), the operating frequency is originally set to two data drivers 103-1 and 103-2. A configuration with half the frequency is adopted. Therefore, two line memories 108-1 and 108-2 are arranged in the panel 200C.

As an example, FIG. 23 shows the arrangement of signal data lines and line memories according to the present embodiment, and FIG. 24 shows a timing chart for reading signal data according to the present embodiment.
However, in FIG. 23, only R data is shown for simplification of the drawing, but actually B data and G data are similarly arranged and arranged.

  Other configurations are the same as those of the second embodiment, and according to the fourth embodiment, the same effects as those of the second embodiment described above can be obtained.

<Fifth Embodiment>
FIG. 25 is a diagram including a display panel configuration example of an active matrix organic EL display (display device) according to the fifth embodiment of the present invention.

  The organic EL display 100D of the fifth embodiment is different from the organic EL display 100B of the third embodiment in that signal data for performing gradation display of an arbitrary single pixel is accumulated a plurality of times in one field period. R, G, and B independent line memories are arranged not on the external IC chip but on the input side of the data driver 104 of the panel 200D, and the gradation display of arbitrary unit pixels is performed multiple times on the IC chip 300C. In other words, a field memory for replacing display data within one field period is included.

  In the fifth embodiment, in order to reduce the operating frequency of the horizontal scanning drive circuit in the data driver using TFT (Thin Film Transistor), the operating frequency is originally set to two data drivers 103-1 and 103-2. A configuration with half the frequency is adopted. Therefore, two line memories 108-1 and 108-2 are arranged in the panel 200D.

  Other configurations are the same as those of the third embodiment, and according to the fifth embodiment, the same effects as those of the fifth embodiment described above can be obtained.

<Sixth Embodiment>
FIG. 26 is a diagram including a display panel configuration example of an active matrix type organic EL display (display device) according to the sixth embodiment of the present invention.

  The organic EL display 100E of the sixth embodiment shows a more specific configuration of the data drivers 103-1 and 103-2 of the organic EL display 100D of the fifth embodiment.

  The data driver 103 (-1, -2) of the sixth embodiment includes a level shifter 1031E, a 2-selector switch unit 1032E, and a horizontal scanning drive circuit (SR) 1033E.

  In this case, the level shifter 1031E is arranged at a position as shown in FIG. 27 or 28, for example.

In the case of the example of FIG. 27, a 5V system signal with 0 / 5V amplitude from the IC chip 300E is input to the line memory 108, and a predetermined process is performed by the horizontal scanning drive circuit 1031. Then, a 10V system with 0 / 10V amplitude is output by the level shifter 1031E. The signal is level-shifted (5V is increased to 10V) and input to the selector switch unit 1032E.
In the selector switch unit 1032E, the 10V signal is appropriately switched according to the switching signal, and the data in accordance with the AWD method is propagated to a predetermined signal line.

In the case of the example of FIG. 28, the level shifter 1031E first level-shifts the 5V system signal of 0 / 5V amplitude of the IC chip 300E into a 10V system signal of 0 / 10V amplitude (boosts 5V to 10V), and 10V system The signal is input to the line memory 108, subjected to predetermined processing by the horizontal scanning drive circuit 1031, and then input to the selector switch unit 1032E.
In the selector switch unit 1032E, the 10V signal is appropriately switched according to the switching signal, and the data in accordance with the AWD method is propagated to a predetermined signal line.

  According to the sixth embodiment, the same effects as those of the third and fifth embodiments described above can be obtained.

It is a circuit diagram which shows the 1st structural example of a general pixel circuit. It is a circuit diagram which shows the 2nd structural example of a general pixel circuit. 3 is a timing chart for explaining a method of driving the circuit of FIG. 2. 1 is a diagram illustrating an outline of a configuration of an active matrix organic EL display according to a first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a configuration example of a pixel circuit of the active matrix organic EL display according to the first embodiment. It is a figure for demonstrating the time division gradation display of this embodiment. It is a figure which shows the specific structural example of the data driver which concerns on this embodiment. It is a figure which shows the switching timing of the selector switch part of FIG. It is a figure which shows the drive timing of the scan line in the case of 8 lines of a line sequential writing system. It is a figure which shows the output form of the data of a line sequential writing system. It is a figure which shows the mode of a scan at the time of employ | adopting a line sequential writing system. It is a figure which shows the drive timing of the scan line in the case of 8 lines of an AWD system. It is a figure which shows the output form of the data of an AWD system. It is a figure for demonstrating the creation example of an AWD time sequence table | surface. It is a figure which shows the outline of a structure of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 2nd Embodiment of this invention. It is a circuit diagram showing a pixel circuit of an active matrix type organic EL display concerning a 2nd embodiment. It is a figure shown including the display panel structural example of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 2nd Embodiment of this invention. It is a figure which shows the timing of the erase signal ES. It is a figure which shows the outline of a structure of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the pixel circuit of the active matrix type organic EL display which concerns on 3rd Embodiment. It is a figure including the display panel structural example of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 3rd Embodiment of this invention. It is a figure including the display panel structural example of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 4th Embodiment of this invention. It is a figure which shows an example of arrangement | positioning of the signal data wiring and line memory by this embodiment. It is a figure which shows the reading timing chart of the signal data by this embodiment. It is a figure including the example of a display panel structure of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 5th Embodiment of this invention. It is a figure including the example of a display panel structure of the active matrix type organic electroluminescent display (display apparatus) which concerns on the 6th Embodiment of this invention. FIG. 27 is a diagram illustrating a first configuration example of a data driver portion of FIG. 26. FIG. 27 is a diagram illustrating a second configuration example of the data driver portion in FIG. 26.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,100A-100E ... Active matrix type organic EL display (display device), 101, 101A, 101B ... Pixel circuit, 102, 102A, 102B ... Pixel array unit, 103, 103-1, 103-2 ... Data driver (DDRV) ), 104, 104-1, 104-2 ... scan driver (SDRV), 105 ... erase driver (EDRV), 106 ... current driver, 107 ... copy driver, 108-1, 108-2 ... line memory, 200, 200A ˜200E, display panel, 111, 112, 114, TFT, 120, current copy circuit, 121-123, TFT, C121, capacitor, ND111, ND121, ND122, node, VCCL, power supply potential line.

Claims (18)

A pixel circuit that drives an electro-optic element whose luminance changes according to a flowing current,
A signal line to which a voltage signal corresponding to at least luminance information is supplied;
At least a first control line;
A first reference potential and a second reference potential;
Nodes,
A first switch connected in series with the electro-optic element between the first reference potential and the second reference potential and turned on and off according to the potential of the node;
A second switch connected between the signal line and the node and turned on and off by the first control line;
A capacitor connected between the node and a predetermined potential and holding a voltage signal input through the second switch,
One field is divided into N (where N is a positive integer) subfields and N different sections are set, and the second switch is turned on and off for each subfield to input a voltage signal. And a pixel circuit controlled to perform N-bit gradation display by turning on and off the first switch in accordance with an input signal. 2. The pixel circuit according to claim 1, further comprising an erase unit that erases the potential of the node as a predetermined potential after inputting a voltage signal for each of the subfields. The pixel circuit according to claim 1, further comprising a current supply circuit capable of supplying a constant current to the electro-optic element through the first switch. The pixel circuit according to claim 2, further comprising a current supply circuit capable of supplying a constant current to the electro-optic element through the first switch. The pixel circuit according to claim 3, wherein the current supply circuit is capable of replicating a predetermined current value and supplies the replicated current. The pixel circuit according to claim 4, wherein the current supply circuit is capable of replicating a predetermined current value and supplies the replicated current. The first horizontal scanning period of each subfield is divided equally into N to set N sections, and the second switch is turned on / off after the section in which the address period is set to a different section for each subfield. 2. The pixel according to claim 1, wherein the period is controlled to perform N-bit gradation display by setting the period to 1 / N times or K / N times the length of one horizontal scanning period (where K is an integer of 2 or more). circuit A plurality of pixel circuits arranged in a matrix;
A signal line wired for each column with respect to the matrix arrangement of the pixel circuit and supplied with a voltage signal according to luminance information;
At least a first control line wired for each row to the matrix arrangement of the pixel circuit;
A first driver for propagating the desired voltage signal to the signal line;
A second driver for applying a signal for turning on and off the switch at a predetermined timing to the first control line;
A first reference potential and a second reference potential;
Each pixel circuit is
An electro-optic element whose luminance varies depending on the flowing current;
Nodes,
A first switch connected in series with the electro-optic element between the first reference potential and the second reference potential and turned on and off according to the potential of the node;
A second switch connected between the signal line and the node and turned on and off by the first control line;
A capacitor connected between the node and a predetermined potential and holding a voltage signal input through the second switch,
The first and second drivers are
Each field is divided into N (where N is a positive integer) subfields and N different sections are set, and the second switch of the pixel circuit is turned on and off for each subfield. A display device that inputs a voltage signal, turns on and off the first switch in accordance with the input signal, and drives the first control line and the signal line to perform N-bit gradation display. The first horizontal scanning period of each subfield is divided equally into N to set N sections, and the second switch is turned on / off after the section in which the address period is set to a different section for each subfield. 9. The display according to claim 8, wherein the cycle is controlled to perform N-bit gradation display by setting the period to 1 / N times or K / N times the length of one horizontal scanning period (where K is an integer of 2 or more). apparatus. Regarding the arrangement order of the subfields expressing the gradation of each pixel circuit, the on / off timing of the second switch in the subfield in one horizontal scanning period is different in all lines, and the timing chart is The display device according to claim 9, wherein when the axis is time and the vertical axis is a line number, the drive timing in which the subfields are arranged so that the on / off timing is the least sparse. The display device according to claim 8, further comprising a line memory for storing signal data for performing gradation display of the pixel circuit. A line memory for storing signal data for performing gradation display of the pixel circuit in one field period;
The display device according to claim 8, further comprising: a field memory that replaces display data within one field period for performing gradation display of the pixel circuit. The display device according to claim 8, wherein the pixel circuit includes an erasing unit that erases the potential of the node as a predetermined potential after inputting a voltage signal for each of the subfields. The display device according to claim 8, further comprising a current supply circuit capable of supplying a constant current to the electro-optic element through the first switch. The display device according to claim 13, further comprising a current supply circuit capable of supplying a constant current to the electro-optic element through the first switch. The display device according to claim 14, wherein the current supply circuit is capable of replicating a predetermined current value and supplying the replicated current. The display device according to claim 15, wherein the current supply circuit is capable of replicating a predetermined current value and supplies the replicated current. An electro-optic element whose luminance varies depending on the flowing current;
A signal line to which a voltage signal corresponding to at least luminance information is supplied;
At least a first control line;
A first reference potential and a second reference potential;
Nodes,
A first switch connected in series with the electro-optic element between the first reference potential and the second reference potential and turned on and off according to the potential of the node;
A second switch connected between the signal line and the node and turned on and off by the first control line;
A capacitor circuit connected between the node and a predetermined potential and holding a voltage signal input through the second switch,
One field is divided into N (where N is a positive integer) sub-fields and N different sections are set, and the second switch is turned on / off for each sub-field to input a voltage signal A driving method of a pixel circuit, wherein the first switch is turned on / off in accordance with an input signal and is driven to perform N-bit gradation display.

Images