JP4662012B2 - Display and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display (hereinafter also referred to as a driving device of a light emitting display panel or simply a driving device ) in which a light emitting element constituting a pixel is actively driven by, for example, a TFT (Thin Film Transistor), and in particular, a lighting period of the light emitting element . The present invention relates to a display capable of realizing multi-gradation expression by digitally controlling and effectively correcting in-plane variation and γ correction in a data line direction, and a driving method thereof .
[0002]
[Prior art]
The development of a display using a display panel configured by arranging light emitting elements in a matrix is being widely promoted. As a light-emitting element used in such a display panel, for example, an organic EL (electroluminescence) element using an organic material for a light-emitting layer has attracted attention, and has already been put into practical use in some products. This is also due to the fact that the use of an organic compound that can be expected to have good light-emitting characteristics for the light-emitting layer of the EL element has led to an increase in efficiency and longevity that can withstand practical use.
[0003]
As a display panel using such an organic EL element, a passive matrix type display panel in which EL elements are simply arranged in a matrix form, and an active matrix type in which active elements such as TFTs are added to each of the EL elements arranged in a matrix form. A display panel has been proposed. The latter active matrix display panel can realize lower power consumption and has less crosstalk between pixels than the former passive matrix display panel. Suitable for high-definition displays that make up
[0004]
By the way, as one of the gradation expressions when the active matrix display panel is driven to illuminate, for example, an effective lighting period corresponding to one frame is divided into a plurality of equally spaced subframes, and light is emitted in units of the subframes. There has been proposed digital time gradation control in which the element is controlled to be lit. As described above, the gradation control for controlling the lighting of the light emitting element in units of subframes is called a so-called unweighted subframe method, and the relationship between the gradation and the light emission luminance is controlled to be almost linear (γ = 1). . However, it is said that the ideal gradation and luminance characteristics are based on a γ correction curve of γ (visual sensitivity) = 1.8 to 2.2.
[0005]
Thus, for example, in the case where gradation control based on a γ correction curve of about γ = 2.0 is to be realized, the luminance difference between gradations on the high gradation side is relatively large, whereas the low gradation side The difference in brightness between gradations is extremely small. Therefore, in order to precisely control the luminance difference according to the luminance difference between gradations on the low gradation side, high resolution is required, and as a result, the clock signal that controls the entire driving circuit is accelerated. Need arises. When the clock signal is increased in this way to increase the operation speed of the circuit, there is a problem that the power consumption of the entire circuit increases.
[0006]
Therefore, as described above, as a means for executing gradation control without increasing the clock signal speed, gradation control using analog gradation control in addition to the digital time gradation control described above is the following patent. It is disclosed in Document 1.
[0007]
[Patent Document 1]
JP 2000-56727 A (paragraphs 0023 to 0033, FIGS. 5 to 7)
[0008]
[Problems to be solved by the invention]
By the way, according to the gradation control method disclosed in Patent Document 1, in addition to digital time gradation control, the light emission luminance of the element is controlled by changing the power supply voltage for driving the light emitting element in an analog manner. Like to do. According to this, although it is not necessary to speed up the clock signal to a certain extent as described above, as shown in FIG. 5 in the Patent Document 1, the power line and each panel signal line (data line) It is necessary to insert a DAC (Digital to Analog Converter) in each of the gaps, and it is inevitable that the cost will increase.
[0009]
The present invention has been made paying attention to the above-described problems, and realizes multi-gradation expression by digitally controlling the lighting period of the light emitting element, and at the same time the data line direction without increasing the clock signal speed. It is an object of the present invention to provide a driving device and a driving method for a light emitting display panel that can realize in-plane variation and γ correction at low cost.
[0010]
[Means for Solving the Problems]
The display according to the present invention, which has been made to solve the above-described problems, includes a light emitting element controlled to emit light through a lighting driving transistor and data for controlling a gate potential of the lighting driving transistor. Each pixel including at least a writing transistor and a charge holding capacitor that holds the gate potential controlled by the data writing transistor is arranged at an intersection of a plurality of data lines and a plurality of scanning lines. A gray-scale display that realizes gray scale control by dividing a unit frame period of a video signal into a plurality of equally spaced sub-frame periods and controlling lighting of the light-emitting elements for each sub-frame period. and control means, if the luminance generated in the set γ correction and data line direction for each scanning line Based on the correction data for realizing the correction per has a feature in that the and a level shift means for level shifting the corresponding potential to the write data supplied to said data write transistor via each data line.
[0011]
A display driving method according to the present invention, which has been made to solve the above-described problems, includes: a light emitting element whose emission is controlled through a lighting driving transistor; and a gate of the lighting driving transistor. Each pixel including at least a data writing transistor for controlling a potential and a charge holding capacitor for holding the gate potential controlled by the data writing transistor is arranged at an intersection position of a plurality of data lines and a plurality of scanning lines. A display driving method configured to be arranged in each of the above, wherein a unit frame period of a video signal is divided into a plurality of equally spaced subframe periods, and lighting control of the light emitting element is performed for each subframe period. and executes the gradation control, the set for each scanning line γ correction and data lines Based on the correction data for realizing the correction of luminance unevenness occurring countercurrent, characterized in that shifting the level of the potential of the write data supplied to the data write transistor via said each data line.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS A light emitting display panel driving apparatus according to the present invention will be described below based on the embodiments shown in the drawings. FIG. 1 shows the form of one pixel constituting an active matrix light-emitting display panel that is lit and driven by a driving apparatus according to the present invention. That is, the form of the pixel denoted by reference numeral 1 shows the most basic pixel configuration in the case where an organic EL element called a conductance control system composed of two TFTs is used as a light emitting element.
[0013]
In FIG. 1, the control TFT, that is, the gate of the data write transistor Tr <b> 1 is connected to a scanning line (hereinafter also referred to as a scanning line) 2, and its source is connected to a data line (hereinafter also referred to as a data line) 3. Has been. The drain of the writing transistor Tr1 is connected to the lighting driving TFT, that is, the gate of the driving transistor Tr2, and to one terminal of the charge holding capacitor C1.
[0014]
The source of the driving transistor Tr2 is connected to the other terminal of the capacitor C1 and to the power supply line 4. The drain of the drive transistor Tr2 is connected to the anode terminal of the organic EL element E1 as a light emitting element, and the cathode terminal of the organic EL element E1 is connected to the reference potential point (ground) of the circuit.
[0015]
In the circuit configuration of the pixel 1 described above, when the ON voltage Select is supplied to the gate of the write transistor Tr1 via the scanning line 2 in the address period, the write transistor Tr1 is turned on. In response to the data voltage Vdata corresponding to the write data from the data line 3 supplied to the source of the write transistor Tr1, the write transistor Tr1 passes a current corresponding to the data voltage Vdata from the source to the drain. Therefore, the capacitor C1 is charged while the gate of the write transistor Tr1 is on-voltage, and the charge voltage corresponds to the data voltage Vdata.
[0016]
On the other hand, a charge voltage charged in the capacitor C1 is supplied to the drive transistor Tr2 as a gate voltage, and the drive voltage Vcc supplied from the power supply line 4 which is the gate voltage and the source voltage to the drive transistor Tr2. Current flows from the drain to the EL element E1, and the EL element E1 is driven to emit light by the drain current of the driving transistor Tr2.
[0017]
Here, when the addressing operation corresponding to one scanning line 2 is completed and the gate of the write transistor Tr1 becomes an off voltage, the write transistor Tr1 becomes a so-called cutoff, and the drain side of the transistor Tr1 becomes open. However, the gate voltage of the drive transistor Tr2 is held by the charge accumulated in the capacitor C1, and the same drive current is maintained until the data voltage Vdata is rewritten in the next address period, and the EL element E1 emits light based on this drive current. The state continues.
[0018]
The pixel 1 described above is arranged in a matrix on the light emitting display panel 10 shown in FIG. 2 to form a dot matrix type display panel. Each pixel 1 includes each scanning line 2 and each data line 3. It is formed at each crossing position. FIG. 2 is a block diagram showing the configuration of the light emitting display panel 10 and its driving circuit.
[0019]
The video signal displayed on the light emitting display panel 10 is supplied to the light emission control circuit 11 shown in FIG. In the light emission control circuit 11, the input video signal is converted into pixel data corresponding to each pixel by performing sampling processing or the like based on the horizontal synchronizing signal and the vertical synchronizing signal in the video signal, and is not shown. The operation of sequentially writing to the frame memory is executed. In the address period after the writing process of pixel data for one frame in the frame memory is completed, serial pixel data read from the frame memory for each one scanning line is sequentially transferred to the shift register in the data driver 12. And supplied to the data latch circuit 13.
[0020]
The shift register and data latch circuit 13 operates to latch pixel data corresponding to one horizontal scan and supply parallel data corresponding to one horizontal scan to the level shifter 14 when the pixel data is captured. Although not shown in FIG. 2, the data line 3 is arranged in the column direction corresponding to each pixel on the display panel 10, and these data lines 3 are connected to the level shifter 14. With this configuration, the data voltage Vdata corresponding to the pixel data is individually supplied to the source of the data write transistor Tr1 constituting each pixel 1. The above-described operation is repeated for each scan in the address period.
[0021]
Further, the light emission control circuit 11 supplies a scanning clock signal corresponding to the horizontal synchronizing signal to the operation driver 16 in the address period. Although not shown in FIG. 2, the scanning line 2 is arranged in the row direction corresponding to each pixel on the display panel 10, and these scanning lines 2 are connected to the scanning driver 16. ing. With this configuration, the above-described ON voltage Select is sequentially supplied to the gate of the data write transistor Tr1 constituting each pixel 1 for each scanning line 3.
[0022]
Accordingly, for each scan in the address period, each pixel 1 on the display panel 10 arranged in the scan line is supplied with the on-voltage Select from the scan driver 16. In synchronization with this, the data voltage Vdata is supplied from the level shifter 14 to each pixel 1 arranged for each scanning line, and the data voltage Vdata is written to each pixel corresponding to the scanning line. Then, by performing this operation over all scanning lines, an image corresponding to one frame is reproduced on the display panel 10.
[0023]
On the other hand, each pixel 1 arranged in the display panel 10 is configured to be supplied with a drive voltage Vcc from the power supply circuit 17 through the power supply line 4 described above. In the embodiment shown in FIG. 2, a gradation control signal is supplied from the light emission control circuit 11 to the power supply circuit 17. A specific example of gradation control based on this gradation control signal will be described later in detail.
[0024]
Further, in the embodiment shown in FIG. 2, digital data corresponding to the correction data set for each scanning line is supplied from the light emission control circuit 11 to the DAC (Digital to Analog Converter) 18. It is configured. The DAC 18 supplies an analog signal corresponding to the digital data to the level shifter 14. The level shifter 14 simultaneously shifts the potential of the data line based on the analog signal from the DAC 18 for each scan line scan. To work.
[0025]
The correction data set for each scanning line is stored in a non-volatile data memory 19 such as an EEPROM connected to the light emission control circuit 11. The light emission control circuit 11 reads the correction data from the data memory 19 for each scanning line in synchronization with the light emission control of the display panel, and supplies the digital data corresponding to the read correction data to the DAC 18. To do. The operation for level shifting the potential of the data line 3 based on the correction data will be described later in detail.
[0026]
Next, FIG. 3 explains a control mode of the gradation control executed in the embodiment shown in FIG. In this embodiment, in order to realize multi-gradation expression, a unit frame, for example, one frame of light emission possible period is divided into 15 subframes as shown in FIG. Then, by controlling the number of lighting in the subframe, it is possible to realize 16 gradation expressions (15 + 1 gradation expression when 100% non-lighting is also considered as one gradation).
[0027]
As an example, when the gradation is set to “10”, for example, the EL element is controlled to be turned on in the 1 to 10 subframe periods in the 1 frame light emission possible period shown in FIG. In the fifteen subframe period, an operation for turning off the EL element is executed. As a result, the EL element is subjected to lighting control in units of subframes, and time gradation is realized.
[0028]
The time gradation described above is executed by a gradation control signal supplied from the light emission control circuit 11 to the power supply circuit 17 in the embodiment shown in FIG. The light emission control circuit 11 is configured to send a gradation control signal to the power supply circuit 17 based on, for example, a gradation control command that has been artificially received. The power supply circuit 17 controls the supply operation of the drive voltage Vcc supplied to each pixel 1 through the power supply line 4 in units of the subframe period, thereby turning on the EL element. Time is controlled in units of subframes, and time gradation is realized. Therefore, in this embodiment, the light emission control circuit 11 and the power supply circuit 17 constitute a gradation control means.
[0029]
According to the gradation expression by the time gradation described above, since the sub-frame is formed by dividing the light emission possible period corresponding to one frame into substantially the same time interval, a particularly high resolution is required for the control. However, digital gradation control can be realized by using an operation clock having a relatively low frequency. Therefore, it is possible to prevent an increase in power consumption caused by increasing the speed of the clock signal.
[0030]
The gradation control described above is called the unweighted subframe method as described above, and the relationship between gradation and light emission luminance is almost linear (γ = 1). Therefore, in order to realize ideal γ correction of about γ = 2.0 as described above, in this embodiment, γ correction corresponding to gradation can be realized as shown in FIG. It is configured as follows. That is, the vertical axis shown in FIG. 3B indicates the level of the data voltage Vdata supplied to the source of the write transistor Tr1 constituting each pixel 1.
[0031]
The data voltage Vdata is changed according to the setting level of the gradation control described above. For example, when the gradation is set to “10” as described above, the data voltage Vdata output from the level shifter 14 is changed as shown in FIG. A voltage value corresponding to the numerical value “10” shown in (b) is output. In short, when the gradation setting is relatively low, the data voltage Vdata is also low, and when the gradation is relatively high, the data voltage Vdata is also high. The change in the data voltage Vdata described above acts as a change in the charge voltage to the capacitor C1 in the configuration of the pixel 1 shown in FIG. 1, and changes the light emission luminance of the EL element. Thus, γ correction is realized in an analog manner.
[0032]
The γ correction control operation described above is executed by supplying digital data corresponding to the gradation setting state from the light emission control circuit 11 to the DAC 18. That is, the DAC 18 generates an analog voltage based on the digital data from the light emission control circuit 11, and this analog voltage is supplied to the level shifter 14. The level shifter 14 receives the analog voltage from the DAC 18 and operates to shift the level of the data voltage Vdata. Therefore, in this embodiment, the DAC 18 and the level shifter 14 constitute level shift means.
[0033]
Next, FIG. 4 explains a control mode for correcting the in-plane variation in the data line direction made by the embodiment shown in FIG. The above-described in-plane variation in the data line direction is caused by the film forming conditions of the TFT or EL element when the light emitting display panel 10 is formed. That is, slight variations in the manufacturing process such as the film forming conditions affect the voltage-current characteristics and the like for TFTs, and affect the current-to-light emission luminance characteristics and the like for EL elements. As a result, the light emission luminance varies for each pixel.
[0034]
The correction operation shown in FIG. 4 effectively corrects the in-plane variation particularly generated in the data line direction as described above, and scan lines 1 to 1 corresponding to one frame period (or one subframe period). An example of a setting state of correction data when sequentially scanning N is shown. First, FIG. 4A shows a scanning selection operation in the address period. In this scanning selection operation, scanning is sequentially performed from the scanning line 1 to N in the address period.
[0035]
On the other hand, FIG. 4B shows the value (voltage) of the data voltage Vdata sequentially output from the level shifter 14 corresponding to the scanning of each scanning line. Note that the data voltage Vdata shown in FIG. 4B shows a case where a specific gradation state is set, and therefore, the correction value of the data voltage Vdata based on the already described γ correction is also included. Yes. As shown in FIG. 4B, the data voltage Vdata is changed for each scanning line and supplied to the source of the writing transistor Tr1 in each pixel 1 to be scanned. Thereby, the light emission luminance of the EL element is controlled for each scanning line, and it is possible to correct the variation in the light emission luminance of the EL element generated in the data line direction.
[0036]
The output pattern of the data voltage Vdata for each scanning line shown in FIG. 4B is generated by the correction data stored in the data memory 19 shown in FIG. 2 as described above. That is, the light emission control circuit 11 operates to read the correction data from the data memory 19 for each scanning line and supply digital data corresponding to the read correction data to the DAC 18 in the address period.
[0037]
The DAC 18 that receives the digital data generates an analog voltage based on the digital data and supplies the analog voltage to the level shifter 14. The level shifter 14 receives the analog voltage from the DAC 18 and performs an operation for level-shifting the data voltage Vdata for each line, thereby generating an output pattern of the data voltage Vdata shown in FIG. 4B.
[0038]
The correction data stored in the data memory 19 is preferably set in the data memory 19 by measuring in-plane variations occurring in the data line direction on each display panel. However, when the tendency of in-plane variation is clear, correction data that can be used in common may be used for each display panel specification.
[0039]
FIG. 5 shows the form of another pixel constituting the light-emitting display panel that is lighted and driven by the drive device according to the present invention. That is, the form of the pixel indicated by reference numeral 1 shown in FIG. 5 shows a pixel configuration composed of 3 TFTs adopting a lighting driving method called a simultaneous erasing method (SES = Simultaneous Erasing Scan) that realizes time-division gradation expression. .
[0040]
The configuration of the pixel 1 includes an erasing transistor Tr3 as an erasing TFT in addition to the circuit configuration of the pixel already described with reference to FIG. In FIG. 5, portions corresponding to the respective components described based on FIG. 1 are denoted by the same reference numerals, and therefore description thereof is omitted. As shown in FIG. 5, the source and drain of the erasing transistor Tr3 are connected to each end of the capacitor C1, and the gate of the erasing transistor Tr3 is connected to an erasing signal line (hereinafter also referred to as erasing line) 5. The erase signal Erase is supplied via the erase line.
[0041]
FIG. 6 is a block diagram showing the configuration of the light emitting display panel 10 in which the pixels 1 shown in FIG. 5 are arranged and the drive circuit thereof. Also in FIG. 6, portions corresponding to the respective components described based on FIG. 2 are denoted by the same reference numerals, and therefore description thereof is omitted. In the embodiment shown in FIG. 6, an erase driver 20 is newly provided as compared with the embodiment shown in FIG. The erasing driver 20 operates to supply an erasing signal Erase for turning on the erasing transistor Tr3 from the erasing driver 20 during the lighting period of the EL element E1 (for example, in the middle of one frame period).
[0042]
As a result, the charge charged in the capacitor C1 is erased (discharged) instantaneously. As a result, the drive transistor Tr2 is cut off, and the EL element E1 is immediately turned off. In other words, by controlling the output timing of the gate-on voltage (erase signal Erase) from the erase driver 20, the lighting period of the EL element E1 is controlled, thereby realizing multi-gradation expression.
[0043]
In the embodiment shown in FIG. 6, the erase signal Erase is output from the erase driver 20 in units of one subframe shown in FIG. Thereby, gradation control of a total of 16 gradations can be realized. Therefore, in this embodiment, the gradation control means is constituted by the erasing transistor Tr3 and the erasing driver 20 constituting each pixel. The γ correction at this time is realized by level-shifting the data voltage Vdata output from the level shifter 14 by the DAC 18 as described based on the embodiment shown in FIG.
[0044]
The means for correcting the in-plane variation occurring in the data line direction is the same as in the embodiment shown in FIG. 2, and digital data corresponding to the correction data read from the data memory 19 is supplied to the DAC 18. To be made. The level shifter 14 receives the analog voltage from the DAC 18 and executes an operation for level-shifting the data voltage Vdata for each line. Thereby, the in-plane variation generated in the data line direction can be corrected.
[0045]
Therefore, also in the configuration shown in FIG. 6, the same operation and effect as the configuration shown in FIG. 2 can be obtained.
[Brief description of the drawings]
FIG. 1 is a connection diagram showing the form of one pixel that is lit and driven by a drive device according to the present invention;
2 is a block diagram illustrating a configuration of a light-emitting display panel in which the pixels illustrated in FIG. 1 are arranged and a driving circuit thereof.
FIG. 3 is a timing chart for explaining gradation control and γ correction means.
FIG. 4 is a timing chart for explaining means for correcting in-plane variation occurring in the data line direction.
FIG. 5 is a connection diagram showing the form of another pixel that is driven to be lit by the drive device according to the present invention;
6 is a block diagram showing a configuration of a light emitting display panel in which the pixels shown in FIG. 5 are arranged and a drive circuit thereof.
[Explanation of symbols]
1 pixel 2 scan line (scan line)
3 data lines (data lines)
4 Power supply line 5 Erase line (erase signal line)
DESCRIPTION OF SYMBOLS 10 Light emission display panel 11 Light emission control circuit 12 Data driver 14 Level shifter 16 Scan driver 17 Power supply circuit 18 DAC
19 Data memory C1 Capacitor E1 Light emitting element (EL element)
Tr1 Write transistor Tr2 Drive transistor Tr3 Erase transistor

Claims (7)

A light emitting element whose emission is controlled via a lighting driving transistor, a data writing transistor for controlling a gate potential of the lighting driving transistor, and a charge holding capacitor for holding the gate potential controlled by the data writing transistor. A display configured by disposing at least each pixel provided at the intersection of a plurality of data lines and a plurality of scanning lines,
A gradation control unit that realizes gradation control by dividing a unit frame period of a video signal into a plurality of equally subframe periods and controlling lighting of the light emitting elements for each subframe period, and each scanning line based on the correction data for realizing a set γ correction and data line direction to produce brightness variation correction every, the level a potential corresponding to the write data supplied to the data write transistor via each data line A display comprising a level shift means for shifting. The display according to claim 1, further comprising: an erasing transistor that realizes the gradation control by erasing the electric charge accumulated in the capacitor at a timing of the subframe period.   3. The display according to claim 1, wherein the level shift unit includes a DAC that shifts a potential corresponding to write data based on the correction data.   The correction data set for each scanning line is stored in a non-volatile memory, and the correction data is sequentially read from the non-volatile memory when the display is turned on. The display according to any one of claims 1 to 3.   The display according to any one of claims 1 to 4, wherein the light-emitting element is composed of an organic EL element using an organic compound in a light-emitting layer. A light emitting element whose emission is controlled via a lighting driving transistor, a data writing transistor for controlling a gate potential of the lighting driving transistor, and a charge holding capacitor for holding the gate potential controlled by the data writing transistor. A display driving method in which each pixel provided at least is arranged at a crossing position of a plurality of data lines and a plurality of scanning lines, respectively.
The unit frame period of the video signal is divided into a plurality of equally spaced subframe periods, and gradation control is performed by controlling lighting of the light emitting elements for each subframe period, and is set for each scanning line. The potential of write data supplied to the data write transistor via each data line is level-shifted based on correction data for realizing γ correction and correction of luminance variations occurring in the data line direction. To drive the display.   7. The display driving method according to claim 6, wherein the correction data is stored in a non-volatile memory, and an operation of sequentially reading out the correction data from the non-volatile memory is performed when the display is turned on. .

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