JP4655497B2 - Pixel circuit driving method, pixel circuit, electro-optical device, and electronic apparatus - Google Patents

Description

The present invention relates to a pixel circuit driving method, a pixel circuit, an electro-optical device, and an electronic apparatus, and more particularly to differential driving of a pixel circuit.

In recent years, flat panel displays (FPD) using organic EL (Electronic Luminescence) elements have attracted attention. The organic EL element is one of current-driven elements that are driven by a drive current that flows through the organic EL element, and emits light with a luminance corresponding to the current level. There are a current programming method and a voltage programming method as a data writing method for a pixel circuit having such an element. The current program method is a method in which data is supplied to the data lines connected to the pixel circuits on a current basis, and the voltage program method is a method in which this data supply is performed on a voltage basis.

In Patent Document 1, the display image signal in the previous frame and the difference signal between it in the current frame are input, and analog gradation data obtained by synthesizing them is output to the pixel circuit, thereby reducing power consumption. A liquid crystal display device for achieving the above is disclosed.
JP 2000-284755 A

In Patent Document 1, the gradation data supplied from the data line driving circuit to the pixel circuit via the data line is completely updated every scan, and thus it is difficult to achieve sufficient power consumption reduction. .

  An object of the present invention is to provide a novel drive control of a pixel circuit.

Another object of the present invention is to reduce power consumption in driving a pixel circuit.

In order to solve such a problem, the first invention holds the first data supplied from the data line in the first frame and generates the first drive current corresponding to the held data. The difference data corresponding to the difference between the first data and the drive data and the gradation data supplied from the data line in the second frame after the first frame and defining the gradation in the second frame As the second data, and the other drive system that generates the second drive current according to the held data, and the first drive current and the second drive current in the second frame Provided is a pixel circuit having an electro-optic element that is set to a luminance equivalent to gradation data by supplying a synthesized current.

Here, in the first invention , the other drive system includes a first capacitor that holds the second data, a gate connected to the first capacitor, and is held by the first capacitor. A first drive element that generates a second forward drive current that is at least a part of the second drive current according to the data, a second capacitor that holds the second data, and a second capacitor Is connected to the gate of the second capacitor, and at least a part of the second drive current according to the data held in the second capacitor, and is opposite to the second forward drive current. It is preferable to have the 2nd drive element which produces | generates reverse drive current of this.

In the first invention , the first data is difference data corresponding to the difference between the gradation data defining the gradation in the first frame and the difference data in the third frame before the first frame. There may be. In this case, one of the drive systems has a third capacitor that holds the first data, a gate connected to the third capacitor, and the data held in the third capacitor, A third drive element that generates a first forward drive current that is at least part of the first drive current, a fourth capacitor that holds the first data, and a gate connected to the fourth capacitor And generates a first reverse drive current that is at least part of the first drive current and is opposite to the first forward drive current in accordance with the data held in the fourth capacitor. And a fourth driving element.

  Further, the first data may be gradation data that defines the gradation in the first frame. In this case, one of the drive systems has a third capacitor that holds the first data, a gate connected to the third capacitor, and the data held in the third capacitor, It is preferable to have a third drive element that generates the first drive current.

In the first invention , the first switching element for selectively supplying the first data of the voltage level supplied to the data line to one electrode of the capacitor included in one drive system, and the first switching element supplied to the data line There may be further provided a second switching element that selectively supplies the second data of the voltage level to one electrode of the capacitor included in the other drive system.

In the first invention , the first driving element is selectively diode-connected, and the first data of the current level supplied to the data line is supplied to the channel of the driving element included in one driving system. The switching element and the second driving element are selectively diode-connected, and the second data of the current level supplied to the data line is supplied to the channel of the driving element included in the other driving system. A switching element may be further provided.

The second invention provides a plurality of scanning lines, a plurality of data lines, a plurality of pixel circuits provided corresponding to the intersection of the scanning lines and the data lines, and a scanning signal output to the scanning lines, A scanning line driving circuit for selecting a scanning line corresponding to a pixel circuit to which data is to be written, and data for outputting data to a data line corresponding to the pixel circuit to be written in cooperation with the scanning line driving circuit. An electro-optical device having a line driving circuit is provided. Here, the pixel circuit is the pixel circuit according to the first invention described above.

A third invention provides an electronic apparatus in which the electro-optical device according to the second invention is mounted.

According to a fourth aspect of the present invention, there is provided a first step of holding the first data supplied from the data line in the first frame in the capacitor included in one drive system, and a capacitor included in the other drive system. Difference data corresponding to the difference between the first data and the gradation data supplied from the data line in the second frame after the first frame and defining the gradation in the second frame is the second data. In the second step and the second frame, the drive element included in one drive system generates a first drive current according to the first data, and the drive element included in the other drive system Generates a second drive current according to the second data, and supplies a combined current obtained by combining the first drive current and the second drive current to the electro-optic element, whereby the luminance of the electro-optic element Is equivalent to gradation data To provide a method of driving a pixel circuit having a third step of setting.

Here, in the fourth invention , the first data corresponds to a difference between the difference data in the third frame before the first frame and the gradation data defining the gradation in the first frame. It may be difference data. Further, the first data may be gradation data that defines the gradation in the first frame.

In the present invention, a plurality of drive systems are provided in the pixel circuit, and data is alternately supplied to each drive system, and the luminance of the electro-optical element is set based on the combined current of these drive systems. Thereby, it is possible to reduce power consumption in driving the pixel circuit.

(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel that drives an electro-optical element by, for example, a TFT (Thin Film Transistor). In the display unit 1, a group of pixels corresponding to m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 is provided with scanning line groups Y1 to Yn each extending in the horizontal direction and data line groups X1 to Xm each extending in the vertical direction. A pixel 2 (a pixel circuit described later) is arranged corresponding to the above. Note that one scanning line Y shown in the figure may indicate a set of a plurality of scanning lines, and one data line X shown in FIG. May indicate a set of data lines.

The control circuit 5 is based on an external signal from a host device (not shown) based on ST and CLX described later.
, Φ, LP, and the like are generated, and the scanning line driving circuit 3 and the data line driving circuit 4 are synchronously controlled based on these internal signals. Under this synchronous control, the drive circuits 3 and 4 perform display control of the display unit 1 in cooperation with each other. The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit, etc., and outputs a scanning signal SEL to the scanning lines Y1 to Yn. Scanning signal S
EL takes a binary signal level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and is a scanning line corresponding to a pixel row to which data is to be written. Y is set to the H level, and the other scanning lines Y are set to the L level. The scanning line driving circuit 3 sequentially sets each scanning line Y in a predetermined selection order (generally from the top to the bottom) every frame (1F) corresponding to the display period of one image. The line sequential scanning to be selected is performed.

The data line driving circuit 4 outputs data to the respective data lines X1 to Xm in synchronization with the line sequential scanning by the scanning line driving circuit 3. This output data is not the gradation data D itself that defines the gradation of the pixel 2, but “difference data ΔD” (in practice, between adjacent frames)
This is an analog signal). In this embodiment, “difference data ΔDi” of the i-th frame Fi is the difference value (Di−ΔDi−1) between the difference data ΔDi−1 of the immediately preceding frame Fi−1 and the gradation data Di of the frame Fi. Is defined as According to this definition, the relationship between the gradation data Di and the difference data ΔDi is, for example, as follows. Since the difference data ΔDi involves both positive and negative, a bit number (for example, 7 bits) obtained by adding one bit indicating positive / negative to the bit number (for example, 6 bits) of the gradation data Di is required.

(Relation between gradation data and difference data)
Frame Fi F1 F2 F3 F4 F5 ...
Gradation data Di 100 120 200 150 80 ...
Difference data ΔDi +100 +20 +180 -30 +110 ・ ・ ・

FIG. 2 is a configuration diagram of the data line driving circuit 4 to which 6-bit gradation data D (= D0 to D5) is input. The data line driving circuit 4 includes an m-bit X shift register 40 and m circuit units 41 provided in units of data lines. The X shift register 40 generates a start pulse ST supplied at the beginning of one horizontal scanning period (1H) as a clock signal CLX.
And the levels of the latch signals S1, S2, S3,.
Set to level.

The m circuit units 41 simultaneously output the current level difference data Idif for a pixel row in which data is written at a certain 1H, and gradation data D relating to a pixel row to be written in the next 1H.
The dot sequential latching is performed simultaneously. A single circuit unit 41 includes three switch groups 42.
, 44, 48, two latch circuits 43, 45, current DAC 46, at least (7 ×
n) It is composed of a pixel column memory 47 having a bit memory space and a difference calculation circuit 49. The operation of the individual circuit units 41 corresponding to the data lines X1 to Xm is performed by latch signals S1,
This is the same except that the fetch timing of the gradation data D by S2, S3,..., Sm is different. The foremost switch group 42 is turned on when the corresponding latch signal S becomes H level. As a result, 6-bit gradation data D is captured by the first latch circuit 43 at the capture timing defined by the latch signal S.

The difference calculation circuit 49 calculates a difference (D−ΔD) between the gradation data D latched by the first latch circuit 43 and the difference data ΔD with polarity held in the pixel column memory 47. The pixel column memory 47 stores difference data ΔD for one pixel column in the previous frame, and as the scanning lines Y are sequentially selected, the corresponding pixel difference data ΔD is sequentially updated. The difference calculation circuit 49 reads the difference data ΔD of the previous frame related to the same writing target as the gradation data D input at a certain 1H from the pixel column memory 47, and the difference data ΔD 1 and the gradation data D between the read difference data ΔD 1 and the gradation data D are read. New difference data ΔD corresponding to the difference is output. The difference data ΔD output from the calculation circuit 49 is transferred to the second latch circuit 45 at the timing when the latch pulse LP becomes H level and the switch group 44 is turned on. At the same time, the first latch circuit 43 receives the gradation data D in the next 1H via the switch group 42.
Are newly latched. A current DAC 46 corresponding to a variable current source 4a, which will be described later, D / A converts the difference data ΔD latched by the second latch circuit 45, and the difference data Idif generated as an analog current is applied to the data line X. Supply.

On the other hand, the difference data ΔD output from the difference calculation circuit 49 is transferred to the pixel column memory 47 at the capture timing when the control signal φ becomes H level and the switch group 48 is turned on.
This capture timing is set after the transfer of the difference data ΔD to the second latch circuit 44 is completed and before the latch of the gradation data D in the next 1H is started.
The difference data ΔD transferred to the pixel column memory 47 is replaced with the previous difference data ΔD related to the same pixel, and is held by the pixel column memory 47 until the next frame difference data ΔD is transferred.

Note that the difference data ΔD is directly applied to the data line driving circuit 4 from a host device (not shown).
In this case, the configuration of the data line driving circuit 4 can be greatly simplified.

FIG. 3 is a pixel circuit diagram of a current programming method according to the present embodiment. 1 shown in FIG.
The scanning line Y corresponds to a set of the three scanning lines Ya to Yc shown in the figure. This pixel circuit
It comprises an organic EL element OLED as an electro-optic element, 12 transistors T1 to T12, and 4 capacitors C1 to C4. A feature of the pixel circuit according to the present embodiment is that it includes two drive systems 20a and 2b that operate alternately. One drive system 20a has six circuit elements T2 to T5, C1 to C2, and the other drive system. 20b is composed of six circuit elements T8 to T11, C3 to C4. The organic EL element OLED represented as a diode is a typical current-driven element in which the luminance is set by a driving current flowing through itself (a synthesized current Ioled described later). The same applies to the embodiments described later, but the capacitors C1 to C4 have a capacity that can hold data of at least two frames. In the example of the figure,
The transistors T3 and T9 are p-channel type and others are n-channel type. However, this is only an example, and the channel type may be set in another combination. In this specification, regarding a transistor which is a three-terminal element including a source, a drain, and a gate, one of the source and the drain is referred to as “one terminal” and the other is referred to as “the other terminal”.

The gate of the transistor T1, which is a switching element, is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and one terminal thereof is the current level difference data Id.
It is connected to the data line X to which if is supplied. The other terminal of the transistor T1 is connected to a node N1 which is an input / output node of one drive system 20a. The gate of the transistor T6, which is a switching element, is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied, and one terminal thereof is connected to the node N1. The other terminal of the transistor T6 is connected to the anode (anode) of the organic EL element OLED. The cathode (cathode) of the organic EL element OLED is connected to a Vss terminal to which a reference voltage Vss lower than the power supply voltage Vdd is always supplied.

One drive system 20a provided between the transistors T1 and T6 includes three circuit elements T2,
It has a positive drive unit composed of T3 and C1, and a negative drive unit composed of three circuit elements T4, T5 and C2. For the positive drive part, the transistor T2 which is a switching element
Are connected to the first scanning line Ya, and one terminal thereof is connected to the node N1. The other terminal of the transistor T2 is commonly connected to the gate of a p-channel transistor T3, which is a driving element, and to one electrode of the capacitor C1. The other electrode of the capacitor C1 is connected to the Vdd terminal to which the power supply voltage Vdd is always supplied together with one terminal of the transistor T3, and the other terminal of the transistor T3 is connected to the node N1. On the other hand, regarding the negative drive unit, the gate of the transistor T4, which is a switching element, is connected to the first scanning line Ya in the same manner as the transistor T2, and one terminal thereof is connected to the node N.
Connected to one. The other terminal of the transistor T4 is commonly connected to the gate of an n-channel transistor T5, which is a driving element, and to one electrode of the capacitor C2.
The other electrode of the capacitor C2 is connected to the Vss terminal together with one terminal of the transistor T5, and the other terminal of the transistor T5 is connected to the node N1.

The gate of the transistor T7, which is a switching element, is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied, and one terminal thereof is connected to the data line X. The other terminal of the transistor T7 is connected to a node N2 which is an input / output node of the other drive system 20b. The gate of the transistor T12, which is a switching element, is connected to the third scanning line Yc similarly to the transistor T6, and one terminal thereof is connected to the node N2. The other terminal of the transistor T12 is connected to the anode of the organic EL element OLED.

The other drive system 20b provided between the transistors T7 and T12 includes three circuit elements T8,
It has a positive drive unit composed of T9, C3 and a negative drive unit composed of three circuit elements T10, T11, C4. For the positive drive part, the transistor T which is a switching element
The gate of 8 is connected to the second scanning line Yb, and one terminal thereof is connected to the node N2. The other terminal of the transistor T8 is commonly connected to the gate of a p-channel transistor T9, which is a driving element, and to one electrode of the capacitor C3. The other electrode of the capacitor C3 is connected to the Vdd terminal together with one terminal of the transistor T9.
The other terminal of the transistor T9 is connected to the node N2. As for the negative drive unit, the gate of the transistor T10 which is a switching element is the same as the second transistor T8.
Is connected to the scanning line Yb, and one terminal thereof is connected to the node N2. Also,
The other terminal of the transistor T10 is commonly connected to the gate of an n-channel transistor T11, which is a driving element, and to one electrode of the capacitor C4. The other electrode of the capacitor C4 is connected to the Vss terminal together with one terminal of the transistor T11.
The other terminal is connected to the node N2.

FIG. 4 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in the period t0 to t2 (or t2 to t4) corresponding to 1F described above are the data writing process in the period t0 to t1 (or t2 to t3) and the subsequent period t1 to t2 (or t3). To t4). The operation state of one drive system 20a is set by the first scanning signal SEL1, and the operation state of the other drive system 20b is set by the second scanning signal SEL2. Further, either the data writing process or the driving process is instructed by the third scanning signal SEL3. In the following description, in a plurality of consecutive frames shown in the figure, the i-th frame is Fi, the subsequent frame is Fi + 1, and the previous frame is Fi-1.

First, in the data writing period t0 to t1 of the frame Fi, since the first scanning signal SEL1 is at the H level, one drive system 20a is in the operating state. Specifically, at timing t0, the first scanning signal SEL1 rises from L level to H level. Thereby, the transistor T1 is turned on, and the input node N1 of one drive system 20a and the data line X are electrically connected. Regarding the positive drive unit, the transistor T2 is turned on, and one terminal of the p-channel transistor T3 and its own gate are diode-connected. The diode-connected transistor T3 has a gate voltage generated on the assumption that a channel current flows.
It functions as a programming element for writing data to the capacitor C1. The same applies to the negative drive section. The transistor T4 is turned on, and one terminal of the n-channel transistor T5 and its own gate are diode-connected. The diode-connected transistor T5 functions as a programming element for writing data to the capacitor C2 in accordance with a gate voltage generated on the assumption that a channel current flows. This period t0 ~
At t1, since the second scanning signal SEL2 is at the L level, the other drive system 20b remains in the non-operating state. Therefore, the capacitors C3 and C4 of the other drive system 20b continue to hold the differential data Idif (i-1) written in the previous frame Fi-1.

Which of the capacitors C1 and C2 of one drive system 20a is mainly used for data writing depends on the current direction of the difference data Idif (i) in the frame Fi. FIG.
), When the current direction of the difference data Idif (i) is set in the direction from the pixel circuit to the variable current source 4a (Idif (i) = Ipls1), the data write to the capacitor C1 in the positive drive unit is performed. Done. That is, the gate of the diode-connected transistor T3 is
A voltage Vg corresponding to the current level of the differential data Ipls1 flowing through its own channel is generated, and a charge corresponding to the potential difference between the gate voltage Vg and the power supply voltage Vdd is accumulated in the capacitor C1. In this case, since the channel current of the transistor T5 in the negative drive section is almost zero, the capacitor C2
The held data is reset to the threshold voltage Vth of the transistor T5. The difference data Idif (i) becomes Ipls1 when Di−ΔDi−1> 0, and the voltage level (absolute value) increases as the difference value increases.

On the other hand, as shown in FIG. 5B, when the current direction of the difference data Idif (i) is set to the direction from the variable current source 4a to the pixel circuit (Idif (i) = Imns1), the negative data Data is written to the capacitor C2 in the driving unit. That is, a voltage Vg corresponding to the current level of the differential data Imns1 flowing through its own channel is generated at the gate of the diode-connected transistor T5, and the charge corresponding to the potential difference between the gate voltage Vg and the power supply voltage Vss is stored in the capacitor C2. Accumulated in. In this case, since the channel current of the transistor T3 in the positive drive unit is almost zero, the data held in the capacitor C1 is reset to correspond to the threshold voltage Vth of the transistor T3. The difference data Idif (i) becomes Imns1 when (Di−ΔDi−1) <0, and the voltage level (absolute value) increases as the difference value increases.

In the data writing period t0 to t1, since the third scanning signal SEL3 is at the L level, the transistors T6 and T12 are turned off, the nodes N1 and N2 of the two drive systems 20a and 20b, and the organic EL
The anode of the element OLED is electrically separated. Therefore, in this period t0 to t1,
The organic EL element OLED does not emit light. This is because the data writing period t2-t of the next frame Fi + 1
The same applies to 3.

In the subsequent drive period t1 to t2, the drive currents Ioled1, Io from the two drive systems 20a, 20b
A combined current Ioled obtained by combining led2 is supplied to the organic EL element OLED. At timing t1, the first scanning signal SEL1 falls from the H level to the L level. Thereby, the transistor T1 is turned off, and the node N1 and the data line X of one drive system 20a are electrically separated. At the same time, the transistors T2 and T4 are also turned off, and the diode connection of the transistors T3 and T5 is eliminated. However, the previously written data is held in the capacitors C1 and C2. Accordingly, the gate voltage Vg corresponding to the data held in the capacitors C1 and C2 is continuously applied to the gates of the transistors T3 and T5 even after the timing t1. At this timing t1, the third scanning signal SEL3 rises from the L level to the H level. As a result, the transistor T6 is turned on, and the output node N1 of one drive system 20a and the organic EL
The anode of the element OLED is electrically connected. As a result, from one drive system 20a, organic E
A path of the drive current Ioled1 is formed that goes to the Vss terminal through the L element OLED. This drive current Ioled1 corresponds to the channel current of the transistor T3 (or T5), and its current level is based on its own gate voltage Vg, in other words, the capacitor C1 (or C2) that generates this gate voltage Vg. Are uniquely identified based on the stored data. In addition, timing t
1, the transistor T12 is turned on together with the transistor T6, and the output node N2 of the other drive system 20b is electrically connected to the anode of the organic EL element OLED. As a result, a path of the drive current Ioled2 is formed from the other drive system 20b to the Vss terminal through the organic EL element OLED. This drive current Ioled2 corresponds to the channel current of the transistor T9 (or T11), and its current level is based on its own gate voltage Vg, in other words, the capacitor C3 (or C4) that generates this gate voltage Vg. Are uniquely identified based on the stored data. The organic EL element OLED has a combined current Ioled that combines two drive currents Ioled1 and Ioled2.
Thus, the luminance of the organic EL element OLED is set to be equivalent to the original gradation data Di.

There are the following three combinations of combined currents Ioled (≧ 0) based on the drive currents Ioled1 and Ioled2. Note that there is no case where the combined current Ioled is negative due to the characteristics of the difference data ΔD, that is, the case where Ioled1 = Imns2 and Ioled2 = Imns2.

(Pattern 1) Ioled1 = Ipls1 and Ioled2 = Ipls2 (FIG. 5C)
When the difference data Idif (i) supplied to one drive system 20a in the frame Fi is Ipls1, a channel current flows through the transistor T3, and a forward drive current Ioled1 (= Ipls1) is generated. When the difference data Idif (i-1) supplied to the other drive system 20b in the frame Fi-1 is Ipls2, a channel current flows through the transistor T9, and the forward drive current Ioled2 (= I
pls2) is generated. In this case, the combined current Ioled is two forward drive currents Ioled1 and Ioled2.
Becomes the level (Ipls1 + Ipls2). The directions of the drive currents Ioled1 and Ioled2 are determined based on the current direction of the combined current Ioled, and the direction in which the combined current Ioled is increased is “forward”.
The direction in which the combined current Ioled is reduced is defined as “reverse direction”.

(Pattern 2) Ioled1 = Ipls1 and Ioled2 = Imns2 (FIG. 5D)
When the difference data Idif (i) supplied to one drive system 20a in the frame Fi is Ipls1, a channel current flows through the transistor T3, and a forward drive current Ioled1 (= Ipls1) is generated. When the difference data Idif (i-1) supplied to the other drive system 20b in the frame Fi-1 is Imns2, a channel current flows through the transistor T11 and the reverse drive current Ioled2 (=
Imns2) is generated. The combined current Ioled in this case has a level (Ipls1-Imns2) obtained by subtracting the reverse current Ioled2 in the opposite direction from the forward drive current Ioled1.

(Pattern 3) Ioled1 = Imns1 and Ioled2 = Ipls2
When the difference data Idif (i) supplied to one drive system 20a in the frame Fi is Imns1, a channel current flows through the transistor T5, and a reverse drive current Ioled1 (= Imns1) is generated. When the difference data Idif (i-1) supplied to the other drive system 20b in the frame Fi-1 is Ipls2, a channel current flows through the transistor T9, and the forward drive current Ioled2 (= I
pls2) is generated. The combined current Ioled in this case has a level (Ipls2-Imns1) obtained by subtracting the reverse current Ioled1 in the opposite direction from the forward drive current Ioled2.

In the data writing period t2 to t3 in the frame Fi + 1 following the frame Fi, since the second scanning signal SEL2 is at the H level, the other driving system 20b is in the operating state. This
Regarding the positive drive part of the other drive system 20b, the transistor T8 is turned on, and one terminal of the p-channel transistor T9 and its own gate are diode-connected. The diode-connected transistor T9 functions as a programming element for writing data to the capacitor C3 in accordance with a gate voltage generated on the assumption that a channel current flows.
The same applies to the negative drive unit, and the transistor T10 is turned on, and one terminal of the transistor T11 and its own gate are diode-connected. Diode-connected transistor T
11 is a capacitor C4 according to the gate voltage generated on the assumption that the channel current flows.
It functions as a programming element for writing data into the memory. This period t2 to t3
Then, since the first scanning signal SEL1 is at the L level, one drive system 20a is in a non-operating state. Therefore, the capacitors C1 and C2 of one drive system 20a are connected to the previous frame Fi.
The differential data Idif (i) written in (1) is continuously held.

Which of the capacitors C3 and C4 of the other drive system 20b is mainly used for data writing depends on the current direction of the difference data Idif (i + 1) in the frame Fi + 1. That is, when Idif (i + 1) = Ipls2, the capacitor C3 is provided by the transistor T9 of the positive drive unit.
Is written. In this case, the data held in the capacitor C4 is reset to be equivalent to the threshold voltage Vth of the transistor T11. The difference data Idif (i + 1) becomes Ipls2 when Di + 1−ΔDi> 0, and the voltage level (absolute value) increases as the difference value increases. On the other hand, when Idif (i + 1) = Imns2, the transistor T of the negative drive unit
11, data is written to the capacitor C4. In this case, the data held in the capacitor C3 is reset to be equivalent to the threshold voltage Vth of the transistor T9. Difference data Id
if (i + 1) becomes Imns2 when (Di + 1−ΔDi) <0, and the voltage level (absolute value) increases as the difference value increases.

In the subsequent drive period t3 to t4, the drive currents Ioled1, Io from the two drive systems 20a, 20b
A combined current Ioled obtained by combining led2 is supplied to the organic EL element OLED. At timing t3, the second scanning signal SEL2 falls from the H level to the L level. Thereby, the transistor T7 is turned off, and the node N2 and the data line X of the other drive system 20b are electrically separated. At the same time, the transistors T8 and T10 are also turned off, and the diode connection of the transistors T9 and T11 is eliminated. However, the previously written data is held in the capacitors C3 and C4. Accordingly, the gate voltage Vg corresponding to the data held in the capacitors C3 and C4 is continuously applied to the gates of the transistors T9 and T11 even after the timing t3. Also,
At this timing t3, the third scanning signal SEL3 rises from the L level to the H level. Thereby, the transistor T12 is turned on, and the output node N2 of the other drive system 20b and the anode of the organic EL element OLED are electrically connected. As a result, a path of the drive current Ioled2 is formed from the other drive system 20b to the Vss terminal through the organic EL element OLED. This drive current Ioled2 corresponds to the channel current of the transistor T9 (or T11), and its current level is based on its own gate voltage Vg, in other words, the capacitor C3 (or C4) that generates this gate voltage Vg. Are uniquely identified based on the stored data. At timing t3, the transistor T6 is turned on together with the transistor T12, and the output node N1 of one drive system 20a and the anode of the organic EL element OLED are electrically connected. As a result, a path of the drive current Ioled1 is formed from one drive system 20a through the organic EL element OLED to the Vss terminal. This drive current Ioled1 corresponds to the channel current of the transistor T3 (or T5), and its current level is based on its own gate voltage Vg, in other words, the capacitor C1 (or C2) that generates this gate voltage Vg. Are uniquely identified based on the stored data. The organic EL element OLED has a combined current I obtained by synthesizing two drive currents Ioled1 and Ioled2.
As a result, the luminance of the organic EL element OLED is set to be equivalent to the original gradation data Di + 1.

As described above, according to the present embodiment, in the current-programmed pixel circuit, the differential driving using the different difference data Idif (i) and Idif (i + 1) is performed to reduce the power consumption. It becomes possible. This is because in a case where writing with a small current is not a problem (for example, a small panel having a small capacity and a long writing time, a device that emits light with high brightness, driving in a high gradation region, etc.), a large current is applied to the data line X. This is because it is no longer necessary to supply. As a result, the power consumption of the current DAC in the data line driving circuit 4 can be reduced, and the circuit configuration can be simplified. It is also possible to reduce noise in the data line X existing between the current DAC and the pixel circuit. Furthermore, in the case of a large-scale display, gradation data is often output as it is, so that an intermediate circuit is loaded. However, in this embodiment, gradation data can be compressed and handled. Because you can
There is also an effect that such a load can be reduced.

In the above-described embodiment, the differential drive is performed in all the gradation regions. However, the differential drive using the difference data ΔD and the normal drive using the gradation data D are performed according to the gradation region. You may switch. For example, differential driving is performed when the luminance of the display unit 1 is generally high, and normal driving is performed when the luminance is low overall. As a result, it is possible to suppress insufficient data writing at the time of low gradation, which is a problem specific to the current programming method.
Further, the differential drive and the normal drive may be switched according to the display target. For example, display unit 1
When a moving image is displayed, differential driving is performed, and when a still image is displayed, normal driving is performed. As a result, unnecessary writing (scanning signal SE when displaying a still image) is performed.
Nothing is written in the L2 scan). Note that during normal driving, driving using only one drive system 20a may be performed by scanning the scanning signals SEL1 and SEL3 without scanning the scanning signal SEL2 shown in FIG. The above points are the same in each embodiment described later.

(Second Embodiment)
FIG. 6 is a pixel circuit diagram of a current programming method according to the present embodiment. 1 shown in FIG.
The scanning line Y corresponds to a set of the three scanning lines Ya to Yc shown in the figure. This pixel circuit
It is composed of an organic EL element OLED, 14 transistors T1 to T14, and 4 capacitors C1 to C4. The pixel circuit according to this embodiment also includes two drive systems 20a that operate alternately.
2b, one drive system 20a is composed of eight circuit elements T2 to T7, C1 to C2, and the other drive system 20b is composed of eight circuit elements T8 to T13 and C3 to C4. In addition,
In the example of the figure, the transistors T4, T8 to T12, and T14 are p-channel type, and the others are n-channel type, but this is only an example, and the channel type may be set in another combination.

The gate of the transistor T1, which is a switching element, is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied, and one terminal thereof is the current level difference data Id.
It is connected to the data line X to which if is supplied. The other terminal of the transistor T1 is connected to a node N1 which is an input / output node of one drive system 20a and also an input / output node of the other drive system 20b. The gate of the transistor T14, which is a switching element, is connected to the first scanning line Ya, and one terminal thereof is connected to the node N1. The other terminal of the transistor T14 is connected to the anode of the organic EL element OLED. The cathode of the organic EL element OLED is connected to the Vss terminal.

One drive system 20a has a positive drive unit composed of four circuit elements T2 to T4, C1, and a negative drive unit composed of four circuit elements T5 to T7, C2. With respect to the positive drive unit, the gate of the transistor T2, which is a switching element, is connected to the second scanning line Yb, and one terminal thereof is connected to the node N1. The other terminal of the transistor T2 is commonly connected to the gate of a p-channel transistor T4, which is a driving element, and to one electrode of the capacitor C1. The other electrode of the capacitor C1 is connected to the Vdd terminal together with one terminal of the transistor T4, and the other terminal of the transistor T4 is connected to one terminal of the transistor T3 which is a switching element. The gate of the transistor T3 is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied, and the other terminal is connected to the node N1. On the other hand, with respect to the negative drive unit, the gate of the transistor T5, which is a switching element, is connected to the second scanning line Yb in the same manner as the transistor T2, and one terminal thereof is connected to the node N1. The other terminal of the transistor T5 is connected to the gate of an n-channel transistor T7, which is a driving element, and to the capacitor C2.
Are commonly connected to one of the electrodes. The other electrode of the capacitor C2 is connected to the Vss terminal together with one terminal of the transistor T7, and the other terminal of the transistor T7 is connected to one terminal of the transistor T6 which is a switching element. This transistor T6
Is connected to the third scanning line Yc in the same manner as the transistor T3, and the other terminal is connected to the node N1.

The other drive system 20b has a positive drive unit composed of four circuit elements T8 to T10, C3 and a negative drive unit composed of four circuit elements T11 to T13, C4. With respect to the positive drive unit, the gate of the transistor T8, which is a switching element, is connected to the third scanning line Yc, and one terminal thereof is connected to the node N1. The other terminal of the transistor T8 is commonly connected to the gate of a p-channel transistor T10 which is a driving element and one electrode of the capacitor C3. The other electrode of the capacitor C3 is connected to the Vdd terminal together with one terminal of the transistor T10, and the other terminal of the transistor T10 is connected to one terminal of the transistor T9 which is a switching element. The gate of the transistor T9 is connected to the second scanning line Yb, and the other terminal is connected to the node N.
Connected to one. On the other hand, with respect to the negative drive unit, the transistor T1 which is a switching element
Similarly to the transistor T8, the gate of 1 is connected to the third scanning line Yc, and one terminal thereof is connected to the node N1. The other terminal of the transistor T11 is commonly connected to the gate of an n-channel transistor T13, which is a driving element, and to one electrode of the capacitor C4. The other electrode of the capacitor C4 is connected to the Vss terminal together with one terminal of the transistor T13, and the other terminal of the transistor T13 is connected to one terminal of the transistor T12 which is a switching element. The gate of this transistor T12 is
Similar to the transistor T9, it is connected to the second scanning line Yb, and the other terminal is connected to the node N.
Connected to one.

FIG. 7 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in the period t0 to t2 (or t2 to t4) corresponding to 1F described above are the data writing process in the period t0 to t1 (or t2 to t3) and the subsequent period t1 to t2 (or t3). To t4). Either the data writing process or the driving process is instructed by the first scanning signal SEL1. The second and third scanning signals SEL2,
The operating state of the drive systems 20a and 20b is set by SEL3.

First, in the data write period t0 to t1 of the frame Fi, since the first scanning signal SEL1 is at the H level, the transistor T1 is turned on and the node N1 and the data line X are electrically connected. Further, since the second and third scanning signals SEL2 and SEL3 are both at the H level, the transistors T2, T3, T5 and T6 are all turned on, and one drive system 20a is in an operating state. As a result, one terminal of the p-channel type transistor T4 in the positive drive section and its own gate are diode-connected. The diode-connected transistor T4 functions as a programming element for writing data to the capacitor C1 in accordance with a gate voltage generated on the assumption that a channel current flows. The same applies to the negative drive unit, and one terminal of the n-channel transistor T7 and its own gate are diode-connected. The diode-connected transistor T7 functions as a programming element for writing data to the capacitor C2 in accordance with a gate voltage generated on the assumption that a channel current flows.
Which of the capacitors C1 and C2 of one drive system 20a is mainly used to write data depends on the current direction of the difference data Idif (i) in the frame Fi as in the first embodiment described above. Yes. In this period t0 to t1, the second and third scanning signals SEL2
, SEL3, the transistors T8, T9, T11, and T12, all of which are turned off, are off, and the other drive system 20b remains inactive. Therefore, the other drive system 20b
The capacitors C3 and C4 continue to hold the differential data Idif (i-1) written in the previous frame Fi-1.

In the data writing period t0 to t1, since the first scanning signal SEL1 is at the H level, the transistor T14 is turned off, and the node N1 and the anode of the organic EL element OLED are electrically separated. Therefore, the organic EL element OLED does not emit light during this period t0 to t1. This point
The same applies to the data writing periods t2 to t3 of the next frame Fi + 1.

In the subsequent drive period t1 to t2, the drive currents Ioled1, Io from the two drive systems 20a, 20b
A combined current Ioled obtained by combining led2 is supplied to the organic EL element OLED. At timing t1, the first scanning signal SEL1 falls from the H level to the L level. Thereby, the transistor T1 is turned off, and the node N1 and the data line X are electrically separated. With that,
The transistor T14 is turned on, and the node N1 and the anode of the organic EL element OLED are electrically connected. Further, at the timing t1, the second scanning signal SEL2 also falls from the H level to the L level. Thereby, with respect to one drive system 20a, the transistors T2 and T5 are turned off, and the diode connection of the transistors T4 and T7 is eliminated. However, capacitor C1
, C2 holds previously written data. Accordingly, the gate voltage Vg corresponding to the data held in the capacitors C1 and C2 is continuously applied to the gates of the transistors T4 and T7 even after the timing t1. As a result, Vss from one drive system 20a through the organic EL element OLED.
A path of the drive current Ioled1 toward the terminal is formed. This drive current Ioled1 corresponds to the channel current of the transistor T4 (or T7), and its current level is determined by its own gate voltage V
In other words, it is uniquely specified based on data held in the capacitor C1 (or C2) that generates the gate voltage Vg. Further, since the second scanning signal SEL2 falls to the L level, the transistors T9 and T12 of the other drive system 20b are both turned on. As a result, the drive current I is directed from the other drive system 20b to the Vss terminal via the organic EL element OLED.
The pathway of oled2 is formed. This drive current Ioled2 corresponds to the channel current of the transistor T10 (or T13), and its current level is based on its own gate voltage Vg, in other words, the capacitor C3 (or C4) that generates this gate voltage Vg. Are uniquely identified based on the stored data. In the organic EL element OLED, a combined current Ioled obtained by synthesizing two driving currents Ioled1 and Ioled2 flows, and thereby the luminance of the organic EL element OLED is the original gradation data Di.
It is set considerably. Since the combined pattern of the combined current Ioled (≧ 0) based on the drive currents Ioled1 and Ioled2 is the same as that in the first embodiment described above, description thereof is omitted here.

In the data writing period t2 to t3 of the next frame Fi + 1, since the first scanning signal SEL1 is at the H level, the transistor T1 is turned on and the node N1 and the data line X are electrically connected. . Since the second and third scanning signals SEL2 and SEL3 are both at the L level, the transistors T8, T9, T11, and T12 are all turned on, and the other drive system 20b is in the operating state. As a result, one terminal of the p-channel type transistor T10 in the positive drive section and its own gate are diode-connected. The diode-connected transistor T10 functions as a programming element for writing data to the capacitor C3 in accordance with a gate voltage generated on the assumption that a channel current flows. The same applies to the negative drive unit, and one terminal of the n-channel transistor T13 and its own gate are diode-connected. The diode-connected transistor T13 functions as a programming element for writing data to the capacitor C4 in accordance with a gate voltage generated on the assumption that a channel current flows. Which of the capacitors C3 and C4 of the other drive system 20b is mainly used for data writing depends on the current direction of the difference data Idif (i + 1) in the frame Fi + 1. In this period t2 to t3, the transistors T2, T3, T5, and T6 controlled to conduct by the second and third scanning signals SEL2 and SEL3 are all off, so that one drive system 20a is in the non-operating state. It remains. Therefore, the capacitors C1 and C2 of one drive system 20a continue to hold the differential data Idif (i) written in the previous frame Fi.

In the subsequent drive period t3 to t4, the drive currents Ioled1, Io from the two drive systems 20a, 20b
A combined current Ioled obtained by combining led2 is supplied to the organic EL element OLED. At timing t3, the first scanning signal SEL1 falls from H level to L level. As a result, the transistor T1 is turned off to electrically isolate the node N1 and the data line X, and the transistor T14 is turned on to electrically connect the node N1 and the anode of the organic EL element OLED. . At the timing t3, the third scanning signal SEL3 rises from the L level to the H level. Thereby, with respect to the other drive system 20b, the transistors T8 and T11 are turned off, and the diode connection of the transistors T10 and T13 is eliminated. However, capacitor C3,
Since the previously written data is held in C4, the gate voltage Vg corresponding to the held data is continuously applied to the gates of the transistors T10 and T13 after the timing t3. In this period t3 to t4, since the second scanning signal SEL2 remains at the L level, the transistors T9 and T12 are continuously turned on. As a result, a path of the drive current Ioled2 is formed from the other drive system 20b to the Vss terminal through the organic EL element OLED. This drive current Io
led2 corresponds to the channel current of transistor T10 (or T13) and its current level is
Based on its own gate voltage Vg, in other words, it is uniquely specified based on data held in the capacitor C3 (or C4) that generates the gate voltage Vg. The third scanning signal S
As EL3 rises to the H level, transistors T3, T of one drive system 20a
6 turns on together. As a result, a path of the drive current Ioled1 is formed from one drive system 20a through the organic EL element OLED to the Vss terminal. This drive current Ioled1 corresponds to the channel current of the transistor T4 (or T7), and its current level is based on its own gate voltage Vg, in other words, the capacitor C1 (or C2) that generates this gate voltage Vg. Are uniquely identified based on the stored data. The organic EL element OLED has two drive currents Ioled
A combined current Ioled that combines 1 and Ioled2 flows, whereby the luminance of the organic EL element OLED is set to be equivalent to the original gradation data Di + 1.

As described above, according to the present embodiment, in the current-programmed pixel circuit, differential driving using different differential data Idif (i) and Idif (i + 1) is performed, thereby reducing power consumption. The same effect as in the first embodiment can be obtained.

(Third embodiment)
In the first and second embodiments described above, the differential driving of the current programming method has been described. In the third and fourth embodiments, application examples to the voltage programming method will be described. In the present embodiment, the data line driving circuit 4 shown in FIG. 1 includes a voltage DAC instead of the current DAC, and supplies voltage level difference data Vdif to the data lines X to Xm. In the present embodiment, the difference data V is based on the sign of the “difference data ΔD” between adjacent frames.
Determine dif. That is, when Di + 1−ΔDi> 0, a positive value Vpls is set as the difference data Vdif, and this is output to the first data line Xa. On the other hand, (Di + 1−Δ
In the case of Di) <0, a negative value Vmns is set as the difference data Vdif, and this is output to the second data line Xb. Further, one scanning line Y shown in FIG. 1 corresponds to the set of two scanning lines Ya and Yb shown in the figure, and one data line X shown in FIG. 1 shows two data shown in the figure. It corresponds to a set of lines Xa and Xb.

FIG. 8 is a pixel circuit diagram of a voltage program method according to the present embodiment. This pixel circuit is composed of an organic EL element OLED, eight transistors T1 to T8, and four capacitors C1 to C4. The pixel circuit according to the present embodiment also includes two drive systems 20a,
2b, one drive system 20a is composed of six circuit elements T1 to T4, C1 to C2, and the other drive system 20b is composed of six circuit elements T5 to T8 and C3 to C4. In the example of the figure, the transistors T2 and T6 are p-channel type and the others are n-channel type. However, this is only an example, and the channel type may be set in another combination.

One drive system 20a includes a positive drive unit configured by three circuit elements T1, T2, and C1, and a negative drive unit configured by three circuit elements T3, T4, and C2. With respect to the positive drive unit, the gate of the transistor T1, which is a switching element, is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied. One terminal of the transistor T1 is connected to the first data line Xa to which the voltage level difference data Vdif (= Vpls) is supplied, and the other terminal is connected to one electrode of the capacitor C1 and the drive. It is commonly connected to the gate of a p-channel transistor T2 which is an element. The other electrode of the capacitor C1 is connected to the Vdd terminal together with one terminal of the transistor T2, and the other terminal of the transistor T2 is connected to the node N1. On the other hand, regarding the negative drive unit, the gate of the transistor T3, which is a switching element, is connected to the first scanning line Ya in the same manner as the transistor T1. One terminal of the transistor T3 is connected to the second data line Xb to which the voltage level difference data Vdif (= Vmns) is supplied, and the other terminal is connected to one electrode of the capacitor C2 and the drive. It is commonly connected to the gate of an n-channel transistor T4 which is an element. The other electrode of the capacitor C2 is connected to the Vss terminal together with one terminal of the transistor T4, and the other terminal of the transistor T4 is connected to the node N1. Organic EL
The anode of the element OLED is connected to the node N1, and its cathode is connected to the Vss terminal.

The other drive system 20b has a positive drive unit composed of three circuit elements T5, T6, C3 and a negative drive unit composed of three circuit elements T7, T8, C4. Regarding the positive drive unit, the gate of the transistor T5, which is a switching element, is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied. One terminal of this transistor T5 is connected to the first
The other terminal is commonly connected to one electrode of the capacitor C3 and the gate of a p-channel transistor T6 which is a driving element. The other electrode of the capacitor C3 is connected to the Vdd terminal together with one terminal of the transistor T6, and the other terminal of the transistor T6 is connected to the node N1. On the other hand, regarding the negative drive unit, the gate of the transistor T7 which is a switching element is the same as that of the transistor T5.
Are connected to the scanning line Yb. One terminal of the transistor T7 is connected to the second data line X
The other terminal is connected in common to one electrode of the capacitor C4 and the gate of an n-channel transistor T8 that is a driving element. The other electrode of the capacitor C4 is connected to the Vss terminal together with one terminal of the transistor T8, and the other terminal of the transistor T8 is connected to the node N1.

FIG. 9 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in the period t0 to t2 (or t2 to t4) corresponding to 1F is performed in the period t0 to t1 (or t2).
To t3) and a driving process in the following period t1 to t2 (or t3 to t4).

First, in the data write period t0 to t1 of the frame Fi, data is written to the capacitors C1 and C2 of one drive system 20a. Specifically, at timing t0,
The first scanning signal SEL1 rises from the L level to the H level, and both the transistors T1 and T3 are turned on. The difference data Vdif (i) (= Vpls (i)) supplied from the first data line Xa is supplied to one electrode of the capacitor C1 through the transistor T1. As a result, data is written to the capacitor C1, and the charge corresponding to Vpls (i) is transferred to the capacitor C1.
Accumulated in. On the other hand, the difference data Vdif (i) (= Vmns (i) supplied from the second data line Xb.
)) Is supplied to one electrode of the capacitor C2 via the transistor T2. As a result, data is written to the capacitor C2, and charges corresponding to Vmns (i) are accumulated in the capacitor C2. In this period t0 to t1, since the second scanning signal SEL2 is at the L level, the other drive system 20b remains in the non-operating state. Therefore, the capacitors C3 and C4 of the other drive system 20b are connected to Vdif (i-1) (= Vpls (i-1) in the previous frame Fi-1.
), Vmns (i-1)).

In the subsequent drive period t1 to t2, a combined current Ioled obtained by combining drive currents from the two drive systems 20a and 20b is supplied to the organic EL element OLED. At timing t1, the first scanning signal SEL1 falls from the H level to the L level. As a result, the transistors T1 and T3 of one drive system 20a are both turned off, and the difference data Vdi for the data lines Xa and Xb.
The supply of f (i) is also stopped. However, since the voltage Vpls (i) is continuously applied to the gate of the transistor T2 according to the data held in the capacitor C1, the forward drive current Ipls1 corresponding thereto flows through the channel of the transistor T2. Similarly, since the voltage Vmns (i) is continuously applied to the gate of the transistor T4 according to the data held in the capacitor C2, the reverse drive current Imns1 corresponding thereto flows through the channel of the transistor T2. Therefore, the drive current output from one drive system 20a is (Ipls1-Imns1). Regarding the other drive system 20b, the voltage Vpls (i-1) is applied to the gate of the transistor T6 according to the data held in the capacitor C3, so that the forward drive current Ipls2 corresponding to the voltage Vpls (i-1) Flowing. Similarly, since the voltage Vmns (i-1) is applied to the gate of the transistor T8 according to the data held in the capacitor C4, the reverse drive current Imns2 corresponding thereto flows through the channel of the transistor T8. Therefore, the drive current output from the other drive system 20b is (Ipls2-Imns2). The final composite current Ioled is ((Ipls1-Imns1
) + (Pls2-Imns2)), and the organic EL element OLED is set to a luminance corresponding to the combined current Ioled flowing through it.

In the data writing period t2 to t3 of the next frame Fi + 1, data is written to the capacitors C3 and C4 of the other drive system 20b. Specifically, at timing t2,
The second scanning signal SEL2 rises from the L level to the H level, and both the transistors T5 and T7 are turned on. Difference data Vdif (i + 1) (= Vpls (i + 1)) supplied from the first data line Xa
) Is supplied to one electrode of the capacitor C3 via the transistor T5. As a result, data is written to the capacitor C3, and charges corresponding to Vpls (i + 1) are accumulated in the capacitor C3. On the other hand, the difference data Vdif (i + 1) (supplied from the second data line Xb
= Vmns (i + 1)) is supplied to one electrode of the capacitor C4 via the transistor T7. As a result, data is written to the capacitor C4, and charges corresponding to Vmns (i + 1) are accumulated in the capacitor C4. In this period t2 to t3, the first scanning signal SE
Since L1 is at the L level, one drive system 20a remains in a non-operating state. Therefore, the capacitors C1 and C2 of one drive system 20a are connected to Vdif (i) (
= Vpls (i), Vmns (i)) is continuously held.

In the subsequent drive periods t3 to t4, a combined current Ioled obtained by combining drive currents from the two drive systems 20a and 20b is supplied to the organic EL element OLED. At timing t3, the second scanning signal SEL2 falls from the H level to the L level. As a result, the transistors T5 and T7 of the other drive system 20b are both turned off, and the difference data Vdi with respect to the data lines Xa and Xb.
The supply of f (i + 1) is also stopped. However, the gate of transistor T6 has a capacitor C3.
Since the voltage Vpls (i + 1) is continuously applied according to the held data, the forward drive current Ipls2 corresponding to this voltage flows through the channel of the transistor T6. Similarly, since the voltage Vmns (i + 1) is continuously applied to the gate of the transistor T8 according to the data held in the capacitor C4, the reverse drive current Imns2 corresponding thereto flows through the channel of the transistor T8. In addition, with respect to one drive system 20a, since the voltage Vpls (i) is applied to the gate of the transistor T2 according to the data held in the capacitor C1, the forward drive current Ipls1 corresponding thereto flows through the channel of the transistor T2. Similarly, since the voltage Vmns (i) is applied to the gate of the transistor T4 according to the data held in the capacitor C2, the reverse drive current Imns1 corresponding to the voltage flows through the channel of the transistor T4. The final composite current Ioled is ((Ipls1-Imns1)
+ (Pls2-Imns2)), and the organic EL element OLED is set to a luminance corresponding to the combined current Ioled flowing through it.

As described above, according to the present embodiment, in the voltage-programmed pixel circuit, by performing differential driving using different differential data Vdif (i) and Vdif (i + 1), low power consumption is achieved. It becomes possible. This is because the voltage amplitude on the data line X can be kept low. As a result, the power consumption of the voltage DAC in the data line drive circuit 4 can be reduced, and the circuit configuration can be simplified. In addition, it is possible to reduce noise in the data line X existing between the voltage DAC and the pixel circuit. Furthermore, in the case of a large-scale display, gradation data is often output as it is, so that an intermediate circuit is loaded. However, in this embodiment, gradation data can be compressed and handled. Therefore, there is an effect that such a load can be reduced.

In this embodiment, when no drive current is output from the drive element as in the case where the difference value between adjacent frames is 0, the difference data Vdif such that the gate-source voltage Vgs is 0V. Is supplied to the pixel circuit. However, the difference data Vdif that gives a reverse bias to the drive element may be supplied to the pixel circuit within a range where the leakage current does not become a problem. As a result, particularly when a drive element is formed on an amorphous silicon substrate, the “Vth shift”, which is a problem, that is, the threshold voltage Vth of the drive element changes with time by only applying a bias in the same direction. Can be suppressed.

(Fourth embodiment)
In the present embodiment, the voltage program type pixel circuit shown in FIG. 8 is changed to share the two data lines Xa and Xb, and the data Vdif (= Vpls, Vmns) is supplied to one data line X. Supply in time division. One scanning line Y shown in FIG. 1 is a set of four scanning lines Ya to Yd.

FIG. 10 is a pixel circuit diagram according to the present embodiment. This pixel circuit is an organic EL element OLED
And eight transistors T1 to T8 and four capacitors C1 to C4. The pixel circuit according to the present embodiment also includes two drive systems 20a and 2b that operate alternately.
One drive system 20a is composed of six circuit elements T1 to T4, C1 to C2, and the other drive system 20b is composed of six circuit elements T5 to T8 and C3 to C4. In the example of the figure, the transistors T2 and T6 are p-channel type and the others are n-channel type. However, this is only an example, and the channel type may be set in another combination.

One drive system 20a includes a positive drive unit configured by three circuit elements T1, T2, and C1, and a negative drive unit configured by three circuit elements T3, T4, and C2. With respect to the positive drive unit, the gate of the transistor T1, which is a switching element, is connected to the first scanning line Ya to which the first scanning signal SEL1 is supplied. One terminal of the transistor T1 is connected to the data line X to which the voltage level difference data Vdif is supplied in a time-sharing manner, and the other terminal is connected to one electrode of the capacitor C1 and the driving element p. The channel type transistor T2 is commonly connected to the gate. The other electrode of capacitor C1 is connected to transistor T2.
And the other terminal of the transistor T2 is connected to the node N1. On the other hand, with respect to the negative drive unit, the gate of the transistor T3, which is a switching element, is connected to the second scanning line Yb to which the second scanning signal SEL2 is supplied. One terminal of the transistor T3 is connected to the data line X, and the other terminal is commonly connected to one electrode of the capacitor C2 and the gate of the n-channel transistor T4 which is a driving element. Yes. The other electrode of the capacitor C2 is connected to the Vss terminal together with one terminal of the transistor T4, and the other terminal of the transistor T4 is connected to the node N1. The anode of the organic EL element OLED is connected to the node N1, and its cathode is connected to the Vss terminal.

The other drive system 20b has a positive drive unit composed of three circuit elements T5, T6, C3 and a negative drive unit composed of three circuit elements T7, T8, C4. With respect to the positive drive unit, the gate of the transistor T5, which is a switching element, is connected to the third scanning line Yc to which the third scanning signal SEL3 is supplied. One terminal of the transistor T5 is connected to the data line X, and the other terminal is commonly connected to one electrode of the capacitor C3 and the gate of the p-channel transistor T6 which is a driving element. Yes. Capacitor C3
The other electrode of the transistor T6 is connected to the Vdd terminal together with one terminal of the transistor T6, and the other terminal of the transistor T6 is connected to the node N1. On the other hand, with respect to the negative drive unit, the gate of the transistor T7, which is a switching element, is connected to the fourth scanning line Yd to which the fourth scanning signal SEL4 is supplied. One terminal of the transistor T7 is connected to the data line X, and the other terminal is one electrode of the capacitor C4 and the driving element n.
The channel type transistor T8 is commonly connected to the gate. The other electrode of the capacitor C4 is connected to the Vss terminal together with one terminal of the transistor T8, and the other terminal of the transistor T8 is connected to the node N1.

FIG. 11 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in a period t0 to t3 (or t3 to t6) corresponding to 1F is a data writing process in a period t0 to t2 (or t3 to t5) (this process is further divided into two). And a driving process in a subsequent period t2 to t3 (or t5 to t6).

First, in the data writing period t0 to t2 of the frame Fi, data writing to the capacitors C1 and C2 of the one drive system 20a is sequentially performed with an offset. In the period t0 to t1, the first scanning signal SEL1 becomes H level and the transistor T1 is turned on, but the other transistors T3, T5, and T7 are off. Therefore, during this period t0 to t1, the difference data Vdif (i) (= Vpls (i)) supplied from the data line X passes through the transistor T1.
It is supplied to one electrode of the capacitor C1. As a result, data is written to the capacitor C1, and charges corresponding to Vpls (i) are accumulated in the capacitor C1. Next period t1 ~
At t2, the second scanning signal SEL2 becomes H and the transistor T3 is turned on, but the other transistors T1, T5, T7 are off. Therefore, during this period t1 to t2, the difference data Vdif (i) (= Vmns (i)) supplied from the data line X is passed through the transistor T3.
It is supplied to one electrode of the capacitor C2. As a result, data is written to the capacitor C2, and charges corresponding to Vmns (i) are accumulated in the capacitor C2. In the data writing period t0 to t2, since the third and fourth scanning signals SEL3 and SEL4 are at the L level, the other drive system 20b remains in the non-operating state. Therefore, the capacitors C3 and C4 of the other drive system 20b are connected to Vdif (i-1) (= Vpls (i-1), Vmns in the previous frame Fi-1.
Continue to hold (i-1)).

In the subsequent drive period t2 to t3, a combined current Ioled obtained by combining the drive currents from the two drive systems 20a and 20b is supplied to the organic EL element OLED, and the organic EL element OLED has a luminance corresponding to the combined current Ioled flowing through itself. Set to Since the synthesized current Ioled has been described in the third embodiment, a description thereof is omitted here.

In the data writing period t3 to t5 of the next frame Fi + 1, data writing to the capacitors C3 and C4 of one drive system 20a is sequentially performed with an offset. In the period t3 to t4, the third scanning signal SEL3 becomes H level and the transistor T5 is turned on, but the other transistors T1, T3, and T7 are turned off. Therefore, during this period t3 to t4, the difference data Vdif (i + 1) (= Vpls (i + 1)) of the frame Fi + 1 supplied from the data line X is supplied to one side of the capacitor C3 via the transistor T5. Supplied to the electrodes. As a result, data is written to the capacitor C3, and charges corresponding to Vpls (i + 1) are accumulated in the capacitor C3. In the subsequent period t4 to t5, the fourth scanning signal SEL4 becomes H and the transistor T7 is turned on, but the other transistors T1, T3, and T5 are turned off. Therefore, this period t4 ~
At t5, the difference data Vdif (i + 1) (= Vmns (i + 1)) supplied from the data line X is supplied to one electrode of the capacitor C4 via the transistor T7. As a result, data is written to the capacitor C4, and charges corresponding to Vmns (i + 1) are accumulated in the capacitor C4. In the data writing period t4 to t5, the first and second scanning signals SEL1,
Since SEL2 is at the L level, the drive system 20a remains in a non-operating state. Therefore, the capacitors C1 and C2 of one drive system 20a are connected to Vdif (i) in the previous frame Fi.
(= Vpls (i), Vmns (i)) is continuously held.

In the subsequent drive period t5 to t6, a combined current Ioled obtained by combining the drive currents from the two drive systems 20a and 20b is supplied to the organic EL element OLED, and the organic EL element OLED has a luminance corresponding to the combined current Ioled flowing through it. Set to

As described above, according to the present embodiment, in the voltage-programmed pixel circuit, differential driving using different differential data Vdif (i) and Vdif (i + 1) is performed, thereby reducing power consumption. The same effect as in the third embodiment can be obtained. Further, since the data Vdif is supplied to one data line X in a time division manner, the number of data lines X can be reduced as compared with the fourth embodiment.

(Fifth embodiment)
In each of the above-described embodiments, the difference data Idif (or Vdif) is alternately written for each frame. However, gradation data is written in one frame (for example, an odd frame) and the other frame (for example, an even number). Difference data may be written in (frame).
In this case, regarding the drive system 20a (or 20b) driven in one frame,
It is not necessary to have two drive systems, and only a single drive system is sufficient.

FIG. 12 is a pixel circuit diagram of a voltage program method according to the present embodiment. First, the circuit configuration is characterized by the circuit element T constituting the negative drive section of one drive system 20a shown in FIG.
3, T4, C2 is lost. Second, a p-channel transistor T9, which is a switching element, is added between the node N1 and the other drive system 20b. The conduction of the transistor T9 is controlled by the third scanning signal SEL3. The control signal SEL3 is set to the H level in the frame Fi that performs normal driving, and is set to the L level in the frame Fi + 1 that performs differential driving. In addition, since it is the same as that of the structure of FIG. 8 about other points,
The same reference numerals are given, and description thereof is omitted here.

FIG. 13 is an operation timing chart of the pixel circuit shown in FIG. A series of operation processes in a period t0 to t2 (or t2 to t4) corresponding to 1F includes a data writing process in a period t0 to t1 (or t2 to t3) and a subsequent period t1 to t2 (or t3 to t4). ) Driving process.

First, in the data write period t0 to t1 of the frame Fi, data is written to the capacitor C1 of one drive system 20a. Here, it should be noted that the data supplied to one drive system 20a is the gradation data Vdata (i) of the frame Fi irrespective of the difference data Vdif (i-1) of the previous frame Fi-1. I want to be. Thereby, the gradation data V is stored in the capacitor C1.
Charges corresponding to data (i) are accumulated. In this period t0 to t1, the second scanning signal SE
Since L2 is at the L level, the other drive system 20b remains in a non-operating state. Therefore, the capacitors C3 and C4 of the other drive system 20b are connected to Vdif (i-1 in the previous frame Fi-1.
) (= Vpls (i-1), Vmns (i-1)).

In the subsequent drive period t1 to t2, the drive current Ioled1 from one drive system 20a is the combined current Io.
It is supplied to the organic EL element OLED as led. At timing t1, the first scanning signal SE
L1 falls from the H level to the L level. As a result, the transistor T1 of one drive system 20a is turned off, but the voltage Vdata (i) is continuously applied to the gate of the transistor T2 by the data held in the capacitor C1. Therefore, the forward drive current Ioled1 corresponding to this
Flows through the channel of transistor T2. On the other hand, the other drive system 20b is electrically isolated from the node N1 because the transistor T9 whose conduction is controlled by the third scanning signal SEL3 is off. Accordingly, the combined current Ioled is the drive current Ioled1 itself output from the one drive system 20a.

In the data writing period t2 to t3 of the next frame Fi + 1, data is written to the capacitors C3 and C4 of the other drive system 20b. Here, the data supplied to the other drive system 20b is the difference data Vdif (i + 1) (= Vpls (i + 1),) of the frame Fi + 1 with respect to the gradation data Vdataf (i) of the previous frame Fi. It should be noted that Vmns (i + 1), so that charges corresponding to the difference data Vdif (i + 1) are accumulated in the capacitors C3 and C4 during this period t3.
From .about.t4, since the first scanning signal SEL1 is at the L level, the drive system 20a remains in the non-operating state. Therefore, the capacitor C1 of one drive system 20a continues to hold Vdata (i) in the previous frame Fi.

In the subsequent drive period t3 to t4, the drive current Ioled1 is output from one drive system 20a.
At the same time, since the transistor T9 whose conduction is controlled by the third scanning signal SEL3 is turned on, a driving current (Ipls2-Imns2) is also output from the other driving system 20b. Therefore, the combined current Ioled is (Ioled1 + (Ipls2-Imns2)).

According to the present embodiment, the same effects as those of the above-described embodiments can be obtained, and the data write amount can be biased to odd frames. Therefore, since a large writing time can be allocated to a frame with a small amount of writing, it is possible to solve the shortage of data writing.

Further, in the present embodiment, the alternate writing of gradation data and difference data, which are different data, has been described in the application example to the voltage program method using the pixel circuit of FIG. 12 as an example.
However, the present invention is naturally applicable to pixel circuits having other configurations including the current programming method.

In each of the above-described embodiments, the example in which the organic EL element OLED is used as the electro-optical element has been described. However, the present invention is not limited to this, and an electro-optical element (inorganic LED display device, field emission display device, etc.) whose luminance is set according to the drive current, or transmittance according to the drive current. -Widely applicable to electro-optical devices (electrochromic display devices, electrophoretic display devices, etc.) exhibiting reflectivity.

Furthermore, the electro-optical device according to each embodiment described above can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. FIG. 14 is an external perspective view of the mobile phone 10 on which the electro-optical device according to each of the above-described embodiments is mounted as an example. The mobile phone 10 includes the above-described display unit 1 together with the earpiece 12 and the mouthpiece 13 in addition to the plurality of operation buttons 11.
When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

Block diagram of electro-optical device Data line drive circuit configuration diagram Pixel circuit diagram according to the first embodiment Operation timing chart according to the first embodiment Operation explanatory diagram according to the first embodiment Pixel circuit diagram according to the second embodiment Operation timing chart according to the second embodiment Pixel circuit diagram according to the third embodiment Operation timing chart according to the third embodiment Pixel circuit diagram according to the fourth embodiment Operation timing chart according to the fourth embodiment Pixel circuit diagram according to the fifth embodiment Operation timing chart according to the fifth embodiment External perspective view of a mobile phone equipped with an electro-optical device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display part 2 Pixel 3 Scan line drive circuit 4 Data line drive circuit 5 Control circuit 20a One drive system 20b The other drive system 40 X shift register 41 Circuit unit 42, 44, 48 Switch group 43 1st latch circuit 45 1st 2 latch circuit 46 DAC
47 pixel row memory 49 difference calculation circuit T1 to T14 transistor C1 to C4 capacitor
OLED organic EL device

Claims (13)

In the pixel circuit,
One drive system that holds the first data supplied from the data line in the first frame and generates a first drive current according to the held data;
The difference data corresponding to the difference between the first data and the gradation data supplied from the data line in the second frame after the first frame and defining the gradation in the second frame The other drive system that holds the second data and generates a second drive current according to the held data;
In the second frame, an electro-optical element that is set to a luminance equivalent to the gradation data by supplying a combined current obtained by combining the first drive current and the second drive current. A pixel circuit. The other drive system is
A first capacitor for holding the second data;
The gate of the first capacitor is connected to the first capacitor, and a second forward drive current that is at least part of the second drive current is generated according to data held in the first capacitor. A first drive element that
A second capacitor for holding the second data;
The second capacitor has its gate connected to the second capacitor, becomes at least part of the second drive current according to data held in the second capacitor, and is driven by the second forward drive. The pixel circuit according to claim 1 , further comprising: a second drive element that generates a second reverse drive current opposite to the current. Said first data includes a gray scale data defining the gradation in the first frame, a differential data corresponding to the difference between the difference data before the third frame of the first frame The pixel circuit according to claim 1 or 2 , characterized in that: The one drive system is
A third capacitor for holding the first data;
A self-gate is connected to the third capacitor, and a first forward drive current that is at least a part of the first drive current is generated according to data held in the third capacitor A third drive element that
A fourth capacitor for holding the first data;
The gate of the first capacitor is connected to the fourth capacitor, becomes at least part of the first drive current according to the data held in the fourth capacitor, and the first forward drive. 4. The pixel circuit according to claim 3 , further comprising a fourth drive element that generates a first reverse drive current in a direction opposite to the current. 3. The pixel circuit according to claim 1, wherein the first data is gradation data defining a gradation in the first frame. 4. The one drive system is
A third capacitor for holding the first data;
The third capacitor has a gate connected to the third capacitor, and a third driving element that generates the first driving current in accordance with data held in the third capacitor. The pixel circuit according to claim 5 . A first switching element that selectively supplies the first data of the voltage level supplied to the data line to one electrode of a capacitor included in the one drive system;
Claims, characterized in that it further comprises a selectively supplying the second switching element to the second data voltage level supplied to the data lines to one of the electrodes of the capacitor included in the other drive system Item 7. The pixel circuit according to Item 4 or 6 . First switching is performed by selectively diode-connecting the first driving element and supplying the first data of the current level supplied to the data line to the channel of the driving element included in the one driving system. Elements,
Second switching for selectively diode-connecting the second drive element and supplying the second data of the current level supplied to the data line to the channel of the drive element included in the other drive system The pixel circuit according to claim 4 , further comprising an element. In an electro-optical device,
A plurality of scan lines;
Multiple data lines,
A plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines;
A scanning line driving circuit for selecting the scanning line corresponding to the pixel circuit to which data is to be written by outputting a scanning signal to the scanning line;
A data line driving circuit that cooperates with the scanning line driving circuit and outputs data to the data line corresponding to the pixel circuit to be written;
The electro-optical device, wherein the pixel circuit is the pixel circuit according to claim 1 . An electronic apparatus comprising the electro-optical device according to claim 9 mounted thereon. In the driving method of the pixel circuit,
A first step of holding, in a capacitor included in one drive system, first data supplied from a data line in a first frame;
The capacitor included in the other drive system is supplied from the data line in the second frame after the first frame, and the gradation data defining the gradation in the second frame, and the first frame A second step of holding difference data corresponding to a difference from the data as second data;
In the second frame, a drive element included in the one drive system generates a first drive current according to the first data, and a drive element included in the other drive system is the second drive system. A second drive current corresponding to the data is generated, and a combined current obtained by combining the first drive current and the second drive current is supplied to the electro-optic element, thereby reducing the luminance of the electro-optic element. And a third step of setting corresponding to the gradation data. The first data is difference data corresponding to a difference between gradation data defining a gradation in the first frame and difference data in a third frame before the first frame. 12. The pixel circuit driving method according to claim 11 , wherein the pixel circuit is driven. 12. The pixel circuit driving method according to claim 11 , wherein the first data is gradation data defining a gradation in the first frame.

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