KR100246237B1 - Plasma display panel's driving device - Google Patents

Abstract

The present invention relates to a control block of a plasma display panel that applies a control signal for controlling a scan electrode driving circuit that applies a driving pulse to scan electrodes respectively provided on the entire horizontal display line, and implements gray scale implementation of the entire screen. A first memory unit for holding information on the selection of a horizontal display line to perform a write operation to implement a scan algorithm for selecting a line to which the write and erase operations should be performed among the horizontal display lines of the entire screen; The second memory unit which holds information on the selection of the horizontal display line to perform the erase operation, the first and second memory units, and the address ADDRESS to read the contents of the first and second memory units are read. The first address generator so that the designated address generator and the contents stored at the address designated by the address generator are read and temporarily stored. A temporary memory unit connected to the second memory unit and a data line, a counter synchronized with the start of the sustain period based on the start of every scan pulse, and receiving a input of the temporary memory unit synchronized with the counter to generate a control signal Characterized in that the control signal generator.

Description

Control Block of Plasma Display Panel

The present invention relates to a driving device of a plasma display panel (hereinafter referred to as a PDP), and more particularly, to a control block of a plasma display panel that implements a scan algorithm (SCAN ALGORITHM) necessary for a write operation and an erase operation of a subframe type PDP. It is about.

As the modern society is called the information society, the importance of display increases with the development and spread of information processing system, and its kinds are gradually diversified.

In addition, research and development of various flat displays having a matrix structure have been actively conducted in recent years because they are not suitable for recent trends aimed at screen enlargement and flattening.

The PDP (PLASMA DISPLAY PANEL) has been in the spotlight as the next-generation large-screen flat panel display. The PDP is applied to a wall-mounted television, a home theater display, a computer monitor, and the like due to its large screen and thin thickness.

In order to express gray level in the PDP, the number of discharges per unit time must be adjusted. As a driving method for expressing such a gray level, there are representatively a subfield method and a subframe method.

In the subfield method, a period having the same number of discharges over the entire screen is used as eight subfields (1T, 2T, 4T, 8T, 16T, 32T, 64T, 128T) according to time. The subframe method divides the entire screen into eight different portions in the horizontal display line direction to form subframes, and the boundaries of the divided subframes change with time, and each line has eight different discharge frequency periods in one frame period. It is a way.

The subframe method will be described in more detail as follows.

Assuming that all lines are 255 lines, if the system has 0 to 255 gray levels, Fig. 1 shows the initial screen division of the subframe. As shown, 128 lines with 128 brightness are allocated, 64 lines with 64 brightness, 32 lines with 32 brightness, 16 lines with 16 brightness, 8 lines with 8 brightness, 4 brightness. Assigns 4 lines, 2 brightness is 2 lines, and 1 brightness is 1 line.

After the screen is maintained for one maintenance period, the partition boundary of the screen moves down one line as shown in FIG. 2. At this time, the bottom line moves to the top.

After another maintenance period, the division boundary of the screen moves down one line again. Since 2 brightness occupies 2 lines, 2 brightnesses appear at the bottom and top line.

After another retention period has elapsed, the boundary of the screen division moves down by one line. At this time, all 2 brightnesses go to the top, and 4 brightness comes to the bottom row. If you move by one line after the 255 maintenance period, it becomes the same state as the initial screen division and expresses all the frames.

The subframe method first erases eight lines for writing and writes eight lines in sequence. At this time, the other lines are sustained. That is, it is possible to emit light brighter than the subfield method having the sustain period of about 70% at the same sustain frequency with the ratio of the sustain period being over 99%.

As the boundary of the screen division moves as described above, the current state must be erased from the previously discharged effect, so the previous state must be erased and the write operation is performed after the erase.

For the write / erase operation, a scan algorithm for determining a line to perform a write operation or an erase operation among horizontal display lines is used. Conventionally, since the scan algorithm is implemented in a control block, the size of the control block is increased and the control is performed. There was a problem that required a lot of lines.

On the other hand, the scan algorithm is controlled using an 40-pin output IC (INTERGRATED CIRCUIT), the scan line is 128,192,224,240,248,252,254,255 first, followed by 129,193,225,241,249,253,255,256. In the case of the selective erase operation, eight lines to be scanned are simultaneously written before scanning each line, and then each line is erased eight times in sequence.

In the case of a screen composed of 480 lines, 12 ICs of the 40-pin are used, and in the first scan, the selection lines of the IC and IC are (3,8) (4,32) (5,24) (5,40) (6,8) (6,12) (6,14) (6,15) and the second scan is (3,9) (4,33) (5,25) (5,41) (6,9) (6,13) (6,15) (6,16)... The scan continues in the order of.

However, in order to implement the driving circuit in the above-described order, 12 control blocks for determining the control line according to each IC are required as many as the number of ICs, and such a control has a problem of becoming very complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and saves data used for write / erase operations in a ROM mounted inside a control block, thereby simplifying a driving circuit and reducing the control line of the plasma display panel. The purpose is to provide a drive.

1 illustrates initial screen division of a subframe in a subframe method.

FIG. 2 illustrates division of a subframe after one maintenance period has elapsed from FIG.

3 is a simplified block diagram of a control block according to the present invention;

4 is a block diagram of a driving IC receiving a signal from a control block according to the present invention;

5 is a waveform diagram showing waveforms applied to a driving IC by operation of a control block;

<Description of the symbols for the main parts of the drawings>

300: control block 310: write operation ROM (first ROM)

311: erase operation ROM (second ROM) 312: address generator

313: data buffer 314: counter

315: control signal generator

The present invention for achieving the above object comprises a control block of the plasma display panel for applying a control signal for controlling the scan electrode driving circuit for applying a driving pulse to the scan electrodes provided on the entire horizontal display line, It holds information about the selection of the horizontal display line to perform the write operation in order to implement a scan algorithm for selecting the line on which the write operation and the erase operation should be performed among the horizontal display lines of the full screen to implement the gray scale of the entire screen. Protruding a first memory portion, a second memory portion holding information on selection of a horizontal display line to perform the erase operation, the first and second memory portions, and contents of the first and second memory portions An address generator for specifying an address (ADDRESS) and contents stored at an address designated by the address generator are read and temporarily A temporary memory part connected to the first and second memory parts by a data line, a counter synchronized with the start of the sustain period on the basis of the start of every scan pulse, and an input of the temporary memory part synchronized with the counter. And a control signal generator for generating a control signal.

In addition, according to an embodiment of the present invention, the first memory unit and the second memory unit are configured as ROM, and the upper four bits of the first and second memory units include information on the selection of the scan electrode driving circuit. The lower six bits store information for selecting one of the horizontal display lines connected to the output terminal of the scan electrode driving circuit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a simplified block diagram of a control block according to the present invention. Referring to this, the control block 300 of the plasma display panel applying the control signal for controlling the scan electrode driving IC applying the driving pulse to the scan electrodes provided on the entire horizontal display lines is the target of the write operation. A first ROM (310) holding information on the selection of the horizontal display line, a second ROM (311) holding information on the selection of the horizontal display line to be erased, and the first ROM (310). And an address generator 312 that specifies an address of the ROM to read the contents of the second ROMs 310 and 311, and contents stored at an address designated by the address generator to be read out and temporarily stored. A data buffer 313 connected to the ROM and a data line, a counter 314 synchronized with the start of the sustain period based on the start of every scan pulse, and a data synchronized with the counter 314 It receives an input of the buffer 313 consists of a control signal generating section 315 that generates a control signal.

The operation of the control block 300 of the plasma display panel configured as described above is as follows.

If the address generator 312 provided inside the control block 300 for the write operation designates a specific address of the first ROM 310 in which the ROM data related to the write operation is stored, the read ROM data is stored in a data buffer ( 313).

The data stored in the data buffer 313 is synchronized with the counter 314 which is synchronized with the start of the sustain period based on the start point of every scan pulse. Initially, the H signal is simultaneously applied to the eight lines for the simultaneous write operation of eight lines. Is authorized.

For the erase operation, when the address generator 312 provided in the control block 300 designates a specific address of the second ROM 311 in which the ROM data related to the erase operation is stored, the read ROM data is stored in a data buffer ( 313).

The data stored in the data buffer 313 is synchronized with the counter 314 which is synchronized with the start of the sustain period based on the start point of every scan pulse. Initially, the H signal is simultaneously applied to the eight lines for the simultaneous erase operation of eight lines. Is authorized.

4 is a block diagram of a driving IC receiving a signal from a control block according to the present invention. Referring to this, the data is loaded according to the clock before the erase operation in accordance with each scan sequence, and the data is strobe in the strobe H and the output is possible in each erase operation section (OE: OUTPUT ENABLE). Make it state. In this case, the upper 4 bits of the first ROM store information about the selection of the driving IC, and the lower 6 bits store information about the selection of the horizontal display line connected to the driving IC indicated by the upper 4 bits. That is, if the ROM data is 0011 001000, the driver IC 3 and line 8 are indicated. In the control signal generator, the above data is generated in every sustain period in synchronization with a counter and applied to the driving IC.

5 is a waveform diagram showing waveforms applied to a driving IC by the operation of the control block.

According to the present invention, by simplifying the control line of the driving circuit, the control block can be simplified and downsized, so that the final target ASIC (APPLICATION SPECIFIC INTERGRATED CIRCUIT) can be realized, and the cost of implementing the control block can be reduced. .

Claims (3)

In the control block of the plasma display panel for applying a control signal for controlling the scan electrode driving circuit for applying a driving pulse to the scan electrodes provided on the entire horizontal display line, the horizontal of the entire screen to implement the gray scale of the entire screen A first memory unit which holds information on the selection of a horizontal display line on which to perform a write operation to implement a scan algorithm for selecting a line on which the write and erase operations should be performed among display lines, and performing the erase operation A second memory section holding information relating to selection of a horizontal display line to be made, an address generating section specifying an address ADDRESS to protrude contents of the first and second memory sections, and the first and second memory sections; And the first and second memory units to read and temporarily store contents stored at an address designated by the address generator. A temporary memory unit connected to the data line, a counter synchronized with the start of the sustain period based on the start of every scan pulse, and a control signal generator for synchronizing the counter with the input of the temporary memory unit to generate a control signal Control block of the plasma display panel, characterized in that. The method of claim 1, The control block of the plasma display panel, characterized in that the first memory unit and the second memory unit is composed of a ROM. The method of claim 1, Information about the selection of the scan electrode driver circuit is stored in the upper four bits of the first and second memory units, and the lower six bits are information for selecting one of the horizontal display lines connected to the output terminal of the scan electrode driver circuit. And a control block of the plasma display panel.

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