GB2102178A - Plasma display panel control - Google Patents

Abstract

Complex waveforms used to control a plasma matrix panel are formed as sequences of common elemental waveform modules stored in a ROM. These modules are combined in various orders into strings capable of independently performing various functions on the plasma panel, including a wide range of brightness control. Large scale parallel addressing is accomplished by forming a string of several sustain modules, followed by a write or erase module. The use of 512 cell parallel addressing enables border electrodes to discharge only once during each extended cycle, thus lowering the intensity of light emitted from the borders by at least a factor of five. An erase before write technique is described which allows an erase operation to be inserted into a write function without extending the length of the write function, thus doubling the maximum data rate of the plasma panel display system. <IMAGE>

Description

SPECIFICATION Plasma display panel control The invention concerns plasma display panels.

Plasma display panels are presently in commercial use as digitally addressable information display devices. The panel itself typically comprises of two glass plates with a gas mixture sealed between them. A plurality of Xaxis electrodes extend in a mutually parallel array on an interior substrate of one plate, and a plurality of Y-axis electrodes extend in a mutually parallel array on the interior of the other plate. The X-axis electrodes are at 900 angle to the Y-axis electrodes, thereby forming a plurality of intersections between the X-axis and Y-axis electrodes. A typical 'comnier6ially' available AC plasma panel has 512 X-axis electrodes and 512 Y-axis electrodes, yielding 262,144 intersections, or cells.

When a voltage of between 1 80 to 200 volts is applied across an X-axis electrode and a Y-axis electrode, a discharge in the gas occurs at the cell formed by the electrodes, causing a pulse of light to be emitted at this point. Simultaneously, a charge is collected on the cell wall, which results in the cell being an "on" cell. Once such a discharge has been produced and the cell is turned "on", the collected wall charge acts to continue the discharging when a lesser AC sustain voltage is applied between the electrodes.

In an "on" cell, the gas will discharge and the cell will emit a pulse of light at each transition of the applied AC sustain waveform. The sustain voltage, however, is insufficient to initiate a discharge at an X-Y intersection. This phenomenon is known as inherent memory, and was originally disclosed by Baker et al, in U.S.

Patent 3 499 167, and by Bitzer et al, in U.S.

Patent 3,959,190. By precisely timing, shaping, and phasing multiple alternating voltage waveforms supplied to X and Y axis electrodes, the generation, sustaining and erasure of light emitting gas discharges at selected locations on the plasma display panel can be controlled.

Four functions are used to control the operation of an AC plasma panel, the write function, the erase function, the sustain function, and the bulk-erase function. The write function causes a selected cell on the panel to change from the "off", or non-light emitting state, to the "on" or light emitting state. The sustain function maintains the state of all cells on the panel, i.e.

causes "on" cells to remain on, and "off" cells to remain off. The sustain function also causes the "on" cells to emit light. The erase function causes a selected cell to be changed from the "on" state to the "off" stage. The bulk-erase function causes all "on" cells in the panel simultaneously to be changed to the "off" state.

Operation of the write, erase, sustain, and bulkerase functions is generally controlled by four logic signals; the X-sustain signal XS, the Ysustain signal YS, the X-address pulse XAP, and the Y-address pulse YAP. These signals, generally supplied by a waveform ROM (Read Only Memory), are digital pulse trains typically recurring at a freqeuncy of 50kHz. The logic signals are supplied to the sustain and drive circuits, and cause the circuits to execute the four control functions on the panel. Since the typical operational frequency of the plasma display system is 50kHz, the complex waveform for each of the four control functions is executed in a 20 microsecond period. It has been found necessary, in the prior art, to have all four functions of an equal length since one ROM is used to store them, and addressing is less complex for the constant length.

This 20 microsecond period is a compromise, since the amount of time needed for the various operations varies. For example, the amount of time needed for a sustain cycle is about 1 5 microseconds, for a write cycle about 23 microseconds, for an erase cycle about 1 6 microseconds, and for a bulk-erase cycle only about 8 microseconds. The typical 20 microsecond period is, therefore, a compromise for the four control functions. Increasing the period of each of the four functions to the 23 microseconds taken by the write function would increase the stability of the plasma display panel after a write function, but it would cause the system to be approximately 15% slower due to the longer period of time required to perform each function.The 20 microsecond period decreases the stability of the plasma display panel after a write function somewhat, an acceptable compromise.

A more significant problem is the fact that prior art systems bear the constraint of having a fixed time base, this fixed time base allowing only one fixed cycle length of 20 microseconds. If the lengths of the four control functions could differ, each of the functions could be done in the minimal time required, thus yielding both a higher data rate and a better write function.

It is also desirable to be able to add a new function which has a length greater than the fixed cycle length of 20 microseconds, such as a distributed conditioning pulse as described in our concurrently filed, copending U.K. Patent Application No. 82 1 7208. The distributed conditioning operation causes all of the cells in a plasma panel to be discharged periodically, eliminating the need for border sustainers. Since the distributed conditioning function takes more than 20 microseconds to perform, two 20 microsecond periods must be chained together to give a compound mode of length 40 microseconds. In order to perform the operation, extra logic for the ROM address lines is necessary to execute the two 20 microsecond component periods sequentially.It may be desirable to have other functions which also take a greater length than the standard 20 microsecond period.

Therefore, it may be seen that the use of a fixed time base having a 20 microsecond period does not allow sufficient flexibility to operate sophisticated plasma display systems.

One possible solution is to increase the length of the period. This solution presents several problems of its own. First, the maximum update rate would be reduced by an amount directly proportional to the increase in the period of the cycle. Also, if only one sustain cycle is run in the increased period, the brightness of the display would be reduced, since only two pulses of light would be emitted from the display in the increased period.

Another major problem caused by the fixed 20 microsecond time base is that large scale parallel addressing is not possible. It is highly desirable to address an entire line, comprised of the 512 cells along an X-electrode, simultaneously. However, the time required to load the data necessary to address 51 2 cells is at least 71 microseconds to prepare the drive circuitry for a write or erase operation. Five complete sustain operations can be done in a period of 75 microseconds, providing sufficient time for loading data. A write function, done properly, takes 23 microseconds, so it may be seen that a period of approximately 98 microseconds or more is required in order to parallel address 512 cells. If a fixed period of 100 microseconds is adopted, 512 cell parallel addressing would be possible, but at a substantial cost.Since the sustain and bulkerase cycles would have the same period, to prevent complex aaddressing circuitry from being required, there would be a substantial delay in addressing, i.e. performing write or erase operations, if a sustain function was being executed at the time.

A major consideration in the design of plasma display panel systems is the amount of ROM memory storage space required, since larger amounts of memory increase both the cost and complexity of the system. The basic system described above, with only write, erase, sustain, and bulk-erase functions, at a fixed 20 microsecond period, needs only about 1 K of memory.

If another function is to be added to the system, the amount of required memory is doubled. For a complex function, such as distributed conditioning, to be added to the system, the memory space in the ROM must be quadrupled, and external control logic must be added to access these new locations in the ROM.

If 512 cell parallel addressing is desired, the minimum period for a cycle that would allow 512 cell parallel addressing is about 100 microseconds. Each of the pulse trains stored in the ROM would have to be 100 microseconds long, 5 times the length of the basic system.

Therefore, in order to add a 51 2 cell parallel addressing feature to the basic plasma panel system, the memory required would be 5 times the minimum memory of 1 K, since the address groups are 5 times as long as the previous 20 microseconds, and thus 5K of memory would be required. If it is desired to parallel address 512 cell locations, and to also have a distributed conditioning feature, the memory capability must be further expanded.

Another desirable feature in a plasma panel is brightness control. Currently, the best existing brightness control circuit for an AC plasma panel is a constant data rate brightness control. This method uses a waveform ROM which stores two groups of control signals. The first group performs sustain, write, erase, and bulk-erase functions in a normal maner, emitting two pulses of light per 20 microseconds cycle. The second group of control signals performs the same functions, but with the emission of substantially no light. By mixing the functions from the two groups and varying the ratio of the two groups, a broad range of variable brightness in the operation of the plasma panel is achieved.

Although the constant data rate brightness control is a great improvement over the prior art, it has several problems. The greatest of these problems occurs when the system is alternatively generating brightness control write and brightness control erase functions. During this operation, light will be generated at the rate of 1 pulse per cycle. Therefore, when write and erase functions are being alternately performed, the minimum brightness achievable by the system is 50% of maximum brightness.

This constraint presents a problem, particularly when it is desired to operate the system at the minimum brightness level, 12.5% of full brightness. Sustain pulses at this minimum intensity will provide the correct panel intensity, bit if alternate write and erase operations are performed, there will be light flashes four times brighter than this minimum intensity.

A second problem inherent in the constant data rate brightness control system is that the maximum light the system is capable of producing occurs when the system emits two pulses of light for every 20 microsecond period. The use of plasma planels in areas having a high level of ambient light makes it desirable to increase the number of light emissions per unit of time, to obtain a somewhat higher level of maximum brightness.

As mentioned above, it is also desirable to perform 51 2 cell parallel addressing, which would allow an entire line on a typical 512x512 plasma panel be addressed simultaneously. Such parallel addressing is desirable because it increases the data rate of the panel, that is, the maximum rate of writing and erasing the panel, by a factor of 5.3. Since the display characteristics of the plasma panel generally improve as the update rate is increased, particularly in cases where the panel is being used as a video display, a major objective in plasma display panel system design is to increase the update rate as much as possible.

Another problem in the design of brightness control systems for plasma panels is the high intensity discharge of the plasma panel borders.

In order to perform write operations on a plasma panel, it is necessary that there be a sufficient number of free particles present in the gas mixture to initiate an avalanche process which causes a write operate to occur. The technique generally used to supply a sufficient quantity of free particles for a write operation utilizes border electrodes around the perimeter of the addressable display area of the plasma panel, which are driven by separate electronic circuits at a sufficiently high voltage level to cause very intense discharges to occur in the border areas.

These discharges flood the viewing area of the plasma panel with a sufficient number of free particles to enable the panel to be written with a high degree of accuracy. In past systems, the intensity of light emitted by the border electrodes has not be controllable. In other words, while the viewing area of the panel may be driven so that the brightness level of the display is fairly low, the borders continue to operate at full intensity, and are highly visible to plasma panel observers. It is therefore desirable to reduce the intensity of light generated by these border electrodes.

The addition of brightness control expands the amount of ROM memory storage space required by a factor equal to the number of brightness levels desired, typically 8. If brightness control is desired in a system with more than the basic four control functions, and 51 2 cell parallel addressing is also desired, the amount of memory required becomes prohibitively large, as demonstrated by the following example. For a system with 8 different control functions and 8 brightness levels, with a 1 20 microsecond period (required for 8 level brightness control), the amount of memory required is 384 addressx8 modesx8 brightness levelsx 5 outputs (required for distributed conditioning)=1 20K. This size of memory is simply too expensive to be considered.Thus, if it is desired to have constant data rate brightness control in combination with sophisticated operating modes, an alternative system is required.

The present invention alleviates the above problems by forming the required waveforms as sequences of a small number of elemental waveform parts, called modules. Thus, the system generates short, elemental modules, and uses these modules as building blocks, stringing them together in different orders to provide a variety of waveforms to perform the required functions.

The modules used include a positive discharge module, a negative discharge module, a blank sustain module, a write module, an erase module, a bulk-erase module, a short sustain equiiization module, a long sustain equilization module and a distributed conditioning module. In order to form a complete waveform which performs a function on the plasma panel, a number of modules are assembled into the complete function.

For example, to generate a sustain waveform, two modules are used. The first module is a negative discharge module, and the seocnd module is a positive discharge module. In this way, the sustain function is assembled from two smaller modules so that the sustain operation will be performed in a minimum time.

A write function is generated by a positive discharge module and a write module. The positive discharge module is the same module used as the second module in the sustain function above. In addition, if the write function is immediately preceded by a sustain function, the initial positive discharge module, used in the write function, is not necessary. An erase function is generated by an erase module and a positive discharge module. A bulk-erase module is used to provide the complete bulk-erase function. Other functions, such as distributed conditioning brightness control, may be performed by the addition of a single extra module to perform each additional function.

512 cell parallel addressing can be done by forming a string of sustain pulses, for a period of time sufficient to enable addressing information to be loaded into the driver chips, and then by causing a write or erase module to be generated.

Since it takes approximately 71 microseconds to load the data into the driver chips, five sustain modules of 1 5 microsecond duration would provide sufficient time for the information to be loaded. In order to complete the function, a write or erase module follows the sustain pulses, performing the write or erase function. The erase module must be followed by a sustain equilization module and then a positive discharge module, since each string of pulses must end with a positive charge pulse.

Because each function occurs in the minimum cycle time required, the addressing rate of the system is maximized. This permits 512 cell parallel addressing while, actually increasing the panel data update rate.

Modular waveforms are generated by using two ROMs that are cascaded. These ROMs include a module generator ROM, which operates at a fast access time, and a string generator ROM, which operates at a slow access time. The module generator ROM is capable of generating each of the modules described above. The string generator ROM indicates to the module generator ROM which modules it is to generate, and will cause the module generator ROM to generate a desired group of modules sequentially, forming a complete function.

The string of pulses which performs either a write or an erase operation can be assembled using blank sustain modules, so that the number of discharges causing the emission of light can be controlled. The use of strings that are 100 microseconds or longer enables alternating write and erase operations to be executed while operating the system at a low level of brightness.

In this way, the problem of light flashes at 50% intensity are eliminated by the present invention.

By generating basic components of the waveform in modules, each individual component operation is executed in the minimum time required. This not only has the effect of improving the data rate of the system, but also provides an optimum write function which was not possible in the system operating with a fixed 20 microsecond period. For example, only two modules are used to perform the sustain function and thus although a sustain operation can be carried out in 1 5 microseconds, it is generally executed in 16.67 microseconds (60 KHz). Since this permits the sustain operations to be performed at a higher frequency than in a system having a fixed 20 microsecond period, the maximum brightness of the system of the present invention is greater than the maximum brightness of a 20 microsecond time base system.Since the present system is capabe of maximum intensity approximately 20% higher than previous systems, the overall range of brightness control is greater.

The present system is also capable of a new type of operation-an erase before write operation. In an erase before write operation, an entire line is erased and then re-written in one cycle. This technique is made possible by the fact that, with 512 cell parallel addressing, a cycle is 100 microseconds or longer. The erase before write function enables a system that is continuously updating the information display, such as a video display terminal, to further double its update rate. Therefore, the present system can increase the update rate of the plasma panel display by a factor of 10.6, while enabling the brightness of the display to be precisely controlled over a greater overall range of brightness.

The memory required by a complex system not using modular waveform generation techniques would be prohibitively large. In order to have 8 levels of brightness control, 8 different control functions, 5 different outputs, and 512 cell parallel addressing, 120K of memory would be required. The module generator ROM of the present invention requires 2.5K of memory and the string generator ROM requires 10K of memory, for a total requirement of 12.5K memory storage space.

In addition, the system of the present invention does not require complex external control logic, but requires only two counters and two latches in addition to the two ROMs.

The amount of memory utilized has been minimized, thus keeping the overall cost of the system as low as possible. In addition, the system of the present invention allows considerable flexibility, and is easily expandable for additional operational modes.

The invention is described further hereinafter, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a diagram of the electrode configuration of a known AC plasma panel showing border sustainer electrodes and display area electrodes for a border sustainer type system; Figure 1 a is a waveform diagram showing the outputs of the drive circuitry, the Y-border sustainer output, the applied cell voltage Y-X and the applied border cell voltage YBDRX for a border sustainer-type system; Figure 1 b is a block diagram of a conventional system with X-Y sustain and driver circuitry, and X-Y border sustainer circuitry controlling the AC plasma panel;; Figure 1 c is a block diagram of a plasma panel system with a driver circuitry and distributed conditioning circuitry replacing the X-Y border sustainer circuitry of Figure 1 b; Figure id is a schematic diagram of the distributed conditioning circuit shown in Figure lc; Figure 2 is a block diagram of the logic circuitry for providing the logic signal outputs which control the sustainer and driver circuitry of the system in Figure 1 c; Figure 2a is a charge showing the ROM addresses and the functions performed for a given mode control input for the logic circuitry of Figure 2;; Figure 3 shows the applied cell voltage Y-X, the Y-driver voltage, the X-driver voltage, and the logic signal outputs supplied by the present invention for a positive discharge module, a negative discharge module, and a blank sustain module; Figure 4 shows the applied cell voltage Y-X, the Ydriver voltage, the X-driver voltage, and the logic signal outputs supplied by the present invention for a write module, an erase module, and a bulk-erase module;; Figure 5 shows the applied cell voltage Y-X, the Y-driver voltage, the X-driver voltage, and the logic signal outputs supplied by the present invention for a short sustain equilization module, a long sustain equilization module, a distributed conditioning module, and the blank sustain module which must follow the distributed conditioning module; Figure 6 shows the assembled string for 512 cell parallel addressing write and erase functions, for the sustain function, and for the distributed conditioning function, the assembled strings being composed of the modules shown in Figures 3-5;; Figure 7 is a schematic diagram of a digital memory device storing 1 6 modules, each module having 32 addressable locations, for generating logic signal outputs causing one of the basic module operations shown in Figures 3-5 to be executed on a plasma panel; Figure 8 is a schematic diagram of a digital memory device having 64 address groups, each group having 32 addressable locations, for causing a selected group of modules from the device in Figure 7 to be sequentially accessed; Figure 9 is a block diagram schematic of the components of the present invention used to provide the logic signal outputs shown in Figures 3-5; ; Figure 10 shows the applied cell voltage Y-X for 512 cell parallel write functions having 8 different levels of brightness, the brightness level input causing each of these levels of brightness, and the effective frequency of each of the waveform strings; Figure 1 0a Is a block diagram of the module generator of Figure 9 modified to produce XBS and YBS logic signal; Figure 1 Ob shows the operation of the border sustainers in response to the logic signals generated by the apparatus of Figure 1 0a;; Figure 11 shows the applied cell voltage Y-X, the Y-driver voltage, the X-driver voltage, and the logic signal outputs generated by the modulator waveform generator for a line erase module, and the positive discharge module and short sustain equalization modules preceding and following the write-erase module; and Figure 12 shows the applied cell voltage Y--X for a selected cell arid for a non-selected cell, for a 512 cell parallel erase before write function.

Figure 1 depicts a prior art plasma panel 70 and sone of the electrodes contained in that panel. The X-electrodes 76, 72 are formed on an interior substrate of a first glass plate, while the Y-electrodes 78, 74 are formed on a second glass plate. These plates are spaced from one another, and a gas is sealed between them. The X-border electrodes 76 and the Y-border electrodes 78 are located around the perimeter of the plasma panel.

The electrodes in the visual display area 75 of the plasma panel 70 are X-electrodes 72 and Yelectrodes 74. The electrodes 72, 74 depicted in Figure 1 represent only a portion of the total number of electrodes, since there are 512 Xelectrodes and 51 2 Y-electrodes in the visual display area 75.

Free particles used to initiate the discharges in the visual display area 75 are generated by discharges at intersections between the Xelectrodes 72 and Y-border electrodes 78, and the intersections between the Y-electrodes 74 and X-border electrodes 76. The voltage levels which are supplied to these electrodes during a sustain operation are shown in Figure 1 a. The voltage supplied to the X-electrodes 72 is Xdriver, the voltage supplied to the Y-electròdes 74 is Y-driver, the voltage supplied to the Y-border electrodes 78 is YBDR The voltage levels supplied to the X-border electrodes 76 is not shown.

The voltage supplied to a single display area cetl, or intersection between an X-electrode 72 and a Y-electrode 74 in the viewing area 75, is the applied cell voltage Y-X. The points in the applied cell voltage Y-X where light pulses will be emitted from "on" cells are indicated by a and b in Figure 1 a.

The voltage applied to border cells, or intersections between the X-electrodes 72 and the Y-border electrodes 78, is the applied border voltage YBDRX driver. The voltage applied to the Y-border electrodes 78, VBDR is of a greater magnitude than the voltage applied to Yelectrodes 74 in the viewing area 75. The magnitude of this voltage, VBDR is typically 120 to 1 50 volts, which is a voltage level high enough to ensure that discharges will occur in the border areas, supplying free particles at each discharge to the rest of the panel.

The applied border voltage Y,,,--X-driver, will therefore vary between VBDR and -V002, a 220 to 250 volt swing. This large voltage swing will cause very intense discharges to occur in the border cells at the point indicated on the applied border voltage VBDRX-driver waveform as c, and a second discharge will take place at d. These discharges generate the particles necessary to ensure the reliable write operations occur in the visual display area 75 of the plasma panel 70.

The X-electrodes 72 and the Y-electrodes 74 making up the visual display area 75 are driven by sustainer and driver circuits common in the art, as referenced below. These sustainer and driver circuits are controlled by the logic signals XS, YS, XAP, and YAP. These logic signals may be used to cause write, erase, sustain, and bulk-erase functions to be executed on the panel 70.

The plasma panel 70, as shown in Figure 1 b, is driven by an X-axis driver circuit 250 and a Y-axis driver circuit 1 50. The circuitry of Figure 1 b is described in detail in our European Patent Application No. 81303065.7 entitled "Plasma Display Panel Drive" and published on the 20th of January, 1982, under Publication No. 0044182, to which reference is hereby directed for a detailed description of the driver circuits. A general description is provided below, to aid in the understanding of the present invention.

A pair of sustain circuits 210 and 110 are used to provide the sustain signal to the driver circuits 250 and 150, respectively. Float circuits 211 and 111 are used to supply floating supply levels of Vcca, the low voltage used to power the logic circuitry, and Vac2, the high voltage used to drive the panel, to the circuits 250 and 150, respectively. The X-axis sustain circuit 210 is controlled by an X-sustain signal XS, and the Yaxis sustain circuit is controlled by a Y-sustain signal YS.The addressing of individual cells of the panel 70, to accomplish selective writing and erasing of these cells, is controlled by an Xaddress pulse XAP and a Y-address pulse YAP, supplied from a waveform ROM (Read Only Memory, shown in Figure 2) through a pair of level shift circuits 240 and 140, which are required, since the driver circuits 250 and 1 50 operate on floating grounds. The X-address information and Y-address information is supplied to the driver circuits 250 and 1 50 through a pair of level shift circuits 93 and 91, respectively, and identifies which cells on the plasma panel 70 are to receive the X and Y address pulses.

Figure 1 c shows an alternate system, in which a distributed conditioning signal DCON is supplied to the X-axis driver circuit 250 via a level shift circuit 200. The distributed conditioning operation functions to replace the conventional X-Y border sustainer and associated logic circuitry is shown in Figure 1 b, and is described below.

The distributed conditioning circuit 52 is shown in the schematic diagram of Figure 1 d.

This circuit supplies the two most significant address bits 50a and 50b to the waveform ROM 40 (Figure 2). The waveform ROM 40 stores the bulk erase, erase, write, and sustain functions in a first group of memory locations, as shown in Figure 2a which are accessed by the system counter/sequencer 34 (Fig. 2) when the bits 50a and 50b are both 0. However, since the most significant address bits for the ROM 40 are provided by lines 50, the control of bits 50a, 50b will cause the sequencer 34 to address different blocks of memory, shown as the distributed conditioning blocks of Figure 2a.Furthermore, the function logic 11 (Fig. 2) controls the next two most significant bits 1 2a and 1 2b of the ROM address, and thus determines which address group (Figure 2a) is accessed. During normal operation of the plasma panel, bits 50a and 50b will be at a logic signal of 00. In order to perform the distributed conditioning function, the address bits 50a and 50b must go to 10 for 20 microseconds, and then to 11 for an additional 20 microseconds, and finally return to 00, as described above.

Since bits 50a and 50b are to be controlled by the same clock controlling the waveform ROM 40, bits 50a and 50b change logic levels only at the time the waveform ROM 40 completes sequencing through an address group. The distributed conditioning circuity 52 has two main components: a monostable multivibrator 53 and a counter 54. The multivibrator 53 is typically an SN 54121, and basically acts as a time delay.

When the input to the multivibrator 53 goes from a logic level of 1 to a logic level of 0, the multivibrator 53 will begin timing. When the multivibrator 53 times out, it will output a low pulse, its output normally being high.

The counter 54 is typically a 54LS1 61, and will supply the address bits 50a and 50b to the waveform ROM 40 (Figure 2). Before the multivibrator 53 times out and outputs a low level pulse, the address bits 50a and 50b are at 00 level. When the low level pulse of the multivibrator 53 is output, it will cause the counter 54 to output as bits 50a and 50b a 10 signal, as soon as the clock input 57 indicates the waveform ROM 40 has completed an address group. When bits 50a and 50b switch to 10, one of the address groups 9 through 12 (Figure 2a) will be accessed.

When bit 50a switches 1, the 1 logic level is supplied to the enable P input of the counter 54, causing the counter to begin sequencing at this point, on the same time base as the waveform ROM. The counter 54 therefore will not change states for 20 microseconds, while the waveform ROM 40 sequences through one of the address groups 9 through 12. At this point, the clock input 57 will increment the counter chip 54 and bits 50a and 50b will switch to 11, causing one of the address groups 13 through 1 6 (Figure 2a) in waveform ROM 40 to be accessed. After 20 microseconds, the counter 54 will increment again, causing bits 50a and 50b to switch to 00, and causing one of ROM address groups 1 through 4 (Figure 2a) to again be accessed. When bit 50a goes to 0, it will supply the 0 logic level to the enable P lead of the counter 54, causing it to stop incrementing.Bit 50a is also input to the multivibrator 53, and when it switches to 0, it will cause the multivibrator 52 to again begin timing.

The time delay provided by the multivibrator 53 is 8.3 milliseconds so that the entire sequence will be repeated at a rate of 120Hz.

The waveform ROM 40 and its addressing circuitry are shown in Figure 2. A distributed conditioning input 50 and a mode control input 12 determine which of 1 6 address groups in the waveform ROM 40 will be accessed. The distributed conditioning input 50 is generated by the distributed conditioning circuit 52 and comprises two address bits, 50a and 50b, as described above, supplied to the waveform ROM 40. These two bits form the most significant address bits for the ROM 40, and determine whether the address groups which is to be accessed is in address groups 1 to 4, 5 to 8, 9 to 12, or 13 to 16, as shown by the chart in Figure 2a. The two next most significant address bits for the waveform ROM 40 are bits 1 2a and 1 2b, which are generated by a function logic circuit 11.

These bits 1 2a and 1 2b determine which of the four basic functions (bulk-erase, erase, write, oF sustain) will be implemented, as shown in Figure 2a.

It may be seen from the chart in Figure 2a that each of the address groups have 64 addressable data words, as shown in the column marked "ROM Address." Sequencing through these 64 addresses is controlled by timing information 38, supplied by a system counter/sequencer 34, and a system clock 32, shown in Figure 2. The chart in Figure 2a shows, under the heading "Function", the operations that will be performed for each of the 1 6 address groups.

The waveform ROM 40 supplies the 5 logic signal outputs controlling the sustainer and driver circuitry of Figure 1 c: an X-sustain signal XS, a Ysustain signal YS, an inverse X-address pulse XAP', an inverse Y-address pulse YAP', and an inverse distributed conditioning pulse DCON'. The latter three pulses are in inverse form since the level shifters used in the circuitry of Figure ic will invert them. The level shifters of Figure Ic, 240, 140, and 200, are well-known, and may comprise, for example, optical isolators or transformers The single ROM system described above is designed to operate at a fixed frequency, typically 50kHz. This type of system has all of the drawbacks and disadvantages described above.

The present invention uses a modular waveform generation circuit in place of the circuitry of Figure 2. The invention separates each of the waveforms used to address the plasma panel into modules. By combining these modules in different sequences, any desired waveform may be generated. Each module begins and ends with no discharge activity taking place, and the applied cell voltage Y-X is at the AC zero voltage level at the beginning and end of each module. This requirement enables any module to follow any other module.

The modules used by the present invention to generate waveforms to address the plasma panel, are shown in Figures 3-5. The logic signals shown in these figures (DCON, XS, XAP, YS, and YAP) are supplied to the sustain and driver circuits 110, 210, 150, 250 shown in Figure Ic which, in response, generate the waveforms Xdriver, Y-driver shown in Figures 3-5. These waveforms cooperate to generate, at the plasma panel 70, the applied cell voltage Y-X, which performs the functions indicated.

The first module in Figure 3 is a negative discharge module. The second module is a positive discharge module. A negative discharge module and a positive discharge module are the two components required to perform the sustain function. When a negative discharge module is followed by a positive discharge module, a single sustain cycle is generated. The negative discharge module and the positive discharge module are also used as components of other functions, when combined with other modules.

The third module shown in Figure 3 is the blank sustain module, which is used for brightness control (described in detail below).

The first module in Figure 4 is a write module.

When the write module is preceded by a positive discharge module (Figure 3), a complete write function will be performed. If a sustain function immediately precedes the write function, the positive discharge module is not necessary, since a sustain function ends with a positive discharge module.

The second module in Figure 4 is an erase module, and when followed by a positive discharge module, a complete erase function will be performed. The positive pulse of the positive discharge module is necessary, following the erase module, because each string of modules comprising a function must end with a module producing a positive pulse so that the first pulse of a succeeding sustain function will produce a discharge of light. A positive pulse is produced by positive discharge, write, and distributed conditioning modules.

The final module shown in Figure 4 is the bulkerase module. The module alone will perform the bulk-erase function. Since it is comprised of two very short pulses, which pulses erase the entire display, a succeeding sustain function will not produce a pulse of light in any case. Thus, it is not necessary to follow the bulk-erase module with a positive pulse producing module; therefore, the bulk-erase module is an exception to the requirement of ending a function with a positive pulse producing module.

In Figure 5, the first two modules shown are a short sustain equilization module and a long sustain equilization module. These two modules are characterized by an applied cell voltage Y-X at the AC zero voltage level, and are used for spacing purposes. These spaces are required when it is necessary to have a string of modules in a certain timer period, and are most commonly used for brightness control systems which are capable of addressing 512 cells, as will be described later.

The third module shown in Figure 5 is a distributed conditioning module. The distributed conditioning function eliminates the need for border sustainer circuitry in Figure 1 b by periodically discharging all of the cells in the panel, as discussed above. In order to perform a distributed conditioning operation, the distributed conditioning module must be followed by a blank sustain module, as shown in Figure 5. The distributed conditioning module must be preceded by a positive discharge module, but this positive discharge module may be the last module of the preceding operation.

While only 9 modules have been disclosed, the system of the present invention has the capability of storing 1 6 different modules. When any one of these modules is accessed, the system must output the 5 logic signals (XS, YS, XAP', YAP' and DCON') which will cause the waveform generated by that module to be executed on the plasma display panel. Figure 7 shows, schematically, a module generator ROM 44 storing information to perform 1 6 different modules. Module 1 is shown to have 32 address locations, and the operation performed by module 1 will be executed by stepping through these locations in order, to produce binary bit patterns which define the logic signal outputs. An additional signal generated by each of the modules is the "end of module" signal EOM.This signal is necessary, since different modules require different time periods.

For example, in order to produce a short sustain equilization module, only 7 of these address locations are utilized. However, in order to perform the longer distributed conditioning function, all 32 of the address locations are needed. Since each module will be performed in the minimum amount of time required, the end of module signal EOM, is necessary to indicate that the module is completed. Therefore, the EOM bit for all but the last address location utilized will have a 0 logic level. For the last address location utilized, the EOM bit will be 1, indicating that the operation performed by the module is complete.

Since there are 1 6 different modules, four address bits 28a, 28b, 28c and 28d are required to select one of the 1 6 modules. These address bits 28a, 28b, 28c, and 28d, are provided by a string generator ROM 42, shown schematically in Figure 8. The string generator ROM 42 sequentially addresses groups of modules from the module generator ROM 44 to assemble a string of modules into a complex waveform. The string generator ROM 42 is shown to provide 8 functions, each at 8 brightness levels, requiring a total of 64 address groups. Each of these address groups contains 32 address locations, each identifying a module. Thus, each string may include up to 32 modules.In other words, each of the addressable locations stores address bits 28a, 28b, 28c, and 28dwhich identify 1 module, and cause that module to be executed.

There is an additional logic signal output, the "end of string" signal EOS. When the EOS signal is at a logic level of 1, it indicates that the last module in the string is being generated. For example, if a sustain function is being generated, a negative discharge module and a positive discharge module must be produced. Since there are only two modules in the basic sustain function, addressable location 2 would have a 1 bit for the EOS logic signal.

Referring now to Figure 6, a number of examples will be utilized to describe the use of modules to assemble functional strings. In a first example, a distributed conditioning function, assembled from a distributed condition module (DCON) and a blank sustain module (BS), is shown preceded by a sustain function. The sustain function is assembled from a negative discharge module (ND) and a positive discharge module (PD). Since the last module of the sustain function is a positive discharge module, the distributed conditioning function may follow the sustain function without requiring an additional positive discharge module.

The blank sustain module (BS) following the distributed conditioning module (DCON), and completing the distributed conditioning function, generally is followed by a negative discharge module (ND), as shown in Figure 6, where the negative discharge module (ND) following the distributed conditioning function is the first module of a sustain function. It should be noted, however, that it is only typical, and not mandatory, that a negative discharge module (ND) follows the distributed conditioning function.

A second example provided by Figure 6 is the sustain function. A negative discharge module (ND) will be generated, and at the last point in that module, an "end of module" signal EOM will be generated. As can be seen from Figure 6, each module ends with an EOM signal, which causes the system to access the next module from the ROM 44. In the case of the sustain function being described, this next module is a positive discharge module (PD). When the positive discharge module has been generated, an "end of module" signal EOM and an "end of string" signal EOS are generated. As can be seen from Figure 6, each function ends with an EOS signal, which causes the next function to be accessed from the string ROM 42. By using this technique, the basic functions may be executed in the minimum amount of time required.

In order to perform a 512 cell parallel addressing operation, a period of at least 71 microseconds is required for loading addressing data into the driver circuits. Therefore, if a write or erase function is to be performed, a string of modules will be assembled as shown in the remaining examples of Figure 6. For a period of at least the 71 microseconds required to load the data, sustain functions composed of positive discharge (PD) and negative discharge (ND) modules will be assembled. After a time sufficient to load the data, a write (W) or erase (E) module is accessed. 512 cell parallel write strings are shown in Figure 6 for both maximum and minimum brightness. For maximum brightness, there are 6 complete sustain functions followed by a write module (W) and a long sustain equilization module (LSE).During the time that the sustain functions are being executed, data is being loaded into the driver circuits. Then, near the end of the string, the 512 cell parallel write module (W) is accessed.

For a minimum brightness level string performing the 512 cell write operation, most of the negative discharge (ND) modules and positive discharge (PD) modules are removed, substituting blank sustain (BS), long sustain equilization (LSE), and short sustain equilization (SSE) modules. It can be seen that one complete sustain function will be performed before the write module (W) is accessed. In addition, the cycle shown for minimum brightness is extended to 120 microseconds, rather than the 100 microseconds of the maximum brightness string. Making the string longer with the same number of light emissions, of course, has the effect of further reducing the overall light emitted from the plasma display panel 70.

Figure 6 also shows a 512 cell parallel erase string, for maximum brightness. There are 5 complete sustain functions, followed by a negative discharge module (ND), and the erase module (E). There are then two short sustain equilization modules (SSE), and a positive discharge module (PD) to end the string with a positive pulse. The requirement for this positive pulse was discussed above.

The total time for a write or erase operation is approximately 102 microseconds. In this time period, 51 2 cells may be written. With nonmodule systems, 1 6 cells could be written in a period of 20 microseconds. Therefore, it may be seen that this system performs a write or erase function approximately 6.4 times faster than such systems. Even when the system is operating at the minimum brightness level shown in Figure 6, and the write or erase function takes 1 20 microseconds to be performed, the system of the present invention is approximately 5.3 times faster than non-module systems. Therefore, the overall data rate of the system of the present invention is at least 5.3 times higher than the data rate systems which do not include the present invention.

The actual circuitry used to form the modules and to assemble the strings of modules is shown in Figure 9. This circuit is used in place of the more common waveform ROM 40 shown in Figure 2. There are two main components to the system: a string generator 41, and a module generator 43. The module generator 43 includes, as a component, the module generator ROM 44 shown in Figure 7, and generates the individual modules described above. The string generator 41 includes, as a comparator, the spring generator ROM 42 shown in Figure 8, and assembles the modules in a desired string to perform whatever function is to be executed.

The operation of the module generator 43 is as follows. Module address information 28 (bits 28a-d) is supplied by the string generator 41, and defines which module is to be generated. This information is supplied via a latch 1 5 to the module generator ROM 44 when the previous module has been completed. The module generator ROM 44 will then output logic signals (XS;YS, XAP', YAP', DCON') which will cause the driver and sustainer circuitry (Figure 1) to execute the-desired module. The module generator ROM 44 is clocked through its addressable location by timing information from a counter 35.

When a module has been completed, an end of module signal EOM will be output from the module generator ROM 44 as described above.

This signal is supplied to the counter 35, causing it to reset. The EOM signal is also supplied to the latch 15, causing it to clock an address into the module generator ROM 44 defining the next module to be accessed in the string. Since the counter 35 has been reset, information from the next module will be accessed beginning at the first addressable location in that module.

These modules are assembled into strings by the string generator 41. When a module has been generated and the End of Module signal EOM is supplied by the module generator ROM 44, the EOM signal is used as a clocking pulse for a counter 33. Each time the counter 33 receives this End of Module signal EOM, it will increment and cause the string generator ROM 42 to output address information 28 defining the next module to be executed. If the address information 28 defines the last module in the string, an End of String signal EOS is generated by the string generator ROM 42. This End of String signal EOS causes the counter 33 to reset, and the latch 13 to provide to the string generator ROM 42 an address defining the next string which is to be performed.

This address comprises the two inputs to the system: a brightness control input 12, and a mode control input 1 8. The module generation system shown in Figure 9, to provide 512 cell parallel addressing with brightness control as described above, would require a string generator ROM memory of 1 OK, and a module generator ROM of 2.5K, for a total memory requirement of 12.5K.

The use of a non-modular system with such capability would require 120K of memory. It can be seen that, as more functions are added, and more brightness levels are used, the memory savings will be multipled.

As discussed above, by removing positive discharge modules and negative discharge modules from module strings, and inserting a number of blank sustain modules equal to the total number of positive discharge modules and negative discharge modules removed, the brightness level of the plasma display may be varied (Figure 6).

Figure 10 shows write strings for 8 brightness levels. Each of these strings produces a pulse of light at the leading edge of both the positive and negative discharge modules. As can be seen, the pulse trains vary from an effective sustain cycle frequency of 59 kHz down to an effective sustain cycle frequency of 8.3 kHz. This results in a variation in the frequency of emitted light pulse from 118 kHz to 16.6 kHz, or a brightness ratio of 7.1. In order to obtain a nearly linear reduction of brightness through the 8 levels, two cycle lengths are used: a 102 microsecond cycle length, and a 1 20 microsecond cycle length. It may be noted that the 59 kHz effective sustain cycle frequency provides a brightness level approximately 20% greater than that of the older 20 microseconds fixed period system.

Variation of brightness levels for an erase function would be similar to that of the write function, and the modules used to make a full brightness erase function have been described above.

Each function generated by a string of modules begins with a negative pulse and ends with a positive pulse. Therefore, having write functions and erase functions alternate, one after the other, will no longer cause the increase in brightness that characterizes older systems. In addition, since 512 cell parallel addressing is being utilized, the update rate of the system has increased by at least a factor of 5.3.

A large increase in the update rate of the system is not the only important advantage that can be obtained by using the 512 cell parallel addressing technique. A write function using this technique will execute one write operation in a 100-microsecond or greater period. It has been discovered that the border is only required to discharge once during the execution of the write function, as long as that discharge is timed so that it is executed immediately before the actual write operation occurs. The impact of this discovery is very significant, since it means that the brightness of the borders can be reduced by a factor of five for 1 00-microsecond write functions, and by a factor of six for 120-microsecond write functions.

Even when the visual display area 75 is emitting light at its minimum brightness, the 8.3 kHz effective sustain cycle frequency, the average intensity of the light emitted from the border would be slightly greater than the intensity of light emitted from the visual display area 75 of the plasma panel 70. Since the intensity of light emitted from the borders would remain constant at this minimum level, as the visual display area 75 emits more light, the light emitted from the sustainers ís less and less important.

The modification to the system to operate the border sustainer is shown in Figure 1 OA. Two additional logic signals, an X-Border Sustain signal XBS and a Y-border Sustain signal YBS are produced, increasing the memory required in the module generator ROM 44 from 2.5K to 3.5K.

Separate border sustainer logic, however, is no longer needed.

Figure 1 OB shows the applied X-border voltage YXBDR and the applied Y-border voltage YBDR X produced by the logic signals generated by the modulator generator ROM 44 (Figure 1 OA). These logic signals will cause the cells along the X borders to discharge at the point indicated by m, and the cells along the Y-borders to discharge at the point indicated by n.

Although Figure 1 OB shows the border discharges for a 51 2 cell parallel write function, similar border discharges will occur for the erase function and for sustain functions of lower frequency. Since sustain functions producing more light are comprised of shorter strings, only the three lowest light levels (effective sustain cycle frequency of 1 7 kHz, 9.8 kHz, and 8.3 kHz, analogous to the write cycles in Figure 10), having 100 microsecond or longer strings, would produce border discharges. The reason border discharges are produced by erase and some sustain cycles is to prevent visible flashing of the borders at low brightness levels.

The speed at which the system is able to operate is very important. In the case of video data, where the display is being updated constantly, maximizing the update rate of the system is even more important. Since a video display is being updated constantly, each of the 51 2 lines of the display are being alternately erased and rewritten constantly. This means that it takes two 1 OO-microsecond cycles to update a line-one cycle to erase the line and one cycle to write the line.

The present invention provides a technique whereby a horizontal line can be erased nonselectively, and then written selectively in one display cycle of 100 microseconds. By doing this, the display speed or update rate of the system is doubled.

The line erase module is shown in Figure 11, preceded by a positive discharge module and followed by two short sustain equalization modules. The line erase modules is non-selective; that is, it will perform an erase operation on an entire line, without requiring addressing data describing X-axis location to be erased to be loaded.

By comparing the line erase module in Figure 11 with the normal erase module in Figure 4, it is apparent that the logic signals causing the function to be executed are different. Since the logic signals YS and YAP remain the same, the line erase module will selectively erase only along a single horizontal line. However, the X-electrodes are supplied with a signal generated solely by XS, and not by XAP, to perform the line erase operation. This means that the entire horizontal line will be erased, without using X-addressing data. For the normal erase operation, the XAP signal performs the erase function, so only electrodes designated by X-addressing data will be erased.

The advantage the line erase module has in not requiring the X-addressing data is that the 71 microsecond time required to load the Xaddressing data into the driver chips is no longer a factor.

The function in which the line erase module is used is called the erase before write function, and is shown in Figure 12. For the selected horizontal line, there are two types of cells-cells which will be "on" at the end of the erase before write function, and cells which will be "off" after the function. The cells to be left "on" are designated by the X-addressing data, so the write operation, which is selective, will be performed for these cells. The applied cell voltage for such cells is the lower waveform in Figure 1 2.

The cells to be left "off" are not designated by the X-addressing data, so the write operation will not be performed for these cells. The applied cell voltage for such cells is the upper waveform of Figure 12. It may be noted that the entire write pulse is not supplied to non-selected cells; they will therefore be "off" at the end of the erase before write function.

The write before erase function therefore takes the place of two functions-an erase function and a write function. The data rate of the system is thereby doubled, a result which is particularly beneficial if a video picture is to be displayed on the plasma display panel 70.

The present invention therefore solves the problem of lack control of brightness in earlier systems when alternate brightness control write and brightness control erase modes were being utilized. Brightness can now be controlled with precision from the minimum brightness level to the maximum brightness level, regardless of what functions are being performed.

A greater range of brightness is also made possible, with the maximum brightness increased by approximately 20 percent over the maximum brightness of earlier systems. The high intensity of light emitted by the border electrodes has been eliminated as a problem, since the border electrodes are only discharged immediately before a write operation takes place. The intensity of light emitted by the border electrodes is only slightly brighter than that emitted by the visual display area 75 when the system is operating at minimum brightness, and dimmer than the visual display area 75 for all other brightness levels.

Since 512 cell parallel addressing is used, the data rate of the system is increased by a factor of at least 5.3. The utilization of an erase before write function allows the maximum data rate of the plasma display system to be further doubled, to 10.6. These increases in the data rate of the system enable continuous video displays, even those utilizing a television signal as an input.

The module waveform generator technique has provided a means by which to vary the time base to optimize each function being performed. In this way, the data rate of the system is increased and the performance of each of the functions has been optimized. In addition, the modular waveform generator system is easily expandable for additional operating functions.

The amount of memory used has been minimized. The modular waveform generator system described in the preferred ernbodiment uses less than 1/9th the memory of non-modular systems, and it does not need nearly as sophisticated an addressing system.

Claims (12)

Claims

1. An AC plasma panel system, in which electrical signal waveforms are applied to panel electrodes to illuminate a plasma between the electrodes, and wherein the waveforms provide write, erase, and sustain functions for said panels, the system comprising a memory which stores data in data modules defining elemental waveform segments, a circuit which accesses data from said memory to generate strings of said data modules, and a driver connected to said electrodes and responsive to said strings of data modules and which generates, on said electrodes, strings of said elemental waveform segments to provide said write, erase, and sustain functions.

2. An AC plasma panel system, as claimed in claim 1, wherein said memory stores data for data modules having different arbitrary lengths for accomplishing different functions on said panel.

3. An AC plasma panel system, as claimed in claim 1, wherein said circuit, which accesses data from said memory, includes a second memory, coupled bo address the first mentioned memory.

4. An AC plasma panel system, as claimed in claim 1, wherein said circuit accesses data from said memory which will cause said driver to generate a distributed conditioning function.

5. An AC plasma panel system, as claimed in claim 1, wherein said circuit accesses data from said memory which will cause said driver to drive the panel at a variable brightness.

6. An AC plasma panel system, as claimed in claim 1, wherein said circuit accesses strings of data modules from said memory which include a variable number of said data modules.

7. An AC plasma panel system, as claimed in claim 1, wherein said data modules define a positive discharge, a negative discharge, a write, an erase, and a blank sustain elemental waveform segment.

8. An AC plasma panel system as claimed in claim 7, wherein said blank sustain elemental waveform segment is characterized by the emission of substantially no light from said panel during its operation.

9. An AC plasma panel system, as claimed in claim 1, wherein said memory stores data modules defining: a first group of elemental waveform segments characterized by the emission of a first level of light from said panel; a second group of elemental waveform segments characterized by the emission of a second level of light from said panel, said second level being lower than said first; and wherein said circuit accesses data modules from said first group and said second group into complex strings of said data modules.

10. An AC plasma panel system, as claimed in claim 1, wherein said memory stores data defining elemental waveform segments for border electrodes of said panel.

11. An AC plasma panel system, as claimed in claim 1, wherein said AC plasma panel includes lines of cells, each cell being located at the intersection of a pair of said panel electrodes, and wherein said panel provides "on" and "off" charge states for panel cells, and wherein said memory stores data modules defining a complex waveform, said waveform causing selected cells in a line to be turned "on"; and causing all cells in said line to be turned "off".

12. An AC plasma panel system, as claimed in claim 1, wherein said AC plasma panel includes lines of cells, each cell being located at the intersection of a pair of said panel electrodes, and wherein said memory stores data modules defining: a non-selective erase operation to erase all the cells in said line using a complex waveform and a selective write operation to write desired cells in said line after said erase operation.

1 3. An AC plasma panel system substantially as hereinbefore described with reference to and as illustrated in Figs. 3 to 12 of the accompanying drawings.