JP2003046486A - Coding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coding circuit that realizes efficient coding. SOLUTION: The coding circuit for transmitting each coded data sequence obtained by coding an original data sequence on the basis of a prescribed coding rule from a plurality of transmission antenna means is provided with a write port side means that writes each of original data configuring the original data sequence to each unit area in a storage means designated by a write address number and with at least two read port side means that read the original data from each of the unit areas in the storage means according to the designation of the read address number generated according to a read rule corresponding to the coding rule to generate a data sequence corresponding to the coding in response to the coded data sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding circuit,
For example, 3GPP recommendation (to be exact, 3G TS25.2
Although it is 11v3.3.0, it is suitable for use in STTD encoding at the time of downlink physical channel frame generation in a base station for mobile radio communication conforming to "3GPP recommendation" below. Here, STTD is Space Time block coding based Transmit Div.
Abbreviation for ersity.

[0002]

2. Description of the Related Art The following Document 1 describes this STTD encoding.

Reference 1: 3G TS 25.211v
3.3.0 (2000-06) Hereinafter, the name of this document 1 will be referred to as “3GPP recommendation”.

In the downlink physical channel frame in the base station of mobile radio communication conforming to the 3GPP recommendation, if there is open loop transmission diversity, STTD encoding as shown in FIG. 2 is performed.

In FIG. 2, in STTD encoding,
Channel data b0, b1, b2, b3 are stored in this order (b
0 is the first and b3 is the last), the original channel data b0, b1, b2, b3 are transmitted to the antenna 1
From the antenna 2 and -b2, b3, b0, -b1 obtained by applying a predetermined encoding to the original channel data.
Send from

In the antenna 2 data transmitted from the antenna 2, two symbol data (i phase and q
The order of the 2-bit set of phases is called 1 symbol) is changed, and the i bit (b2) of the symbol (S1) that is moved from the back to the front is inverted to -b2, and the symbol (S0) that is moved from the front to the back is changed. The q bit (b1) is inverted to -b1.

On the receiving side that receives the antenna 2 data and the antenna 1 data transmitted from the antenna 1, it is possible to realize transmission diversity.

[0008]

[Problems to be Solved by the Invention] However, 3GP
In order to realize STTD encoding according to P recommendation, it is desired to efficiently solve the following problems (1) to (5).

(1) In order to determine whether i-bit inversion or q-bit inversion is performed, a signal for recognizing whether the symbol has moved from the back to the front or the symbol transferred from the front to the back (hereinafter referred to as " (Referred to as "front-back instruction signal") is required.

(2) SF = 51 of the dedicated channel DPCH
In the slot format of 2, the original channel data is output as it is without STTD encoding the first symbol of each slot (one slot is 5 symbols), and the remaining 4 symbols are STTD encoded.

(3) In order to change the order of symbols in STTD encoding, it is necessary that the contents of channel data of at least 2 symbols be fixed (write completion). However, in STTD encoding, it depends on the SF value. Since the symbol intervals are different, the time from channel data input to antenna 1 and antenna 2 data output (hereinafter,
"STTD encoding processing time") is different.

(4) It is necessary for a base station for mobile radio communication to switch to an arbitrary slot format without interruption for rate control, but it is necessary to devise to realize this.

(5) In the common channel PCCPCH, the method of STTD encoding differs depending on whether the boundary of slots is the boundary of even-numbered slots to odd-numbered slots or the boundary of odd-numbered slots to even-numbered slots. The final symbol of slot 14 is S
Do not TTD encode.

In order to realize STTD encoding, it is necessary to collectively solve all of the problems (1) to (5), but the problems (1) to (5) are: If generalized, it can be applied to encodings other than STTD encoding.

[0015]

In order to solve such a problem, according to the present invention, each encoded data sequence obtained by encoding an original data sequence based on a predetermined encoding rule is transmitted from a plurality of transmitting antenna means. In the encoding circuit that transmits,
(1) write port side means for writing each piece of original data constituting the original data series into a unit area in a storage means designated by a write address number; and (2) a read rule corresponding to the encoding rule. According to the designation of the read address number generated accordingly, the original data is read from the unit area in the storage means to generate at least two read ports for generating the coded data series corresponding to the coded data series. And a side means.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Embodiment Hereinafter, an embodiment will be described with reference to an example in which the encoding circuit according to the present invention is applied to an STTD encoding circuit.

The features common to the first to fifth embodiments are as follows.
The point is that the desired STTD encoding is executed by hardware using memory access control.

(A-1) Configuration of the First Embodiment FIG. 1 shows a configuration example of the main part of the STTD encoding circuit of the present embodiment. The STTD encoding circuit can be installed in a base station for mobile radio communication.

In FIG. 1, the STTD encoder circuit includes a write data generator 11, a write address generator 12, a write side phase management counter 13, an antenna 1 memory 14, an antenna 2 memory 15, and an inverter. 16, a selector 17, an antenna 1 read data acquisition unit 18, an antenna 2 read data acquisition unit 19,
The antenna 1 read address generation unit 20, the antenna 2 read address generation unit 21, and the read side phase management counter 22 are provided.

Of these, the write data generator 11 is a part for receiving the channel data D1 and generating the data D2 for writing in the memories 14 and 15, and executes serial-parallel conversion or the like as necessary. Channel data D
The 1 may be serial data or parallel data, but the write data D2 is 2-bit wide parallel data obtained by parallelizing the i-bit and q-bit of the channel data in symbol units. is there.
However, if the channel data D1 also includes other accompanying data (accompanying data) other than the user data, the bit width of the data D2 is further increased. The accompanying data includes a DTX bit, which will be described later, and a gap enable in the compress mode.

It should be noted that, in the figure, the data D2 is added.
The notation [1: 0] indicates that the write data D2 is 2¹~
Two⁰It indicates that the data is 2-bit parallel data
It The same applies to other signals. For example, write add
The address generation unit 12 specifies the address number for writing.
[N: 0] of the write address signal A1 output for
The write address signal A1 is 2ⁿ~ 2⁰(= 2ⁿ+2
^n-1+2^n-2+ ... + 2 ¹+2⁰) N + 1 bit path
Indicates that it is a Larel signal (where n is an arbitrary signal)
It's just a number). Also, although it does not exist in FIG. 1,
For example, [0] in Figure 4 is 2⁰, That is, 1-bit wide signal
Is shown.

Write side frame pulse WP1 and SF (Spreading Factor) synchronized with the channel data D1.
The write side phase management counter 13 that receives the SF value signal SV indicating the value is a counter that outputs the write side count enable WT1 in accordance with these signals.

Here, the SF value indicated by the SF value signal SV is a value indicating the symbol rate of the slot format. In the case of STTD encoding, SF = 4,8,1
Since there are eight types of 6, 32, 64, 128, 256 and 512, the unique identification display of these eight types is possible with 3 bits.

The write side frame pulse WP1
Is a signal indicating the beginning of the frame of the channel data D1.

Therefore, the write side phase management counter 13 changes the write side count enable WT1 at the phase corresponding to the symbol width corresponding to the SF value signal SV and the write side frame pulse WP1.

The write address generator 12 which receives the write side count enable WT1 and the write side frame pulse WP1 is a counter which outputs the write address signal A1 in response to these signals. The write address generation unit 12 may be a count-down type counter, but here it is assumed to be a counter-up type counter. Since the count-up is executed by incrementing by 1, the address number indicated by the write address signal A1 is divided into [n: 1] and [0].
As shown in (D) and (E). Focusing only on FIG. 3 (E), 0, 1, 0, 1, and 0 and 1 repeat alternately.
0, ...

As is clear from the fact that the same write address signal A1 and the same write data D2 are supplied to the memory 14 for the transmitting antenna 1 and the memory 15 for the transmitting antenna 2, regarding the writing of the data D2. Is
The functions of the memory 14 and the memory 15 are exactly the same. These memories 14 and 15 are of a type that can read data while writing data.

Since the write address signal A1 is [n: 0], both the memory 14 and the memory 15 have the word number 2 ^{n + 1} (that is, the number of addressable memory areas (memory depth) is 2). ^{n + 1} ). Further, the number of bits that can be stored in one word of 2 ^{n + 1} words is 2 bits. The 2 bits have a configuration for storing all bits for one symbol in the memory area specified by each write address signal A1. Therefore, in the example of the channel data of FIG. 2 described above, for example,
Two bits b0 and b1 forming the symbol S0 are stored in the same memory area (word) pointed to by the write address signal A1, and b2 and b3 forming the subsequent symbol S1 are different write address signals A1. Will be stored in another memory area pointed to by.

Regarding the writing of the data D2, the memory 1
4 and the memory 15 have exactly the same functions, the STTD encoding according to the present embodiment for generating the antenna 1 data AD1 and the antenna 2 data AD2 corresponding to the antenna 1 data and the antenna 2 data in FIG. This is characteristically executed when the written data D2 is read from the data 14 and 15.

However, as shown in FIG. 2, when reading from the memory 14 for the antenna 1, the written data D2 is
Since the data D3 is generated only by reading the data in the same procedure as the writing, the data D3 becomes the same data series as the data D2, and the read terminal (output terminal) of the memory 14 is the antenna 1 read data fetching section 18 as it is. It is connected to the.

On the other hand, when reading from the memory 15 for the antenna 2, basically, the written data D2 is read in a procedure different from that at the time of writing, and bit inversion is also performed if necessary, so bit inversion is performed. Inverter 1 to execute
6 and a selector 17 for selecting the inverted bit and the non-inverted bit are inserted between the read terminal of the memory 15 and the antenna 2 read data fetching section 19. The data D4 and the data D2 become different data series due to the difference between the procedure at the time of writing to the memory 15 and the procedure at the time of reading, and the data D4 is further changed to the data D5 by the bit inversion of the inverter 16.
The series of the data D6 is generated by the selector 17 that selects the data D4 and the data D5, and the data D6 is supplied to the antenna 2 read data fetching unit 19.

The data line for transmitting the data D4 is 1
When two signal lines are formed for parallel transmission of 2 bits of symbol, the number of signal lines for transmitting the data D5 and D6 is also two, so that the selector 17 operates the data D
The signal lines for transmitting 4 and D5 are selected one by one and connected to each signal line of the data D6. This allows
For example, it is possible to invert the i bit of the symbol S1 and not invert the q bit.

The antenna 1 read data acquisition section 18 is a section having a function of generating antenna 1 data AD1 by performing parallel-serial conversion on the data D3 input in parallel. In this respect,
The same applies to the antenna 2 lead data acquisition unit 19, and the data D
The antenna 2 data AD2 is generated from 6.

Next, the read side phase management counter 22, the antenna 1 read address generation unit 20, and the antenna 2 read address generation unit 21 address the memories 14 and 15 to generate the data D3 and D4. This is the part to do.

Of these, the lead side phase management counter 22
Is a portion corresponding to the write side phase management counter 13, and is the SF value signal SV and the read side frame pulse R.
Read side count enable RT1 after receiving P1 and
Is output. Here, the read side frame pulse RP1 is a signal corresponding to the write side frame pulse WP1,
This is a signal indicating the frame head of the data D3, D4, antenna 1 data AD1, and antenna 2 data AD2.
The interval of the active level (here, high level) of the read-side frame pulse RP1 is the same as that of the write-side frame pulse WP1, but the phase thereof is changed as shown in FIG. ) And (F)
As shown in FIG. 7, the write side frame pulse WP1 is set at least two symbols later than the write side frame pulse WP1.

The antenna 1 read address generator 20 which receives the read-side frame pulse RP1 and the read-side count enable RT1 finally has the antenna 1
This is a part for outputting a read address signal A2 designating a read address number for reading the data D3 to be the data AD1.

The read address signal A2 is the same [n: 0] signal as the write address signal A1. However, the read address signal A2 is used not only to read the data D3 from the memory 14, but also to read the data D4 from the memory 15 by a part of bits [n: 1] constituting the higher order thereof. To be done.

Similar to the address generator 20, the antenna 1 read address generator 21 that receives the read-side frame pulse RP1 and the read-side count enable RT1.
Is a portion which outputs an addressing signal A3 in order to read data D4 which finally becomes the antenna 2 data AD2. However, the address designating signal A3 is not a [n: 0] signal like the read address signal A2, but is a signal of [0], that is, a 1-bit width, and the read address signal A3 is the least significant bit. A read address signal A23 having an n + 1 bit width in which the upper [n: 1] of the read address signal A2 is an upper bit.
Are used for addressing for reading the data D4 from the memory 15.

The address designation signal A3 is also supplied to the control input terminal of the selector 17 as it is, and is utilized for controlling the selection by the selector 17.

When the associated data other than the user data is used as the channel data D1, it is not necessary to perform bit inversion on the associated data, so the inverter 16 or the like is used for processing the associated data. No need.

The operation of this embodiment having the above-mentioned structure will be described below.

(A-2) Operation of the First Embodiment FIG. 3 shows a timing chart of STTD encoding of the present embodiment. When the clock is input after the power is turned on, the write side phase management counter 13, the read side phase management counter 22, the write address generation unit 12, the antenna 1 read address and the antenna 2 read address generation unit 20,
21 is self-propelled based on the SF value signal SV set by a higher-level device (not shown) such as a monitoring controller.

The write side phase management counter 13 generates the count enable WT1 shown in FIG. 3 (C) in symbol increments for the write address signal A1. The symbol width of this count enable WT1 changes depending on the SF value set by the SF value signal SV.

A write address signal A1 common to the memories 14 and 15 output from the write address generator 12.
Counts up when the count enable is 1 (that is, when it is at a high level), the least significant bit [0] thereof is 0, 1, 0, 1, ... As shown in FIG.
And changes.

When the high level of the write side frame pulse WP1 indicating the beginning of the channel data D1 shown in FIG. 3B is input, the write side phase management counter 13 and the write address generation unit 12 take in the initial value 0, It is adjusted to the phase of the input channel data D1.

Further, in the write data generator 11, for example, the serially input i-bit and q-bit channel data D1 are parallelized in symbol units to write data common to the antenna 14 and antenna 2 memories 14 and 15. Generate D2. The write data D2 can include accompanying data accompanying the channel data, such as DTX bits and gap enable in the compress mode (in that case, the number of parallelized bits increases as described above).

In the example of FIG. 3B, the symbols A, B,
.. are input as the channel data D1. Of these, for example, the bits corresponding to the symbol C are b0 and b1, and the bits corresponding to the symbol D are b.
2 and b3, the lower 4 bits of the write address signal A1 are 0010, that is, FIG.
The write address signal A1 of (D) is 1 (that is, "001" which is the upper 3 bits of the "0010").
Then, when the write address signal A1 of FIG. 3 (E) is 0 (that is, the least significant bit “0” of the “0010”), the bits b0 and b1 are the address number (the lower order of the address number). (4 bits) is written in each memory area of the memory 14 and the memory 15 designated by 0010, and when the write address signal A1 is incremented (counted up) by 1 and the lower 4 bits become 0011 (that is, FIG. 3). When the write address signal A1 in (D) is 1,
When the write address signal A1 of FIG. 3 (E) becomes 1, the bits b2 and b3 are (the lower 4 bits of) the address number.
It is written in each memory area of the memory 14 and the memory 15 designated by 0011.

By repeating the above processing, the memory 1
Symbols having the same contents are written in the memory areas designated by the same address numbers 4 and 15.

In this case, the write address signal A1
However, this does not mean that the bit width of the write address signal A1 is not less than 3 bits.

On the other hand, in the read side phase management counter 22, as in the write side (write side), the read address signals A2 and A3 supplied to the antenna 14 and antenna 2 memories 14 and 15 are shown in FIG. The count enable RT1 shown in () is generated in symbol steps. The read address signals A2 and A3 are counted up when the count enable RT1 is 1 (that is, at high level).

Therefore, the read address signals A2 and A3
Count up at the same time, but the two least significant bits of the same phase are in a mutually inverted relationship. That is, FIG.
While the least significant bit [0] of the address signal A2 shown in (I) changes to 0, 1, 0, 1, ..., The address signal A3 shown in FIG. It changes to 0, ...

In the address signal A23 for designating the read address in the memory 15, the address signal A3 is used as the least significant bit, and [n: 1] of the address signal A2 shown in FIG. Because of the configuration, the original input channel data D1 or data D2
Compared with, a signal in which the order of symbols is changed is obtained. For example, if the array of data D2 is b0, b1, b2, b
3 (earlier on the left side), the address signal A23
The array of the data D4 read from the memory 15 is b2, b3, b0, b1 (earlier to the left).

Since the high level of the read side frame pulse RP1 shown in FIG. 3 (F) is output with a delay of exactly 2 symbols from the high level of the write side frame pulse WP1 of FIG. 3 (A), Reading is started when the writing of the first two symbols (that is, symbols A and B) in the channel data D1 to the memories 14 and 15 is completed. In order to change the order of the symbols, the order of the symbols in the channel data D1 is slower between the two symbols (for example, the symbols A and B) to be replaced, and the symbols are written later in the memories 14 and 15. Since (in this case, the symbol B) is read earlier in the channel data D1 and needs to be read earlier than the symbol (in this case, the symbol A) previously written in the memories 14 and 15, writing is delayed. These replacements cannot be performed until the writing of the symbol to be inserted is completed.

Therefore, the initial value 0 of the least significant bit 0, 1, 0, 1, ... Of the address signal A2 is fetched, and the address signal A3 is 1, 0, 1, 1.
The initial value 1 of 0, ... Is taken in when the writing of the two symbols A and B is completed.

Antenna 1 data AD1 shown in FIG. 3 (K)
Is a data sequence which is exactly the same as the input channel data D1 except that the phase is delayed by the two symbols. Note that when the data AD1 is transmitted, it is possible to read the data without waiting for the completion of the writing of the second symbol (symbol B) because it is not necessary to change the data order, but the data order needs to be changed. Since the STTD encoding is performed in phase with the antenna 2 data AD2, the data AD1 is also delayed by 2 symbols.

Finally, in the antenna 2 data AD2 shown in FIG. 3L, the data sequence is changed, and bit inversion is also performed, so that the data series -B, A-, -D, C-,-.
F, E-, ... Here, -D is -b2
Corresponding to b3, C- corresponds to b0-b1. Also,
-B2 indicates that bit b2 written in memory 15 is inverted, -b1 indicates that bit b1 written in memory 15 is inverted, and "-" is not added. The bit (eg, b0) indicates a non-inverted bit that has not been inverted.

As described above, the inverter 16 performs the inversion, and the selection of the inverted bit and the non-inverted bit is performed by supplying the address signal A3 output from the address generation unit 21 to the control input terminal of the selector 17. ,Control.

In the case of FIG. 3, when the address signal A3 is 1, the selector 17 controls the earlier signal line (for example, the data D) with respect to the position in the data AD2 after serial conversion.
The signal line for transmitting the bit b2 in 4) is the inverter 16
In addition to selecting the one passing through, the slower signal line (for example, the signal line transmitting the bit b3 in the data D4) is selected not to pass through the inverter 16. Conversely, when the address signal A3 is 0, The slower signal line (for example, the signal line transmitting the bit b1 in the data D4) is selected through the inverter 16 and the earlier signal line (for example, the signal transmitting the bit b0 in the data D4). The line) is controlled so as to select one that does not pass through the inverter 16.

That is, if the read address signal A3 is 1, what is read from the memory 15 at that time is STT.
Since the symbol is moved from the back to the front by D encoding, the i bit is inverted, and if the read address signal A3 is 0, the symbol read at that time is the symbol transferred from the front to the back, so the q bit is inverted.

In this way, the channel data D1
The antenna 1 data AD1 and the antenna 2 data AD2, which are the STTD encoding results for, can be transmitted.

(A-3) Effects of the First Embodiment As described above, according to the present embodiment, the address signal (A3) can be utilized as the above-mentioned front-back instruction signal.
The STTD encoding can be realized very efficiently for the reason that it is not necessary to separately provide the front-back instruction signal.

(B) Second Embodiment Hereinafter, only the points of this embodiment different from the first embodiment will be described.

In this embodiment, S of the dedicated channel DPCH is used.
In the slot format of F = 512, original channel data is output as it is without STTD encoding for the first symbol of each slot (one slot is 5 symbols), and the remaining 4
The present invention provides an efficient realization method in terms of the need to STTD encode symbols.

When SF = 512, the channel type is DPC
Since only H is used, a signal indicating the channel type is unnecessary.

(B-2) Configuration and Operation of Second Embodiment FIG. 4 shows a configuration example of the main part of the STTD encoding circuit of this embodiment. The functions of the components and signals in FIG. 4 given the same reference numerals as in FIG. 1 are basically the same as those in the first embodiment. In addition, corresponding reference numerals 13A, 20A, 21
The functions of the respective constituent parts provided with A and 22A correspond to those of the first embodiment.

In the present embodiment, the slot concept which is not used in the first embodiment is used. In order to correspond to the slot, another selector 2 is provided in the next stage of the selector 17.
5, and the SF value signal SV is supplied to the write address generation unit 12
A, antenna 1 and antenna 2 are connected to the read address generation units 20A and 21A, and the control input terminal of the selector 25.

The selector 25 receives the SF value signal SV and the read side slot counter value CT2, which will be described later, at its control input terminal, so that when SF = 512 of DPCH, the first symbol in the slot is the antenna 1 read data D1.
Select 0, otherwise, antenna 2 lead data D
The data D6 derived from 11 is selected. As a result, as shown in FIG. 5 (N), the same symbol as the data AD1 shown in FIG. 5 (M) is arranged at the first symbol in each slot of the data AD21.

Further, the write side phase management counter 13A which is supplied with the SF value signal SV counts the number of symbols in one slot and counts the number (hereinafter, this count value is referred to as "slot counter value"). A counter that supplies CT1 to the write address generation unit 12A.
Since the number of symbols in one slot is 5, this counter is a quinary counter that counts from 0 to 4. The write-side phase management counter 13A also outputs the write-side count enable WT1 similarly to the write-side phase management counter 13 of the first embodiment.

The write address generation unit 12A that receives the write side count enable WT1 and the slot counter value CT1 has basically the same function as the write address generation unit 12, but outputs the address signal A5 [ The function of the first counter for outputting 2: 0] (that is, lower 3 bits) and the function of the second counter for outputting [n: 3] higher than the lower 3 bits are different.

That is, the first counter outputs the incrementing 3-bit parallel count value, but the count value is the write side slot counter value C.
It is an octal counter that stops incrementing when T1 is 0 (holds the count value at that time), outputs the same count value continuously due to the stop, and then starts incrementing again. n: 3] is 0 to 2 when the write side slot counter value CT1 is 0.
^{It is} a 2 ⁿ⁻² binary counter that counts up to ⁿ⁻² −1.

[2: 0] of the address signal A5 obtained by the first counter is as shown in FIG. 5F, and the address signal A5 obtained by the second counter is A2.
[N: 3] of 5 is as shown in FIG. Figure 5
As is clear from (F), the address signal A5 [2:
0] is 0, 0, 1, 2, 3, 4, 4, 5, 6, 7,
0, 0, 1, 2, ... And 0 (or 4) are generated twice for every 5 counts.

On the other hand, the phase management counter 22A on the read side (read side) receives the frame pulse RP1 on the read side and the SF value signal SV shown in FIG.
5 is a circuit for outputting the slot counter value CT2 shown in FIG. 5 and the read side count enable RT1 shown in FIG. The slot counter value CT2 is generated by a quinary counter incorporated in the read side phase management counter 22A, like the write side phase management counter 13A.

The slot counter value CT2, read side count enable RT1, read side frame pulse R
P1 and antenna 1 for receiving the SF value signal SV
The read address generation unit 20A is a counter that outputs the address signal A7. The corresponding address signal A of [n: 0]
The contents of No. 7 are as shown in FIGS. 5 (J) and (K).
The antenna 1 read address generation unit 20A also has a built-in counter for outputting [n: 3] of the address signal A7 and a counter for outputting [2: 0] like the write address generation unit 12A. ing.

The slot counter value CT2, the read side count enable RT1, the read side frame pulse R
P1 and antenna 2 for receiving the SF value signal SV
The read address generation unit 21A [2:
0] for outputting the address signal A6.

Of the memories 14 and 15, the address signal A7 is used as a read address for the memory 14.
Is supplied to the memory 15, and the address signal A7 is supplied to the memory 15.
6 is supplied. The address signal A76 is output from the antenna 2 read address generation unit 21A [2:
0] address signal A6 is the lower 3 bits, and [n: 3] of the address signal A7 is the upper bit thereof [n: 0].

The least significant bit [0] of the address signal A6 is supplied to the control input terminal of the selector 17.

With such a configuration, the address generator 21A
Holds the value of [0] of the address signal A6 when the read side slot counter CT2 is 0, repeats 1 and 0 inversions at other times, and also [2: 1] of the address signal A6. , [0] is 0, the data D11 is read by counting up. Data D1 read by the address signal A76
1 is an inverter 16, a selector 17 and a selector 2
As a result of being processed in 5, data D7 is obtained. The data D7 is data that becomes the data AD21 of FIG. 5N only by receiving serial-parallel conversion or the like.

When the high level of the write side frame pulse WP1 shown in FIG. 5A is input, the slot counter value CT1 of the write side phase management counter 13A and the write address A5 take in the initial value 0, The first embodiment is that writing to the memories 14 and 15 is synchronized with the phase of the input channel data D1 and that the high level of the read side frame pulse RP1 is input when at least 2 symbols of the input channel data D1 are determined. It is the same as the form.

Also, as is clear from a comparison between FIGS. 5B and 5M, also in this embodiment, the data AD1 (data D10 and) data AD1 becomes the same data series as the input channel data D1. There is.

(B-2) Effect of Second Embodiment As described above, according to the present embodiment, the same effect as that of the first embodiment can be obtained.

In addition, in this embodiment, 1 of each slot is used.
The input channel data (D1) is output as it is without STTD encoding only for the symbol th, and the subsequent 4 symbols are SF of the individual channel DPCH for STTD encoding.
It is possible to efficiently support the slot format of = 512.

(C) Third Embodiment Hereinafter, only differences of the present embodiment from the first and second embodiments will be described.

In the first and second embodiments, since the antenna 1 and antenna 2 data are output when at least 2 symbols of the input channel data are determined, the STTD encoding processing time differs depending on the SF value. The present embodiment is characterized in that the STTD encoding processing time is constant regardless of the SF value (difference).

(C-1) Configuration and Operation of Third Embodiment FIG. 6 shows a configuration example of the main part of the STTD encoding circuit of this embodiment. The functions of components and signals in FIG. 6 that are assigned the same reference numerals as in FIG. 4 are basically the same as those in the second embodiment. In addition, corresponding reference numerals 12B, 14A, 15
The functions of the respective constituent parts provided with A, 20B, 21B, and 22B correspond to those of the second embodiment.

Write address generation unit 12B of this embodiment
The address signal A8 output by is similar to the address signal A5 of the second embodiment except that it is set to [7: 0]. As is clear from the address signal A8 being [7: 0], the memory 14A of the present embodiment,
The number of words of 15 A (the number of addressable memory areas) is 256 (= 28).

Further, the address signal A9 output from the address generating section 20B on the read side is [7: 0] corresponding to the number of words 256, and the higher bits [7: 3] of the address signal A9 are higher bits. Address generator 2
1B outputs [2: 0] of the address signal A6 to the lower 3
The address signal A96 generated by setting the bit also
[7: 0].

FIG. 7 shows how the channel data D1 at the symbol intervals corresponding to various SF values are input from the high level of the write side frame pulse WP1 indicating the frame head of the channel data D1.

As described above, in order to perform STTD encoding and switch the order of the two symbols, the memory 1
Writing to 4A and 15A must be completed at least 2 symbols. In the case of SF = 512, the symbol interval is the largest, and in the section corresponding to one symbol of SF = 512, 128 symbols of SF = 4 having the smallest symbol interval are included.

That is, when the writing of the second symbol of the channel data D1 is completed at SF = 512, the writing of the channel data of 2 symbols or more is completed at all other SF values, so that the channel data at SF = 512 is completed. When the second symbol of is determined, the high level of the read side frame pulse RP1 is input and the outputs of the antenna 1 and antenna 2 data AD1 and AD21 (data D10,
If you start (reading D11), STT
Even if the D-encoding processing time (that is, the phase difference between the write-side frame pulse WP1 and the read-side frame pulse RP1) is fixed to a constant value, any S that may occur
It becomes possible to correspond to the F value.

As shown in FIG. 7, when the second symbol of SF = 512 is confirmed, 129 symbols of SF = 4 are confirmed. After that, if the first high level of the read side frame pulse RP1 is input. Good (L2
<L1). In order to read the data of 129 symbols (pieces) stored in the memories 14A and 15A without being overwritten by the subsequent data, a memory depth of 130 words or more is required, and the minimum memory depth that satisfies this condition. The size is 256 words.

A method of changing the STTD encoding processing time itself can be considered to cope with the change of the SF value, but in order to take such a method, a complicated circuit structure is required for that. On the other hand, as in this embodiment, S
The TTD encoding processing time is fixed, and the memory 14A, 1
When a sufficient number of words is provided for 5A, a complicated circuit configuration is unnecessary.

Further, in the present embodiment, the channel data supply block (the part that outputs the channel data D1) located in the preceding stage of the STTD encoding circuit has the antenna 1 and the antenna 2 which are the final outputs of the STTD encoding circuit.
Constant STTD from the output phase of data AD1 and AD21
Channel data D with the phase obtained by calculating the encoding processing time backward
Since 1 can be output, the circuit configuration can be simplified.

(C-2) Effects of the Third Embodiment As described above, according to the present embodiment, it is possible to obtain the same effects as the effects of the second embodiment.

In addition, in this embodiment, since the fixed STTD encoding processing time can be used without depending on the SF value, it is possible to efficiently cope with the dynamic change of the SF value with a simple structure. It becomes possible.

Further, according to the present embodiment, the circuit configuration of the channel data supply block which outputs the channel data (D1) in the preceding stage of the STTD encoding circuit can be simplified, so that the STTD including the peripheral circuits can be simplified. The configuration efficiency of the encoding circuit can be improved.

(D) Fourth Embodiment Hereinafter, only the points of this embodiment different from the first to third embodiments will be described.

The present embodiment is characterized by switching to an arbitrary slot format without interruption for rate control.

(D-1) Configuration and Operation of Fourth Embodiment FIG. 8 shows a configuration example of the main part of the STTD encoding circuit of the present embodiment. In FIG. 8, the functions of components and signals given the same reference numerals as those in FIG. 4 are basically the same as those in the third embodiment. Further, the functions of the signals provided with the corresponding codes SV1 and SV2 correspond to the SF value signal SV of the third embodiment. SV1, SV2, and SV have basically the same signal content, but different output timings.

In this embodiment, the register 23 is provided to generate the SF value signal SV1 and the register 24 is provided to generate the SF value signal SV2.

The register 23 is a register for taking in the SF value signal SV inputted to the write side when the high level of the write side frame pulse WP1 is inputted, and the SF value signal SV taken into the register 23 is SV1, and the register 24, the write side phase management counter 13A,
It is supplied to the write address generation unit 12B.

The register 24 takes in the SF value signal SV1 when the high level of the read side frame pulse RP1 is input. The SF value signal SV1 captured in the register 24 becomes SV2 and is supplied to the read side phase management counter 22B, the antenna 2 read address generation unit 21B, the antenna 1 read address generation unit 20B, and the control input terminal of the selector 25. .

Since the SF value signal SV is a signal of [2: 0], SV1 and SV2 are naturally signals of [2: 0]. The registers 23 and 24 that process the SF value signals SV, SV1, and SV2 are, for example, three D-FFs (D-FF (D) in which the same write-side frame pulse WP1 (or read-side frame pulse RP1) is connected to the clock input terminal.
It can be configured by arranging flip-flops) in parallel.

Further, the register 26 newly added in the present embodiment, when the high level of the write side frame pulse WP1 is supplied to [7: 3] of the address signal A8 output from the write address generator 12B. The address signal A8 [7: 3] of the fetched address signal A8.
Is supplied to the antenna 1 read address generator 20B as an address signal A10. Register 26
Each time the high level of the write-side frame pulse WP1 is supplied, the fetch operation is repeated, so that [7:
3] is [7: 3] of the write address signal A8 when writing is started at the head of the frame.

When the antenna 1 read address generator 20B receiving the address signal A10 from the register 26 receives the high level supply of the read side frame pulse RP1, it outputs the lower bit [2: 0] of the read address signal A11 to be output. 0 is fetched, and the value of the address signal A10 is fetched in the upper bits [7: 3]. Like the registers 23 and 24, the register 26 can also be configured by arranging D-FFs in parallel, but the number of D-FFs to be arranged becomes five corresponding to [7: 3].

When the write-side frame pulse WP1 is supplied with a high level, the write address generator 12B takes in 0 to the lower bit [2: 0] of the write address signal A8 to be output, and the upper bit [7]. : 3], the operation of taking in the value obtained by adding 1 to the previous value is executed.

Timing charts of the STTD encoding circuit of this embodiment are shown in FIGS.

FIG. 9 shows the state of the initial operation. When the clock is input after the power is turned on, the write side phase management counter 13A, the read side phase management counter 22B, the write address generation section 12B, the antenna 1 read address and The antenna 2 read address generation units 20B and 21B are free-running with the initial values of the SF value signals SV1 and SV2, which are the default SF values (in FIG. 9, the SV1 and SV2 have the same arbitrary initial values).

In this state, if the high level of the write side frame pulse WP1 shown in FIG.
As shown in (B), since the SF value (SF = 512 in the example of FIG. 9) set by the higher-level device such as the monitoring controller is fetched into the register 23, the write-side constituent elements 12B, 13
A refers to the SF value as the SF value signal SV1.

At the same time, FIG. 9 (D) and
As shown in (E), the lower bits [2: 0] of the write address signal A8 are set to 0, and the upper bits [7: 3] are set to the value i + 1 obtained by adding 1 to the previous value i. On the write side, the frame phase of SF = 512 is fixed. At this time, the value i + 1 of the high-order bits [7: 3] of the write address signal A8 at the start of writing is the register 2
6 is taken in and held.

Further, in the register 24, when the high level of the read side frame pulse RP1 is input, the value of the SF value signal SV1 is taken in as SV2, so that the read side constituent elements 22B, 21B and 20B are set to the SV2. With reference to the value, this value is also supplied to the control input terminal of the selector 25.

At the same time, the antenna 1 read address generator 20B outputs 0 to the lower bits [2: 0] of the read address signal A11 and the address signal supplied from the register 26 to the upper bits [7: 3]. A10 value i +
When 1 is taken in and the antenna 2 read address generation unit 21B takes 1 in [2: 0] of the read address signal A6, the frame phase of SF = 512 is fixed on the read side as well.

On the other hand, in FIGS. 10A to 10O showing the state of slot format switching, the write side is slotted by the write side frame pulse WP1 and the read side is set by the read side frame pulse RP1 just like the initial operation. The format switches.

Here, when the write-side frame pulse WP1 is input at the high level, the write address generator 12B takes in i + 1 obtained by adding 1 to the previous value i to the upper bits [7: 3] of the write address signal A8. Figure 1 for the reason
This will be described with reference to 1.

FIG. 11 shows a state in which 0 is written in all the bits of the write address signal A8 when the slot format is switched from the frame of SF = 512 to the frame of SF = 4 on the write side.

As shown in FIG. 11, when the value of the write address signal A8 at the end of the frame (SF = 512) before switching the slot format is near 0 (higher bits [7: 3] are 0), for example, the most symbol Assuming that the frame is switched to the SF = 4 frame having a short interval, the address number 3 (that is, [7: 3] = 0, [2: 0] = 3) designated by the write address signal A8 of the SF = 512 frame is set. The data z written in the word is overwritten with the data D of SF = 4 frames before being read from the memories 14A and 15A, and cannot be transmitted from the STTD encoding circuit.

To avoid this, the address signal A
Although it is possible to use a value obtained by adding 1 to the value of lower bits [2: 0] as the first write address after the slot format switching, instead of adding 1 to the value i of [7: 3] of 8 The value of the lower bit [2: 0] of the write address A8 immediately after switching the slot format is 0, the value of the lower bit [2: 0] of the antenna 1 read address A11 is 0, and the value of the antenna 2 read address A6 is [2: 0]. Unless the value of 1 is set to 1, it is difficult to switch the order of two symbols adjacent to each other by the least significant bit of the antenna 2 read address signal A116, and to use the i-bit inversion and the q-bit inversion as the anteroposterior instruction signal. . Therefore, the write address A immediately after switching the slot format
It is necessary to add 1 to the value i of [7: 3] of 8.

In this way, the address signal A8 [7:
In addition to taking in the value obtained by adding 1 to the previous value in [3],
By incorporating 0 in [2: 0], all bits [7: 0] of the write address signal A0 are increased by 8 at the maximum and increased by 1 at the minimum from the address of the final symbol of the frame before the slot format switching. Under the limited number of words, the data on the memories 14A and 15A that have not been read out are circulated by incrementing the address signal A8.
In order to prevent the data from being overwritten in accordance with the above, it is advantageous that the increase width 8 is small. Therefore, instead of changing the address signal A8 to [7: 3] and [2: 0], for example,
When divided into [7: 2] and [1: 0] as described below,
The maximum increment is 4, which is even more advantageous.

However, even if it is divided into [7: 3] and [2: 0], at least 248 at least until the last symbol of the previous frame which has not been read out is overwritten.
(= 256-8) There is a word margin. The length of L2 in FIG. 11 is the same as that in FIG. 7, and since L2 is smaller than L1 in FIG. 7, L2 is smaller than 128 words. Therefore, it can be said that this initial value acquisition method is sufficiently safe.

As a method of avoiding the risk of overwriting, the memory is formed into a two-sided structure (two memories corresponding to the memories 14A and 15A are provided, and a total of four memories are used), and before switching the slot format. Although it is conceivable to switch the memory to be used after switching, etc., considering that the control becomes complicated and the memory capacity is doubled, the present embodiment has a simpler circuit and a smaller circuit scale. It is advantageous and more efficient.

Incidentally, Antenna 1 read address signal A1
Regarding the value of the upper bits [7: 3] of the write address signal A8 when the writing is started on the write side, which is held in the register 26, is taken into the upper bits [7: 3] of 1. In the initial operation as shown in FIG. 9, the high-order bits [7: 3] of the write address signal A8 and the antenna 1 read address signal A11 are input when the frame pulses WP1 and RP1 are input at the high level on both the write side and the read side.
This is because these values do not necessarily match just by taking in the value obtained by adding 1 to the previous value.

Further, in this embodiment, the registers 23 and 2 are
4, the phase management counters 13A and 22B on the write side and the read side and the address generation units 12B, 20B and 21 are provided.
Since B independently refers to the SF value signals SV1 and SV2, antenna 1 and antenna 2 data AD1 and AV
D21 is not affected by the slot format switching of the input channel data D1 and can provide an STTD encoding circuit in which instantaneous interruption does not occur even when the slot format is switched.

(D-2) Effects of the Fourth Embodiment According to this embodiment, it is possible to obtain the same effects as the effects of the third embodiment.

In addition, in this embodiment, it is possible to safely and efficiently perform switching to an arbitrary slot format without interruption and perform desired rate control.

(E) Fifth Embodiment Hereinafter, only differences of the present embodiment from the first to fourth embodiments will be described.

In this embodiment, the common channel PCCPCH is different in the STTD encoding method depending on whether the slot boundary is the boundary from the even numbered slot to the odd numbered slot or the boundary from the odd numbered slot to the even numbered slot. It is characterized by being able to respond.

(E-1) Configuration and Operation of Fifth Embodiment FIG. 12 shows a configuration example of the main part of the STTD encoding circuit of this embodiment. The functions of the components and signals in FIG. 12 that are assigned the same reference numerals as in FIG. 8 are basically the same as those in the fourth embodiment. Further, the functions of the constituent parts 12C, 20C, 21C, 22C, 25A given the reference numerals corresponding to those in FIG. 8 correspond to those of the fourth embodiment.

In FIG. 12, in this embodiment, the PCC
Channel type signal C for recognizing PCH
K is supplied to the write address generation unit 12C, the antenna 1 and antenna 2 read address generation units 20C and 21C, and the control input terminal of the selector 25A.

In this embodiment, the high level of the write-side and read-side frame pulses WP1 and RP1 is 1.
It is premised that the data is input in frame (10 ms) units.

Further, in the present embodiment, the selector 25A
A final symbol designating signal LD indicating the final symbol of one frame generated by the read side phase management counter 22C is supplied to the control input terminal of.

In the PCCPCH, the last symbol in each even-numbered slot (eg, slot # 0, slot # 2, etc.) is an adjacent odd-numbered slot (eg, slot # 0).
Since the STTD encoding is performed by changing the order of the first symbol (e.g., slot # 1), it is necessary to fix at least 3 symbols of the channel data of SF = 256 before outputting the antenna 1 and antenna 2 data.

FIG. 13 is a timing chart (PCCPCH) of STTD encoding of this embodiment. FIG.
The hatched area is the Primary SH area, which is to be inserted in the subsequent block.
Any value may be used as the STTD encoded output of PCH.

PCCPCH by channel type signal CK
At that time, the following STTD encoding is performed. PCC
Since SF = 256 in PCH and the number of symbols in one slot is 10, the slot counter value CT1,
The slot counters in the phase management counters 13A and 22C that output CT2 are decimal counters that count from 0 to 9.

In FIG. 13, one frame (10 ms)
The write side frame pulse WP1 shown in FIG.
13 is input, the write-side phase management counter 13A and the write address generator 12C
As shown in (D), (E) and (F), the initial value 0 is fetched as the write side slot counter value CT1 and the write address signal A8.

The slot counter for generating the write address signal A8 has a write side slot counter value CT1 of 0.
It is a 256-ary counter that holds the value when, and counts up from 0 to 255 at other times.

When the read side frame pulse RP1 is input at the input phase shown in the third and fourth embodiments (that is, when the channel data of SF = 512 is input when 2 symbols are determined), as shown in FIG. SF = 25
6, the channel data is determined by 3 symbols before the antenna 1 and antenna 2 data is output.
Special STTD encoding of CH can be performed.

When the high level of the read side frame pulse RP1 is input, the read side phase management counter 22C and the antenna 1 read address signal A12 have an initial value 0.
The antenna 2 read address signal A13 has an initial value of 1
Take in.

Further, the antenna 1 read address signal A12 shown in FIGS. 13K and 13L is incremented in the same manner as the write address, and the antenna 2 read address signal A13 shown in FIG. 13M is the read side slot. When the counter value CT2 is 0, the value is held, in other cases, [0] repeats 1,0 inversion, and [2: 1] counts up when [0] is 0.

In the antenna 1, like the case of the write side, the data is read only by the antenna 1 read data fetch section 18, but in the antenna 2, the antenna 2 read data D1 is fetched.
3 is inverted by i-bit or q-bit by using [0] of the antenna 2 read address signal A13 as the forward / backward instruction signal, and then the selector 25A outputs P by the channel type signal CK.
In the case of CCPCH, the antenna 1 read data (without changing the order of symbols) D12 is used in the last symbol of the frame (indicated by the last symbol designating signal LD), and in other cases, antenna 2 read data (changing the order of symbols). Yes) D13 is selected and taken into the antenna 2 read data fetching section 19.

(E-2) Effects of Fifth Embodiment As described above, according to this embodiment, the same effects as those of the fourth embodiment can be obtained.

In addition, in this embodiment, STTD encoding can be efficiently executed even in the case of PCCPCH.

(F) Other Embodiments In the first to fifth embodiments, two memories (for example, 14 and 15) for the antenna 1 and the antenna 2 are used, but the write port is 1 instead. Alternatively, one 1-write / 2-read memory having two read ports may be used.

In the second embodiment, the write address, the antenna 1 and antenna 2 read address bits are divided into [n: 3] and [2: 0], but the input channel data is 2 as shown in FIG. If the read is started when the symbol is fixed, it may be divided into [n: 2] and [1: 0]. Also, in SF = 512 of DPCH, S
The first symbol of a slot that is not TTD encoded is always the TPC bit (see Table of 3GPP Recommendation).
11), if the TPC bit is inserted in the subsequent block, [n: 0] is set without dividing the write address, antenna 1 and antenna 2 read address bits into [n: 3] and [2: 0]. A method of holding the value when the slot counter value is 0 as in the case of [2: 0] may be used.

However, in this case, since the data of the first symbol of the slot is overwritten with the data of the second symbol,
Among the information associated with the channel data, the gap enable signal in the compress mode cannot pass through the STTD encoding circuit.

In the third to fifth embodiments, S
In order to uniquely determine the TTD encoding processing time without depending on the SF value, the memory depth is set to 256 words and SF =
Although the high level of the read side frame pulse is input at the timing when the second symbol of 512 channel data is determined, the depth of the memory may be 512 words or more (the MSB of the address bit is 8 or more). Is.

Further, the timing of inputting the read side frame pulse can also be the timing at which the m-th symbol (m ≧ 3) of the channel data of SF = 512 is determined. In this case, the memory depth is required to store the number of SF = 4 symbols existing in the time difference between the write side frame pulse and the read side frame pulse.

Further, in the fourth embodiment, the method of fetching the initial value of the write address, antenna 1 and antenna 2 read address bits is divided into [7: 3] and [2: 0]. : 2] and [1: 0] may be used. Further, although the example in which the phases of the write-side and read-side frame pulses are the same has been described, the present invention is not limited to the case where the phases of the write-side and read-side frame pulses are changed (of the write-side and read-side frame pulses, respectively). It is applicable (even if the phase difference varies). That is, the switching of the slot format can deal with the output phase change of the physical channel frame.

In the fifth embodiment, the write address, the antenna 1 and antenna 2 read address bits are divided into [7: 3] and [2: 0], which are [7: 2] and [7: 2]. 1: 0]. In addition, the write side and read side frame pulses are 1 frame (10 m
s) is assumed to be input in units (in the first to fourth embodiments, the input of the frame pulse is 10
It does not matter whether it is in units of ms or only once at the start of transmission) or only once at the start of transmission, and the initial value acquisition at the time of frame pulse input is eliminated in the same way as in the fourth embodiment, and the case classification by channel type is eliminated. You can also At that time, a counter for counting the length of one frame is provided in the write-side and read-side phase management counters,
At the beginning of each frame, the write address and the antenna 1 read address must be set to 0, and the antenna 2 read address must be set to 1 to initialize the STTD encoding circuit.

Further, in order to completely execute the STTD encoding, it is necessary to configure a circuit having all the characteristics of the above-mentioned first to fifth embodiments. Assuming that
It is also considered effective to use the features of each embodiment alone.

In the first to fifth embodiments described above, the present invention is realized mainly by hardware, but the functions of the present invention can be realized by software.

[0150]

As described above, according to the present invention, efficient coding can be realized.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration example of a main part of an STTD encoding circuit according to a first embodiment.

FIG. 2 is a conceptual diagram illustrating an outline of STTD encoding.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is a schematic diagram showing a configuration example of a main part of an STTD encoding circuit according to a second embodiment.

FIG. 5 is a timing chart showing the operation of the second embodiment.

FIG. 6 is a schematic diagram showing a configuration example of a main part of an STTD encoding circuit according to a third embodiment.

FIG. 7 is input channel data showing the operation of the third embodiment.

FIG. 8 is a schematic diagram showing a configuration example of a main part of an STTD encoding circuit according to a fourth embodiment.

FIG. 9 is a timing chart showing an initial operation of the fourth embodiment.

FIG. 10 is a timing chart showing a slot format switching operation of the fourth embodiment.

FIG. 11 is a timing chart showing overwriting of channel data according to the fourth embodiment.

FIG. 12 is a schematic diagram showing a configuration example of a main part of an STTD encoding circuit according to a fifth embodiment.

FIG. 13 is a timing chart showing the operation of the fifth embodiment.

[Explanation of symbols]

11 ... Write data generation unit, 12 ... Write address generation unit, 13 ... Write side phase management counter, 14 ... Antenna 1 memory, 15 ... Antenna 2 memory, 16 ... Inverter, 17 ... Inverting non-inverting selector, 18 ... Antenna DESCRIPTION OF SYMBOLS 1 read data acquisition part, 19 ... Antenna 2 read data acquisition part, 20 ... Antenna 1 read address generation part, 21 ... Antenna 2 read address generation part, 22 ... Read side phase management counter, 23 ... Write side SF value acquisition Included register, 24
... Read side SF value fetch register, 25 ... Antenna data selector, 26 ... Write start upper address holding register.

Claims (5)

[Claims] 1. An encoding circuit for transmitting each encoded data sequence obtained by encoding an original data sequence based on a predetermined encoding rule from a plurality of transmission antenna means, wherein each original data sequence forming the original data sequence is The write port side means for writing the data into the unit area in the storage means designated by the write address number, and the storage means according to the designation of the read address number generated according to the read rule corresponding to the encoding rule An encoding circuit, comprising: at least two read port side means for generating the encoded corresponding data sequence corresponding to the encoded data sequence by reading the original data from a unit area therein. 2. The encoding circuit according to claim 1, wherein the encoding rule requires that the data order be exchanged from the original data sequence within a predetermined interchange range in at least one encoded data sequence. , A data order changing means for changing the data order by making the read address number different from the write address number in the range of the number of bits corresponding to the change range from the least significant bit, An encoding circuit, wherein the reading of the original data is started at least at the time when the writing to the storage means is completed for at least the replacement range. 3. The encoding circuit according to claim 1, wherein the encoding rule requires that the polarity of the data is inverted according to a predetermined inversion pattern in at least one encoded data sequence. Connected to the read port of the input means, the polarity inverting means for inverting the polarity of the input data and outputting from the output terminal, the first input terminal connected to the read port of the storage means, and the second input terminal Selecting means for connecting to the output terminal of the polarity inverting means and for connecting the input terminal selected according to the selection control signal supplied to the control input terminal to the output terminal, and the selection control signal according to the inversion pattern An encoding circuit, comprising: polarity inversion control means for supplying to an input terminal. 4. The encoding according to claim 3, wherein the encoding rule requires that neither the data order nor the data polarity is reversed at a predetermined cycle in at least one encoded data sequence. In the circuit, the data order changing unit includes a first encoding stop unit that reads out the original data in the same order as in the original data series in each cycle, and the polarity inversion control unit in each cycle. An encoding circuit, comprising: a second encoding stop unit that supplies a selection control signal for selecting the first input terminal to the control input terminal. 5. The encoding circuit according to claim 1, wherein the transmission data rate of the encoded data sequence is changed by synchronizing a data rate designating signal designating the transmission data rate with a phase of the original data sequence. A write side data rate supply means for supplying the write port side means, and a read side data rate supply means for supplying the data rate designation signal to the read port side means in synchronization with the phase of the encoded data sequence. And an encoding circuit characterized by being capable of dynamically changing the transmission data rate.