JPH11196007A - Viterbi decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a Viterbi decoder which can fast perform high speed Viterbi decoding processing with small capacity of hardware. SOLUTION: A Viterbi decoder is provided with 2<n> pieces of ACS calculate means 504, and 2<n> pieces of path metric value are stored in an address space of each of path metric value memories 508 and 509. Then these path metric value are read out of the memory 508 (509). A path metric value register 502 holds plural sets of 2<n> pieces of path metric value, and a multiplexer 503 selects 2<n> pieces of path metric value. Then 2<n> pieces of means 504 simultaneously calculate the updated path metric value, based on those selected path metric value and the branch metric value. The calculated path metric value are written to the memory 509 (508). since 2<n> ACS calculations are carried out at the same time, Viterbi decoding processing can be performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a Viterbi decoder, and more particularly, to a Viterbi decoder for decoding convolutional codes at high speed by a plurality of ACS calculation units.

[0002]

2. Description of the Related Art A Viterbi decoder is used for a maximum likelihood decoding method of a convolutional code, and selects a code distance closest to a received code sequence from known code sequences as a maximum likelihood path. This is to obtain decoded data corresponding to the selected path. Because of its high correction capability, it is used as a decoder in a mobile communication system.

FIG. 6 is a partial schematic diagram of a conventional Viterbi decoder.
Shown in The path metric value memory 303 sequentially outputs path metric values according to the address of the address control unit 305. ACS (Adder-Comparator-Selector) calculation unit 301
Performs an ACS calculation from the path metric value and the branch metric value input from the path metric value memory 303 via the selector 304, and outputs an updated path metric value and a path select value. The updated path metric value is stored in the path metric value memory 306 via the selector 302 according to the address from the address control unit 305. The path select value is stored in the path select memory 307 according to the address from the address control unit 305. The above processing is sequentially performed, all the path metric values are read from the path metric value memory 303, and all the updated path metric values calculated by the ACS calculation unit 301 are written into the path metric value memory 306. The path metric value is read from the memory 306, and the updated path metric value is written to the path metric value 303. In the above configuration, since one ACS calculation unit performs the sequential processing, the processing time is doubled as the constraint length K increases.

In order to increase the speed of the Viterbi decoder, ACS is used.
A plurality of calculation circuits are provided to perform ACS calculation processing in parallel. As the high-speed Viterbi decoder, there are a type in which an ACS circuit is provided for the number of states (2 ^{K -1} ) for parallel processing, and an SST type Viterbi decoder using a predecoder. These high-speed Viterbi decoders cannot be realized with a large constraint length K because it is practically impossible to provide the ACS circuits by the number of states when the constraint length K increases. Therefore, although the speed is reduced, a plurality of ACs smaller than the number of states are provided to the Viterbi decoder.
An S circuit is provided to perform time-division parallel processing. As an example of such a Viterbi decoder, Japanese Patent Application Laid-Open No. 8-34
There is a Viterbi decoder disclosed in Japanese Patent No. 0262. In this method, a small number of ACS calculation circuits are provided in parallel to perform parallel ACS calculation processing, and two path metric memories are provided for each of the ACS calculation circuits so that read / write operations are alternately processed in a time-division manner. Things.

[0005]

The conventional Viterbi decoder having the configuration shown in FIG. 6 has a disadvantage that the processing time is doubled every time the constraint length K increases by one. Further, the conventional high-speed Viterbi decoder has an excessively large hardware scale and can be applied only to a code having a small constraint length K. Even in a conventional Viterbi decoder in which a plurality of ACS calculation circuits are provided and parallel processing is performed in a time-division manner, since the combination of the ACS calculation circuit and the path metric memory is not in an optimal relationship, the speed is higher than the circuit scale. Was not enough.

An object of the present invention is to provide a Viterbi decoder which includes a plurality of ACS calculation circuits and performs time-division parallel processing.
An object of the present invention is to provide a Viterbi decoder that performs high-speed Viterbi decoding processing with a small amount of hardware by optimizing an interface between a CS calculation circuit and a path metric memory.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method of calculating an updated path metric value from a path metric value and a branch metric value read from a path metric value memory. A path metric value memory for storing a plurality of path metric values for one address space, a path metric value register for temporarily storing a path metric value, a path metric value register, A multiplexer to select the value and multiple A
A plurality of ACS calculation means for performing CS calculation is provided.

With this configuration, a small A
High-speed Viterbi decoding can be performed by the CS calculation means and the path metric value memory.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides a path metric value memory for storing a path metric value, and a selector for selecting the path metric value read from the path metric value memory. , 2 ⁿ (n ≧ 1) ACS calculating means for calculating an updated path metric value from the branch metric value and the path metric value, a path select memory for storing a path select value,
In a Viterbi decoder comprising a timing control unit for controlling timing of each unit, and an address control unit for controlling the path metric value memory and the path select memory, the path metric value is stored in one address space of the path metric value memory. 2 ⁿ means for storing, a path metric value register for temporarily holding the path metric value read from the path metric value memory, and control of the path metric value held by the path metric value register from the address control unit. by the 2 ⁿ pieces selected output multiplexer, said provided a selector for the selection of the updated path-metric value synthesis from ACS calculating means, a Viterbi decoder simultaneously performing a plurality of ACS calculation with a small amount of hardware Enables high-speed Viterbi decoding It has the effect of making it possible.

The second aspect of the present invention is the first aspect.
The Viterbi decoder according to the above, further comprising an operation unit that performs the operation of the branch metric value from the received data, and selects and outputs the branch metric value under the control of the address control unit. This has the effect of enabling high-speed Viterbi decoding processing.

The third aspect of the present invention is the first aspect of the present invention.
In the above-described Viterbi decoder, a path select register that holds the path select value output from the ACS calculation means for one address space of the path select memory and outputs the path select value to the path select memory under the control of the timing control unit. This has the effect of simplifying the processing of the path select value and enabling high-speed Viterbi decoding processing.

The invention according to claim 4 of the present invention is the invention according to claim 1.
In the above-mentioned Viterbi decoder, an arithmetic unit for calculating the branch metric value from received data, selecting and outputting the branch metric value under the control of the address control unit, and the path output from the ACS calculation means. A path select register for holding a select value for one address space of the path select memory, and outputting the select value to the path select memory under the control of the timing control unit. This has the effect of enabling high-speed Viterbi decoding processing including processing.

The invention according to claim 5 of the present invention is the invention according to claim 4.
A mobile communication terminal device incorporating the above-described Viterbi decoder, and has an effect of enabling a small and highly reliable portable terminal device.

The invention according to claim 6 of the present invention is the invention according to claim 4.
A mobile communication base station device incorporating the above-described Viterbi decoder, and has an effect of enabling the base station to be small and highly reliable.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

(First Embodiment) In a first embodiment of the present invention, a plurality of path metric values are stored in one address space of a path metric value memory, and the path metric value is stored in a path metric value register. This is a Viterbi decoder that temporarily holds, separates a plurality of multiplexers, and simultaneously performs a plurality of ACS calculations.

FIG. 1 is a block diagram showing the configuration of the Viterbi decoder according to the first embodiment of the present invention. In FIG. 1, path metric value memories 508 and 509 are memories for storing 2 ⁿ (n ≧ 1) path metric values in one address space. The addresses of the path metric value memories 508 and 509 are 0 to {(2 ^(K-1) / ²ⁿ ) -1} (K is a constraint length and K-1 ≧ n). The selector 501 is a selector that selects the path metric value read from the path metric value memories 508 and 509. The path metric value register 502 is a register that holds the path metric value selected by the selector 501. Multiplexer 503
Is a multiplexer that separates 2 ⁿ path metric values held in the path metric value register 502 and selects and outputs 2 ⁿ .

The 2 ⁿ ACS calculating means 504 is an arithmetic circuit for simultaneously calculating an updated path metric value from the branch metric value and the path metric value output from the multiplexer 503. Selectors 506 and 507 are ACS calculating means.
A selector for combining and selecting 2 ⁿ updated path metric values from 504. The path select memory 511 is a memory that stores a path select value output by the ACS calculation unit 504. The address control unit 513 is a circuit that controls the path metric value memories 508 and 509, the path select memory 511, and the multiplexer 503. The timing control unit 514 is a circuit that controls the timing of each unit.

FIG. 2 is a timing chart of the Viterbi decoder according to the first embodiment, and shows the first part of one cycle of processing. In FIG. 2, M is 2 ^K−1 / 2 ^{n + 1}
Where K is a constraint length, n is a natural number satisfying K−1 ≧ n ≧ 1, L is an address value of the path select memory 511, and is determined according to the code length.

The operation of the Viterbi decoder according to the first embodiment will be described with reference to the block diagram of FIG. 1 and the timing chart shown in FIG. The path metric value memory 508 is
A combined path metric value of the address 00 specified by the path metric value memory address A202 from the address control unit 513 is output. The number of the combined path metric values is 2 ⁿ .

The selector 501 uses the switching signal 209 from the timing control unit 514 to determine the path metric value from the read path metric value memory from the path metric value from the read path metric value memory and the write path metric value memory. Select and output. In the present embodiment, when the switching signal 209 is “Hi”, the signal is read from the path metric value memory 508 and written to the path metric value memory 509. When the switching signal 209 is “Low”, it is read from the path metric value memory 509 and written to the path metric value memory 508. The path metric value selected by the selector 501 is held in the path metric value register 502 at the data holding timing 2031 from the timing control unit 514.

The path metric value memory 508 stores an address
Path metric value memory address A202 from control unit 513
, The combined address of the next specified address M
Output a metric value. Path metric value memory 50
The path metric value read from 8
Via the data control timing from the timing control unit 514.
Stored in the path metric value register 502
Is done. Path read from path metric value memory
The metric value is sequentially data retention timing 2031 to 2034
Is stored in the path metric value register 502 according to
You. Thus, the address 0 of the path metric value memory 508
4 × 2 stored in 0, M, 01, M + 1ⁿPassmet
Is stored in the path metric value register 502.
You. That is, in the path metric value register (1),
Status numbers 0 to (2ⁿ-1) Path metric value is retained
It is. The state number is stored in the path metric value register (2).
2^{K- Two}~ (2^K-2+2ⁿ-1) Path metric value is retained
Is done.

The multiplexer 503 separates the combined path metric value held in the path metric value register 502 and converts the path metric value to 2 ⁿ according to the path metric value memory address A202 from the address control unit 513.
The number is selected and output to 2 ⁿ ACS calculation means 504. That is, 2 ⁿ sets corresponding to branches input to the same state value are selected from 4 × 2 ⁿ path metric values, and 2 ⁿ sets are selected and output to the ACS calculation means 504. Multiplexer 503
Selects the path metric values of state numbers 0 and ^2K-2 and outputs them to the ACS calculation means (1) and (2). Select the state number 1 and the path metric value of (2 ^K-2 +1),
Output to ACS calculation means (3) and (4). Similarly, the path metric values of the state numbers (2 ⁿ⁻¹ −1) and (2 ^K−2 +2 ⁿ⁻¹ −1) are selected, and the ACS calculation means (2 ⁿ −
1) and (2 ⁿ ).

The ACS calculation means 504 calculates and outputs 2 ⁿ updated path metric values from the branch metric value 205 and the 2 ⁿ path metric values output from the multiplexer 503. The pass select value is output at the same time. That is, the ACS calculating means (1) calculates the updated path metric value of the state number 0, and the ACS calculating means (2)
Calculates the updated path metric value of state number 1, and similarly, the ACS calculating means (2 ⁿ ) calculates the state path number (2 ⁿ −
The updated path metric value of 1) is calculated and output.

The 2 ⁿ updated path metric values output from the ACS calculation means 504 are combined into one address space of the path metric value memory 509 by the selectors 506 and 507, respectively. The combined path metric value (hereinafter, the combined path metric value) is output only from the selector 507 connected to the write path metric value memory 509 by the switching signal 209 from the timing control unit 514. The combined path metric value from the selector 507 is stored in the address address 00 of the path metric value memory 509 specified by the path metric value memory address B207 from the address control unit 513.

The path select memory 511 stores the path select value at the designated address L in accordance with the path select memory address 208 from the address control unit 513.

By repeating the above operation, all the path metric values are read from the path metric value memory 508,
When the calculation of all the updated path metric values is completed and all the updated path metric values are written in the write path metric value memory 509, the read path metric value memory and the write path metric value memory are switched. Path metric value memory address A20
2 and the path metric value memory address B207 are the path metric value memory address B207 for reading and the path metric value memory address A202 for writing.
Switching between the read path metric value memory, the write path metric value memory, and the path metric value memory address is performed by a switching signal 209 from the timing control unit 514.

The operation after switching between the read path metric value memory and the write path metric value memory is as follows.
As described above, the synthesized path metric value is read from the read path metric value memory 509, the path metric value held in the path metric value register 502 is separated by the multiplexer 503, and 2 ⁿ values are selected. From the path metric value and the branch metric value output from the multiplexer 503 by the 2 ⁿ ACS calculating means 504, 2 ⁿ
Update path metric values are calculated simultaneously, and the selector 50
In steps 6 and 507, the operation of synthesizing 2 ⁿ updated path metric values into one address space of the path metric value memory and writing the result into the write path metric value memory 508 is repeated.

Since 2 ⁿ ACS calculation means are provided, when Viterbi decoding is performed on a convolutional code having a constraint length K, 2 ^K−1 / 2 ⁿ
One-bit decoding can be performed in one operation. Since the path metric value register is provided, the memory access time is effectively 0, and decoding can be performed only in the ACS calculation time. Since the path metric value memory has two surfaces, one for reading and the other for writing, the process of reading and writing the path metric value is simplified with a small amount of memory. Although the address control is slightly complicated, it is possible to use a two-port memory to configure the memory with one surface.

As described above, according to the first embodiment of the present invention, 2 ⁿ path metric values are stored in one address space of the path metric value memory, and the path metric value is stored in the path metric value register. temporarily hold, and separated by the multiplexer 2 ⁿ pieces selected by performing the 2 ⁿ ACS calculations simultaneously, it is Viterbi decoding at a high speed.

(Second Embodiment) A second embodiment of the present invention has a calculation unit for calculating a branch metric value from received data and selecting and outputting the same under the control of an address control unit. A plurality of path metric values are stored in one address space of the path metric value memory, and the path metric value is temporarily stored in the path metric value register.
Multiplexers are separated by a multiplexer, and multiple
It is a Viterbi decoder that performs CS calculation.

The second embodiment differs from the first embodiment in that an arithmetic unit for calculating a branch metric value from received data is provided.

FIG. 3 is a block diagram showing a configuration of the Viterbi decoder according to the second embodiment of the present invention. In FIG. 3, path metric value memories 708 and 709, a selector 701,
Path metric value register 702, multiplexer 703, A
CS calculation unit 704, selectors 706 and 707, path select memory 711, address control unit 713, timing control unit 714
Is not particularly different from the first embodiment. The arithmetic unit 712 is an arithmetic circuit that calculates a branch metric value from the received data, and selects and outputs it under the control of the address control unit 714.

The operation of the Viterbi decoder according to the second embodiment will be described with reference to the block diagram of FIG. Arithmetic unit 712
Calculates the branch metric value from the received data. Further, arithmetic section 712 selects and outputs a branch metric value according to the address signal from address control section 714.

The combined path metric value is read from the path metric value memory 708, the path metric value is selected by the selector 701, and the path metric value register 70 is selected.
2 and the multiplexer 703 separates the combined path metric values, selects 2 ⁿ path metric values,
The output to the 2 ⁿ ACS calculation means 704 is the same as in the first embodiment.

The ACS calculating means 704 calculates and outputs 2 ⁿ updated path metric values from the branch metric value 605 from the arithmetic unit 712 and the 2 ⁿ path metric values output from the multiplexer 703. The pass select value is output at the same time. The 2 ⁿ updated path metric values output from the ACS calculation means 704 are combined by selectors 706 and 707 into one address space of the path metric value memory.

The combined path metric value is output from the selector 707 and stored in the path metric value memory 709.
The path select memory 711 stores the path select value at the specified address according to the path select memory address 208 from the address control unit 713.

By repeating the above operation, all path metric values are read from the path metric value memory 708,
When the calculation of all the updated path metric values is completed and all the updated path metric values are written in the write path metric value memory 709, the read path metric value memory and the write path metric value memory are switched. Subsequent operations are the same as in the first embodiment.

Since the operation unit for calculating the branch metric is controlled by the timing control unit, it is easy to match the timing with the ACS calculation means, and the received data can be decoded quickly.

As described above, according to the second embodiment of the present invention, the arithmetic unit for calculating the branch metric value from the received data and selecting and outputting the same under the control of the address control unit is provided. 2 ⁿ path metric values are stored in one address space of the metric value memory, and the path metric value is temporarily stored in the path metric value register.
Separated by the multiplexer 2 ⁿ pieces selected, simultaneously the 2 ⁿ A
By performing the CS calculation, the Viterbi decoding process including the calculation of the branch metric value can be performed at high speed.

(Third Embodiment) In a third embodiment of the present invention, the path select value output from the ACS calculation means is held for one address space of the path select memory, and the control from the timing control unit is performed. The path metric value memory stores a plurality of path metric values in one address space, temporarily stores the path metric value in the path metric value register, and separates the path metric value by the multiplexer. This is a Viterbi decoder that selects one and performs a plurality of ACS calculations at the same time.

The Viterbi decoder of the third embodiment is different from the first and second embodiments in that it has a path select register.

FIG. 4 is a block diagram showing the configuration of the Viterbi decoder according to the third embodiment of the present invention. In FIG. 4, path metric value memories 808 and 809, selector 801,
Path metric value register 802, multiplexer 803, A
CS calculation means 804, selectors 806, 807, address control unit 8
13. The timing control unit 814 is not particularly different from the first embodiment. The path select value register 810
This register holds the path select value output from the ACS calculating means 804 for one address space of the path select memory.

The operation of the Viterbi decoder according to the third embodiment will be described with reference to the block diagram of FIG. Reads the path metric value from the path metric value memory 808, selects a path metric value in the selector 801, holds the path metric value register 802, to separate the path metric value 2 ⁿ pieces selected by the multiplexer 803, ^the 2 ⁿ The output to the ACS calculation means 804 is the same as in the first embodiment.

The ACS calculating means 804 calculates and outputs 2 ⁿ updated path metric values from the branch metric value 205 and the 2 ⁿ path metric values output from the multiplexer 803. The pass select value is output at the same time.
The path select value is stored in the path select value register 810 for one address space of the path select memory 811 and is output according to the path select value output timing from the timing control unit 814. The path select memory 811 stores the path select value at the specified address according to the path select memory address 208 from the address control unit 813. The 2 ⁿ updated path metric values output from the ACS calculation means 804 are combined into one address space of the path metric value memory by the selectors 806 and 807, respectively. The combined path metric value is output from the selector 807 and stored in the path metric value memory 809.

By repeating the above operation, all path metric values are read from the path metric value memory 808,
When the calculation of all the updated path metric values is completed and all the updated path metric values are written in the write path metric value memory 809, the read path metric value memory and the write path metric value memory are switched. Subsequent operations are the same as in the first embodiment.

Since the path select value register is provided, A
Since the path select value output from the CS calculating means can be written in the path select memory at a time, A
Timing adjustment between the CS calculation means and the path select memory is facilitated, and the writing time can be reduced.

As described above, according to the third embodiment of the present invention, the path select value output from the ACS calculating means is held for one address space of the path select memory, and is controlled by the timing control unit. A path select register for outputting to the path select memory is provided, 2 ⁿ path metric values are stored in one address space of the path metric value memory, the path metric value is temporarily stored in the path metric value register, and separated by the multiplexer. By selecting 2 ⁿ and simultaneously performing 2 ⁿ ACS calculations,
Viterbi decoding can be performed at high speed, including processing of the path select value.

(Fourth Embodiment) In a fourth embodiment of the present invention, an arithmetic unit for calculating a branch metric value from received data and selecting and outputting the same under the control of an address control unit; A path select register for holding the path select value output from the calculating means for one address space of the path select memory and outputting the path select value to the path select memory under the control of the timing control unit; This is a Viterbi decoder which stores a plurality of path metric values, temporarily stores the path metric values in a path metric value register, separates them by a multiplexer, selects a plurality of them, and performs a plurality of ACS calculations at the same time.

The Viterbi decoder according to the fourth embodiment uses the first
The third embodiment differs from the first to third embodiments in that it includes both an operation unit for calculating a branch metric value and a path select register.

FIG. 5 is a block diagram showing the configuration of the Viterbi decoder according to the fourth embodiment of the present invention. In FIG. 5, the path metric value memories 108 and 109, the selector 101,
Path metric value register 102, multiplexer 103, A
CS calculation means 104, selectors 106 and 107, path select memory 111, address control unit 113, timing control unit 114
Is not particularly different from the first embodiment. The path select value register 110 is a register that holds the path select value output from the ACS calculation means 104 for one address space of the path select memory. The operation unit 112 is an operation circuit that calculates a branch metric value from the received data, and selects and outputs a branch metric value under the control of the address control unit 114.

The operation of the Viterbi decoder according to the fourth embodiment will be described with reference to the block diagram of FIG. Arithmetic unit 112
Calculates the branch metric value from the received data. Further, the operation unit 112 selects and outputs a branch metric value according to the address signal from the address control unit 114.

[0053] from the path metric value memory 108 reads the path metric value, the selector 101 selects the path metric value, held in the path metric value register 102, a multiplexer 103, 2 ⁿ pieces by separating the path metric value The selection and output to the 2 ⁿ ACS calculation means 104 are the same as in the first embodiment.

The ACS calculation means 104 calculates and outputs 2 ⁿ updated path metric values from the branch metric value 205 from the operation unit 112 and the 2 ⁿ path metric values output from the multiplexer 103. The pass select value is output at the same time. The path select value is stored in the path select value register 110 for one address space of the path select memory 111, and is output according to the path select value output timing from the timing control unit 114.

The path select memory 111 stores a path select value at a designated address according to the path select memory address 208 from the address control unit 113. A
The 2 ⁿ updated path metric values output from the CS calculation means 104 are combined by selectors 106 and 107 into one address space of the path metric value memory. The combined path metric value is output from the selector 107 and stored in the path metric value memory 109.

By repeating the above operation, all the path metric values are read from the path metric value memory 108,
When the calculation of all the updated path metric values is completed and all the updated path metric values are written in the write path metric value memory 109, the read path metric value memory and the write path metric value memory are switched. Subsequent operations are the same as in the first embodiment.

As described above, according to the fourth embodiment of the present invention, the operation of the branch metric value is performed from the received data, and the operation unit for selecting and outputting the operation is controlled by the address control unit. path select values output by one address space worth retaining the path select memory from the device, provided with a path select register for outputting the path select memory under control of the timing controller, 2 ⁿ to 1 the address space of the path metric value memory Path metric values are stored, the path metric value is temporarily stored in the path metric value register, and separated by the multiplexer.
^By selecting ⁿ pieces and performing 2 ⁿ ACS calculations at the same time, Viterbi decoding can be performed at high speed, including calculation of branch metric values and processing of path select values.

[0058]

As described above, according to the present invention, the Viterbi decoder stores a plurality of path metric values in one address space of the path metric value memory, and stores the path metric value read from the path metric value memory. The metric value is held in the path metric value register, the ACS calculation is performed simultaneously by the plurality of ACS calculation means, and the plurality of updated path metric values are selected and combined by the selector, so that the Viterbi decoding process can be performed at a high speed with a small amount of hardware. The effect that it can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a Viterbi decoder according to a first embodiment of the present invention;

FIG. 2 is a timing chart of the Viterbi decoder according to the first embodiment of the present invention;

FIG. 3 is a block diagram of a Viterbi decoder according to a second embodiment of the present invention;

FIG. 4 is a block diagram of a Viterbi decoder according to a third embodiment of the present invention;

FIG. 5 is a block diagram of a Viterbi decoder according to a fourth embodiment of the present invention;

FIG. 6 is a block diagram schematically showing a conventional Viterbi decoder.

[Explanation of symbols]

 101, 106, 107 Selector 102 Path metric value register 103 Multiplexer 104 ACS calculation means 108, 109 Path metric value memory 110 Path select value register 111 Path select memory 112 Operation unit 113 Address control unit 114 Timing control unit 201 Master clock 202 Path metric Value memory address A 203 Data holding timing 204 Path metric value register 205 Branch metric value 206 Output of ACS calculating means 207 Path metric value memory address B 208 Path select memory address 209 Switching signal 301 ACS calculator 302, 304 Selector 303, 306 Path metric Value memory 305 Address control unit 307 Path select memory 501, 506, 507 Selector 502 Path metric value register 503 Multiplexer 504 ACS calculation means 508, 509 Path metric value memory 511 Path select memory 513 Address control unit 514 Timing control unit 701, 706, 707 Selector 702 Path metric value register 703 Multiplexer 704 ACS calculation means 708, 709 Path metric value memory 711 Path select memory 712 Operation unit 713 Address control unit 714 Timing control unit 801, 806, 807 Selector 802 Path metric value register 803 Multiplexer 804 ACS calculation means 808, 809 Path metric value memory 810 Path select value register 811 Path select memory 813 Address control unit 814 Timing control unit

Claims (6)

[Claims] A path metric value memory for storing a path metric value; a selector for selecting the path metric value read from the path metric value memory;
2 ⁿ (n ≧ 1) ACSs for calculating an updated path metric value from a branch metric value and the path metric value
Calculation means, a path select memory for storing a path select value, a timing control unit for controlling the timing of each unit, and a Viterbi decoder comprising an address control unit for controlling the path metric value memory and the path select memory, Means for storing 2 ⁿ path metric values in one address space of the path metric value memory; a path metric value register for temporarily storing the path metric value read from the path metric value memory; A multiplexer for selecting and outputting 2 ⁿ pieces of the path metric values held by the address control unit under control of the address control unit, and a selector for selecting and combining the updated path metric values from the ACS calculation means. Vita characterized by performing an ACS calculation Bi-decoder. 2. The Viterbi decoder according to claim 1, further comprising an arithmetic unit for calculating the branch metric value from the received data, and selecting and outputting the branch metric value under the control of the address control unit. vessel. 3. A path select register which holds the path select value output from the ACS calculating means for one address space of the path select memory and outputs the path select value to the path select memory under the control of the timing control unit. The Viterbi decoder according to claim 1, comprising: 4. An arithmetic unit for calculating the branch metric value from received data, selecting and outputting the branch metric value under the control of the address control unit, and the path select value output from the ACS calculation means. 2. The Viterbi decoder according to claim 1, further comprising: a path select register that holds the data for one address space of the path select memory and outputs the same to the path select memory under the control of the timing control unit. 5. A mobile communication terminal device incorporating the Viterbi decoder according to claim 4. 6. A mobile communication base station device comprising the Viterbi decoder according to claim 4.