JP2001332980A - Device and method for interleave - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform block interleave, using memory capacity for one interleave. SOLUTION: This interleaver performs block interleave for a unit of m×n data. The interleaver sets logical addresses from 0 to (m×n-1) to an interleave memory and writes i-th data of the next super frame to the logical address, where i-th data of a certain interleave block are read out. The interleaver calculates the logical address of i-th data to be outputted from a k-th interleave block, on the basis of a function fk(i)=f(fk-1(i)).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interleave apparatus and an interleave method for performing block interleave on a data sequence.

[0002]

2. Description of the Related Art An interleaver and a deinterleaver will be described.

When transmitting digital signals, Bit Error
In order to secure Rate (hereinafter BER) characteristics, an error correction coding process is usually performed on a signal to be transmitted. As a method of such error correction processing, a method called a concatenated code that uses a combination of a plurality of error correction codes is known.

FIG. 19 is a conceptual diagram for explaining the connection code.

[0005] On the transmitting side, the concatenated code is encoded with an encoding system A for an information sequence, and further encoded with another encoding system B for transmission. On the receiving side, an information sequence is obtained by first decoding the received sequence using a decoding system corresponding to the encoding system B, and further decoding the received sequence using a decoding system corresponding to the encoding system A. By using such a concatenated code, B is superior to the case where any one error correction method is used.
ER characteristics can be obtained.

For example, in the case of BS digital broadcasting, etc., FIG.
As shown in the figure, on the transmitting side, first, Re
It is encoded by an ed-Solomon encoder, and further encoded by a convolutional encoder. Then, on the receiving side, the received sequence is decoded by a convolutional code using, for example, a Viterbi decoder, and then decoded by a Reed-Solomon decoder to obtain an information sequence.

When Viterbi decoding is performed on a convolutional code, erroneous correction (hereinafter, burst error) tends to occur continuously in a data sequence having a low code-to-noise ratio (hereinafter, CNR).

Therefore, in a data transmission system such as a BS digital broadcast, for example, as shown in FIG. 21, an interleaver is provided between an RS encoder and a convolutional encoder.
Further, a deinterleaver is provided between the Viterbi decoder and the RS decoder.

Here, the interleaver is a device for rearranging an input sequence according to a certain rule, and the deinterleaver is a device for rearranging an input sequence according to a rule reverse to that of the interleaver. Thus, by providing an interleaver and a deinterleaver, as shown in FIG.
Burst errors generated by performing Viterbi decoding are dispersed to improve error correction capability.

The logical operation of a general interleaver and deinterleaver will be described. Note that the interleaver and the deinterleaver have the same operation of rearranging an input sequence according to a certain rule, except that the rules for rearranging data are reversed. Therefore, only the operation of the interleaver will be described here. The interleaver is roughly classified into two types, a block interleaver and a convolutional interleaver, according to the data rearrangement rule. Here, the interleaver divides the data stream into blocks each having a fixed number of data groups, Only the operation of the block interleaver for which processing has been completed will be described. Hereinafter, when simply referred to as an interleaver, it refers to a block interleaver.

The interleaver uses a data array composed of m rows × n columns, and performs data rearrangement by changing the order of writing and reading data with respect to this data array. it can.
This m × n data array is hereinafter referred to as an interleaved block or simply a block.

The interleaver first arranges a one-dimensional data input sequence in the row direction as shown in FIG. 23 (a), and forms an m × n two-dimensional data array on a memory. I do. Subsequently, as shown in FIG. 23B, data is sequentially read from the memory from the data array in the column direction from the memory, and a one-dimensional data output sequence is transmitted.

For example, when an input sequence of 0, 1, 2, 3, 4, 5,... Is given to an interleaver using 2 × 3 blocks, as shown in FIG. Are written on the memory. On the other hand, at the time of reading, as shown in FIG. 24B, the interleaver reads data from the memory in the column direction from the 2 × 3 data array, and reads 0, 3, 1, 4,
The output sequence of 2, 5,... Is transmitted.

The above is the logical operation of the interleaver. By using such an interleaver, BS
In a data transmission system such as digital broadcasting, a burst error caused by Viterbi decoding or the like can be converted into a random error.

In the above-described interleaver, the input of the data of the next block is performed after the output of all the data for one block is completed, and the interleaver performs a complete operation for each block. Therefore, data input / output to / from this interleaver is input / output from / to the memory intermittently in block units. However, depending on the application, it may be necessary to continuously input and output data to and from the interleaver.

As an interleaver which can meet such a demand, an interleaver employing a so-called double buffer system is known. FIG. 25 shows a schematic circuit configuration of a double buffer type interleaver.

The double-buffer interleaver has 1
A configuration including two memories each having a data capacity of a block, and an input selector and an output selector for switching input / output signals (for example, write data, write address, read data, read address, and control signal) for these two memories. Is done.

The input selector and the output selector switch the memory to be selected each time one block is processed. The input selector and the output selector always select different memories. For example, when processing the k-th block in the order of input to the interleaver, if the input selector selects memory A, the output selector selects memory B. When processing the (k + 1) -th block, the memory to be selected is switched, and the input selector selects the memory B and the output selector selects the memory A. The input data is written to the memory selected by the input selector, and the output data is read from the memory selected by the output selector. Therefore, data is always input to one of the memories, and data is always output from the other memory. Therefore, in the double buffer type interleaver, the interleave processing can be performed while continuously inputting and outputting data.

[0019]

By the way, in order to perform block interleaving, the above-mentioned double buffer type interleaver must be applied, and the memory capacity for interleaving requires twice the capacity of the interleaving block. Had been done. Therefore, when the interleaver is integrated, the cost of the memory for the interleave becomes very large.

The present invention has been made in view of such circumstances, and has as its object to provide an interleave apparatus and an interleave method capable of reducing the capacity of a memory used for interleave and deinterleave. I do.

[0021]

An interleave apparatus according to the present invention is an interleave apparatus for performing block interleave in a unit of an interleave block consisting of m × n data. An interleave memory in which a logical address is set and capable of storing data for one interleave block; and a memory controller for writing input data to the interleave memory and reading data written in the interleave memory according to a predetermined interleave rule. The memory control unit calculates the logical address of the i-th output data of the k-th interleaved block as a function f _k (i) = f (f _k−1
(I)), and writing the i-th input data of the (k + 1) -th interleaved block to the same address as the logical address.

Here, f (i) = n × (i% m) + (i
/ M), and f _k (i) has the following relationship with f (i). f ₂ (i) = f (f (i)) f ₃ (i) = f (f ₂ (i)) f ₄ (i) = f (f ₃ (i)) f _k-1 (i ) = F (f _k−2 (i)) f _k (i) = f (f _k−1 (i)) where m and n are integers of 1 or more, and (x% y) means that x is y
, And (x / y) represents an integer part of a quotient obtained by dividing x by y.

Also, an interleave device according to the present invention
Is an f (i) generating circuit for calculating f (i), and 0- (m
× n-1) are set, and the table
Array in order of cable address $ f_k-1(I) No. storing 格納
1 and a table from 0 to (m × n-1)
Address is set, and array $ f
_k(I) a second table for storing｝, and f
_k-1By calculating (f (i)), the k-th IN
The logical address of the data output at the ith
Dress is f_kWith memory control for calculating (i)
You.

Further, the interleave device according to the present invention comprises an f (i) generation circuit for calculating f (i), and 0 to (m).
× n-1) table address until the set {(and a third table for storing _{i) f k-1},} f (f k -1 (i) arranged in order of the table address) A look-up control unit is provided for calculating f _k (i), which is a logical address of the i-th output data of the k-th interleaved block, by performing an operation.

Further, the interleave device according to the present invention comprises an f (i) generating circuit for calculating f (i), and g (i)
G (i) for calculating = i% (mn) + i / (mn)
A generation circuit, a first register storing f _k (i−1), and a second register storing f _k (1); g
By calculating (f _k (i−1) + f _k (1)),
The memory control unit is provided for calculating f _k (i) which is a logical address of data output at the i-th of the k-th interleave block.

The interleaving method according to the present invention uses m ×
An interleaving method for performing block interleaving in units of interleaved blocks of n data, wherein a logical address of 0 to (m × n-1) is set in the interleave memory, and input data is interleaved by the interleave memory. When the data written in the interleave memory is read in accordance with a predetermined interleave rule, the logical address of the i-th output data of the k-th interleave block is changed to a function f _k (i) =
It is characterized by calculating based on f (f _k-1 (i)) and writing the i-th input data of the (k + 1) -th interleaved block to the same address as the logical address.

Here, f (i) = n × (i% m) + (i
/ M), and f _k (i) has the following relationship with f (i). f ₂ (i) = f (f (i)) f ₃ (i) = f (f ₂ (i)) f ₄ (i) = f (f ₃ (i)) f _k-1 (i ) = F (f _k−2 (i)) f _k (i) = f (f _k−1 (i)) where m and n are integers of 1 or more, and (x% y) means that x is y
, And (x / y) represents an integer part of a quotient obtained by dividing x by y.

The interleave method according to the present invention calculates f _{k -1} (f (i)) to obtain a logical address f _k (i) of the i-th output data of the k-th interleave block. i) is calculated.

Further, the interleave method according to the present invention calculates f (f _k−1 (i)) to obtain f _k (i.e., the logical address of the i-th output data of the k-th interleave block). i) is calculated.

Further, the interleaving method according to the present invention calculates the logical address of the i-th output data of the k-th interleaved block by calculating g (f _k (i−1) + f _k (1)). F _k (i) is calculated.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an interleaver to which the present invention is applied will be described as an embodiment of the present invention.

The operating principle First interleaver, before describing the specific interleaver, the operating principle of the interleaver used in the interleaver, so as to correspond to the operation of the interleaver for interleaving a block of m × n, generally Give an explanation.

First, generalize the rules between the input and output blocks for the m × n block interleaver. The input block _{{DI 0, DI 1, DI} 2, ·
_{·· DI i, ··· DI mn-} 2, DI mn-1 and}, the output block _{{DO 0, DO 1, DO} 2, ··· DO i, ···
DO _mn−2 , DO _mn−1 }, the rule between the input block and the output block is DO _i = D as shown in FIG.
It is represented by _{If (i)} .

Here, i indicates a position of an arbitrary data in the block. This i is 0 ≦ i ≦ (m × n−
It is an integer value in the range of 1). The data position in the block is hereinafter referred to as an index. Also,
f (i) = n × (i% m) + (i / m) m,
n indicates a natural number. m indicates the depth of interleaving. a% b indicates the remainder of dividing a by b. a /
b indicates a quotient (an integer part) obtained by dividing a by b.

The interleaver according to the embodiment of the present invention performs the following operation based on the relationship between the input block and the output block (that is, the interleave rule).

The interleaver has a function of m ×, as shown in FIG.
It has an interleave memory capable of storing n data. The interleave memory has # 0 to # 0 for each cell.
A logical address of # (n × m−1) is assigned.

Data is continuously input to such an interleaver in the order of indexes. The interleaver
The input data is continuously stored in the memory, and the data is continuously output from the memory while replacing the data in accordance with the above-described interleaving rule.

Here, when reading certain data, the interleaver specifies one logical address and reads the data from the specified logical address. At that time, the interleaver simultaneously writes the next data to the read logical address. That is, the interleaver performs read and write simultaneously by specifying the same address. The data to be written at this time is data of a block next to the block being read, and is data having the same index as the index of the data being read.

Specifically, as shown in FIG. 3, the interleaver reads out the data of the index i of the k-th interleaved block for the logical address x and also reads the data of the index i of the (k + 1) -th interleaved block. Write it. Here, k is a natural number, and indicates the input number (or output order) of the block input (or output) to the interleaver.

The logical address for the data at an arbitrary index i in an arbitrary interleaved block is
It is calculated based on the following equation. f _k (i) = f (f _k−1 (i)) Here, f (i) is n × (i% m) + (i / m). This f (i) is a function used to indicate the relationship between the input and output blocks of the block interleaver described above.
F _k (i) has the following relationship with f (i). f ₂ (i) = f (f (i)) f ₃ (i) = f (f ₂ (i)) f ₄ (i) = f (f ₃ (i)) f _k-1 (i ) = F (f _k−2 (i)) f _k (i) = f (f _k−1 (i))

As described above, the interleaver to which the present invention is applied has a function f representing the interleave rule of the input / output block.
Based on (i) and the logical address for the interleave memory obtained in the past, the logical address where the data to be output at the i-th position of the k-th block is stored. Then, the interleaver accesses the logical address, reads out the data to be output at the i-th of the stored k-th block, and
Stores data input to the i-th block of the (+1) th block.

The operation of such an interleaver will be specifically described in block order as follows.

The logical address is # in the interleave memory.
0 to # (mn-1), and it is assumed that valid data does not exist in each address in the initial state. Also, the number of data in the interleaved block is m ×
n.

The data of the first block is input in the order of the index. The interleaver writes the data input in the order of the index in the order of the logical addresses of the interleave memory. That is, the i-th input data is written to the logical address #i.

Subsequently, the interleaver performs an operation of writing the data of the second block into the interleave memory while reading the data of the first block. The data to be output at the i-th position in the first block is f (i) = n × (i
% M) + (i / m) th data. F (i) of the first block = n × (i% m) + (i / m)
The data that has been input the first time has been written to logical address #f (i). Therefore, the interleaver converts the data at the index i of the first block to the logical address #f.
Read from (i). At the same time, the interleaver writes the i-th input data of the second block to this logical address #f (i).

Next, the interleaver performs an operation of writing the data of the third block into the interleave memory while reading the data of the second block. As in the previous case, the data to be output at the i-th position in the second block is f (i)
= N × (i% m) + (i / m) th input data. Here, the i-th input data in the second block has been written to the logical address #f (i) in the previous operation. Therefore, the interleaver converts the data at the index i of the second block to the logical address #f (f (i)).
Read from At the same time, the interleaver
The data input to the i-th block is written to this logical address #f (f (i)). Note that this f (f
(I)) is hereinafter described as f ₂ (i).

Similarly, when the interleaver writes the data of the fourth block to the interleave memory while reading the data of the third block, the data of the index i of the third block is written in the logical address #f (f (f (f
(I))), and at the same time, the data input to the i-th block of the fourth block is stored in the logical address #f (f
(F (i))). Note that this f (f (f
(I))) is hereinafter described as f ₃ (i).

In general, when writing the data of the (k + 1) th block to the memory while reading the data of the kth block, the data of the index i of the kth block is written into the logical address #f _k (i) , And at the same time, the i-th input data of the (k + 1) th block is written to the logical address #f _k (i).

More specifically, 0, 1, 2, 3, 4, and 4 are added to the interleaver for performing 2 × 3 block interleaving.
The case of inputting data such as 5, 6, 7,... Will be described with reference to FIG.

As shown in FIG. 4A, it is assumed that logical addresses from # 0 to # 5 are assigned to the interleave memory.

First, as shown in FIG. 4B, the interleaver converts the first block (0, 1, 2, 3, 4, 5) into
Writing is performed in the order of the logical address.

Subsequently, the interleaver reads the first block and writes the second block (6, 7, 8, 9, 10, 11) as shown in FIG. 4 (c).
At this time, the reading order of the first block is f (i) = 3
× (i% 2) + (i / 2), the order of access to the interleave memory is as shown by the dotted line in the figure.
The order is # 0 → # 3 → # 1 → # 4 → # 2 → # 5. Therefore, when data 1 of address # 0 is read, data 6 is written to address # 0, and when data 3 of address # 3 is read, address 6 is read.
When data 7 is written to address # 1 and data 1 at address # 1 is read, data 8
Is written, and when data 4 of address # 4 is read, data 9 is written to address # 4. When data 2 of address # 2 is read, this address # 4 is read.
When data 10 is written to address 2 and data 5 at address # 6 is read, data 11 is written to address # 6.

Subsequently, the interleaver reads the second block and writes the third block (12, 13, 14, 15, 16, 17) as shown in FIG. 4D. At this time, the reading order of the second block is f ₂
According to (i), the access order to the interleave memory is # 0 → # 4 → # 3 →
The order is # 2 → # 1 → # 5. Therefore, when data 6 at address # 0 is read, data 12 is written to address # 0, and when data 9 at address # 4 is read, data 1 is written to address # 4.
When data 3 is written and data 7 at address # 3 is read, data 14 is written to address # 3. When data 10 at address # 2 is read, data 15 is written to address # 2. When data 8 of address # 1 is read, data 16 is written to address # 1 and data 1 of address # 6 is read.
When 1 is read, data 1
7 is written.

The f (i) and f ₂ (i) used above are used.
The specific values of are shown in FIG.

As described above, in the interleaver according to the embodiment of the present invention, when reading out the i-th data of the k-th block, the read address is calculated based on f _k (i). With a memory having a data capacity for a block, interleaving can be performed while continuously inputting and outputting data.

Note that the interleaver and the deinterleaver are:
The operation of rearranging the input sequence according to a certain rule is the same, except that the rules for rearranging the data are reversed.
The above processing can be applied to a deinterleaver.

(Configuration and Operation of Interleaver)
A specific configuration of the interleaver will be described.

The interleaver 1 comprises an address generation circuit 11 and an interleave memory 12, as shown in FIG.

The address generation circuit 11 generates a read / write address (real address) for the interleave memory 14. The address generation circuit 11 stores data to be output at the i-th block of the k-th block based on the function f (i) representing the interleaving rule for the above-described interleaved block and the logical address for the interleaved memory obtained in the past. The read / write address is calculated. The interleave memory 12 reads out and outputs the data to be output at the i-th position of the k-th block with respect to the address, and at the same time, k +
Write the i-th input data of the first block.

The interleaver 1 having such a configuration operates based on a timing pulse generated inside the address generation circuit 11. The address generation circuit 11 generates a read / write address for accessing the interleave memory 12 at each internally generated timing.

(Configuration and Operation of Address Generation Circuit) Next, the address generation circuit 11 will be described in more detail.

The address generation circuit 11 calculates the logical address f _k (i) for the interleave memory 12 using the relationship f _k (i) = f _k-1 (f (i)). I have.

Specifically, an array A ｛f _k (i) ｛0 ≦ i
<M × n} memory array and array B {f
f _k (i) is calculated using a memory table for storing _k−1 (i) と and an arithmetic circuit for calculating f (i).
In these two memory tables, addresses from 0 to (m × n−1) are set. This address specifies the arrangement order of each data constituting the array.
The data group constituting the array A and the array B is i ｛0 ≦ i <
m × n}.

(K) When outputting a logical address for the i-th data in the block, first, f (i) is calculated, and this f (i) is supplied as an address of a memory table for storing array B, The value is read from the array B. Then, the value read from the array B is written to the address i of the memory table storing the array A. Then, the value stored at the address i of the array A becomes the i-th logical address of the (k) -th block. Subsequently, when processing for the next block is performed, the value of array A may be substituted for array B as it is and updated. For example, the memory table storing the array B and the memory table storing the array A may be replaced for each block.

From the viewpoint that the access order to the array B according to the index order simplifies the circuit scale, the value of the array A is not directly substituted into the array B and updated, but the array A ｛f _k ( f ^-1 (i))} to array B
May be updated. f ^-1 (i) is
This is the inverse function of f (i).

Specifically, FIG. 7 shows a circuit configuration of the address generation circuit 11 capable of performing such an operation.

As shown in FIG. 7, the address generation circuit 11 includes a timing control section 21 and a flag D generation circuit 2.
2, a flag E generating circuit 23, an index counter 24, a first address table 25, a second address table 26, an f '(i) generating circuit 27, a first selector 28, It has a second selector 29, a third selector 30, a fourth selector 31, a fifth selector 32, and a logical address / real address conversion circuit 34.

The timing control section 21 generates a timing pulse serving as an operation clock of the entire address generation circuit 11. Further, the timing control unit 21 generates and outputs a start signal which is an instruction to start an interleave operation synchronized with the timing pulse and a block start position signal indicating a start position of the interleave block.

The flag D generation circuit 22 is a circuit that generates a flag D indicating 0 or 1. Flag D
The start signal from the timing control unit 21 is supplied to the generation circuit 22. The start signal is a command issued when the operation of the address generation circuit 11 starts or when the address generation circuit 11 is restarted, and is issued from an external system controller or the like. Flag D generation circuit 2
2, when the flag D is initialized to 0 by the start signal and the data processing of the first interleaved block after reset is completed (that is, after the start signal,
At the time when the block start position signal indicating the block start position is received twice), the flag D is set to 1. And
Thereafter, the flag D is kept at 1 until the processing is stopped.

The flag E generating circuit 23 is a circuit for generating a flag E indicating 0 or 1. Flag E
The generation circuit 23 is supplied with a block start position signal. The flag E generation circuit 26 initializes the flag E to 0 according to the block start position signal. The flag E
The generation circuit 26 inverts the value of the flag E every time a pulse indicating the block start position is received.

The index counter 24 increments the timing pulse supplied from the timing control section 21 to generate an index value i. The index value i is initialized to 0 when the start signal and the block start position signal are supplied. The index counter 24 stores the index value i in the f '(i) generating circuit 27 and the first and second address tables 25,
26.

The first address table 25 and the second address table 26 are tables capable of storing block address data for one interleave block. First address table 25 and second address table 25
In the address table 26, table addresses from # 0 to # (m × n-1) are set in the internal cells, respectively. First address table 25 and second address table 25
By designating this address to the address table 26, data can be written and read to and from the table address. Further, the first address table 25 and the second address table 26 are provided with an output terminal ODT, an input terminal IDT, and an address terminal ADR.

An index i output from the index counter 24 is input to the f '(i) generating circuit 27. f '(i) is a circuit for calculating the above-mentioned f' (i) for the input index value i. As shown in FIG. 8, a specific circuit configuration is as follows: a remainder circuit 41 for calculating the remainder of m with respect to an input index i; a multiplication circuit 42 for multiplying the output of the remainder circuit 41 by n; The quotient when i is divided by m (integer value)
, And an addition circuit 44 that adds the output of the multiplication circuit 42 and the output of the division circuit 43.

The first selector 28 switches between the output from the first address table 25 and the output from the second address table 26 according to the flag E, and selects one of the output data. And the second selector 29
Output to If the flag E is 0, the first selector 28 selects the first address table 25, and the flag E
Is 1, the second address table 26 is selected.

The second selector 29 switches between the output from the index counter 24 and the output from the first selector 28 in accordance with the flag D, selects one of the output data and outputs the logical address / real data. Output to the address conversion circuit 34. The second selector 29 sets the flag D to 0
If so, the index counter 24 is selected and the flag D
Is 1, the first selector 28 is selected.

The third selector 30 switches the output of the f '(i) generating circuit 27 and the output of the increment counter 23 in accordance with the flag E, selects the output data from one of them, and 1 address table 25
Output to the address terminal. The third selector 30 selects the index counter 24 when the flag E is 0, and selects the f ′ (i) generating circuit 27 when the flag E is 1.

The fourth selector 31 switches between the output of the f '(i) generating circuit 27 and the output of the increment counter 23 in accordance with the flag E, selects the output data from one of them, and 2 address table 26
Output to the address terminal. The fourth selector 31 selects the f '(i) generating circuit 27 if the flag E is 0,
If the flag E is 1, the index counter 24 is selected.

The fifth selector 32 switches the first address table 25 or the second address table 26 in accordance with the flag E, and switches one of the input terminals IDT from the second selector 29 to the other. Input the output of When the flag E is 0, the fifth selector 32 selects the second address table 26, and when the flag E is 1
In this case, the first address table 25 is selected.

Logical address / real address conversion circuit 34
Converts the value output from the second selector 29 into a real address supplied to the interleave memory 12 from the logical address fk (i).

Next, the operation of outputting the logical address and the operation of updating the address table of the address generation circuit 11 having such a configuration will be described.

When the flag D is 0 (in the case of processing for the first interleaved block), the second selector 29 selects the index counter 24, and the index value i output from the index counter 24 is output as a logical address as it is. You.

If the flag D is 1 and the flag E is 0 (in the case of processing for the second and subsequent interleaved blocks), the third selector 30
And the index value i output from the index counter 24 is given as the table address of the first address table 25. Then, the first selector 28 selects the first address table 25, and the data stored at the address specified by the table address (index value i) given from the index counter 24 is output as a logical address. Is done.

When the flag D is 1 and the flag E is 1 (in the case of processing for the second and subsequent interleaved blocks), the fourth selector 31
And the index value i output from the index counter 24 is given as the table address of the second address table 26. Then, the first selector 28 selects the second address table 26, and the data stored at the address specified by the table address (index value i) given from the index counter 24 is output as a logical address. Is done.

When the flag E is 0, the fifth selector 32 selects the second address table 26, and
The logical address output from the selector 29 is stored in the second address table 26. That is, the logical address value output from the first address table 25 is stored in the second address table 26. At this time, the storage address of the input data is the fourth address.
Selector 31 selects the f '(i) generation circuit 27, and is designated by the value output from the f' (i) generation circuit 27.

When the flag E is 1, the fifth selector 32
Selects the first address table 25, and the logical address value output from the second selector 29 is stored in the first address table 25. That is, the logical address value output from the second address table 26 is
It is stored in the first address table 25. At this time, since the third selector 30 selects the f '(i) generating circuit 27, the storage address of the input data is specified by the value output from the f' (i) generating circuit 27. You.

By performing such an operation, the address is
In the address generation circuit 11, the array A ｛f _k(I) ｛0 ≦ i <
address table for storing m × n} and array B
｛F_k-1(I) an address table for storing｝;
An arithmetic circuit for generating the number f ′ (i) is prepared, and f
_k-1(F (i)) to calculate the k-th interleave block
Logical address of the data output at the i-th
f_k(I) can be calculated.

Next, the operation of the address generation circuit 11 will be described with reference to the timing chart of FIG.

The timing chart shown in FIG. 9 shows an example in which the present invention is applied to a 2 × 3 block interleaver.

FIG. 9A shows a block start position signal,
(B) is an index value i output from the index counter 24, (c) is a flag D, (d) is a flag E,
(E) is an output value of the first address table 25,
(F) is the output value of the second address table 26,
(G) is an output logical address value, (h) is an address value input to the first address table 25, (i)
Indicates address values input to the second address table.

The address generation circuit 11 starts operating in response to a start signal, and performs processing based on a timing pulse.

The index counter 24 increments the timing pulse and updates the index value i. The index value i is initialized to 0 at the generation timing of the block start position signal. That is, in the case of a 2 × 3 block, counting from 0 to 5 is initialized to 0 next.

The flag D is set high only for the first block immediately after the start, and is set low thereafter. The flag E is alternately high and low for each block.
Is switched.

The logical address output indicates that the flag D is high.
In the first block, the value becomes the index value i. Thereafter, the logical address is output when the flag E is
ow, the first address table 25
When the flag E is high, the output value of the second address table 26 is obtained. When the flag E is low, the address value given to the first address table 25 is the index value i.
When the flag E is high, it is set to f '(i). The address value given to the second address table is an index value i when the flag E is high, and f '(i) when the flag E is low.
It is said.

As described above, according to the interleaver 1 to which the present invention is applied, block interleaving can be performed using one interleave memory for one interleave block, and the memory capacity can be reduced.

Next, a modification of the address generation circuit 11 in the interleaver 1 will be described. In the following description of the first to third modified examples, the same components used in the address generation circuit 11 shown in FIG. Description is omitted.

(First Modification) The address generation circuit of the first modification calculates the logical address f _k (i) for the interleave memory 12 by f _k (i) = f (f _k−1).
(I)).

Specifically, the array C ｛f _k-1 (i) ｛0
A memory table for storing ≦ i <m × n}, and f
F _k (i) is calculated using an arithmetic circuit for calculating (i). In this memory table, addresses from 0 to (m × n−1) are set. This address specifies the arrangement order of each data constituting the array. The data group constituting the array A and the array B is i ｛0 ≦
i <m × n}.

When outputting the logical address for the i-th data in the k-th block, the index i is supplied as the address of the memory table storing the array C, and the value is read from the array C. Then, the read value is supplied to the arithmetic circuit, and f (f _k-1 (i)) is calculated. The value calculated by this arithmetic circuit is output as a logical address. Then, the value calculated by the arithmetic circuit is stored at the address i of the memory table, and is used for processing of the next block.

FIG. 10 shows an address generation circuit 80 according to a first modification capable of performing such an operation.

As shown in FIG. 10, the address generation circuit 80 includes a timing control section 21, a flag D generation circuit 22, an index counter 24, an address table 81, an f (i) generation circuit 82, It has a second selector 29 and a logical address / real address conversion circuit 34.

The address table 81 is a table capable of storing data of a block address for one interleave block. In the address table 81, a table address from # 0 to # (n × m-1) is set in each of the internal cells, and by specifying this address, data corresponding to a predetermined table address is set. Can be written and read. The address table 81 has an output terminal ODT, an input terminal IDT, and an address terminal AD.
R is provided. The index value i from the index counter 24 is input to the input terminal IDT. The input terminal IDT has an f (i) generation circuit 8
2 is input. Output terminal O
DT is connected to the second selector 29.

The f (i) generating circuit 82 calculates the index value i output from the index counter 24 with respect to the index value i.
This is a circuit for calculating f (i) described above. As shown in FIG. 11, a specific circuit configuration is as follows: a remainder circuit 83 for calculating the remainder of n with respect to the input index i; a multiplication circuit 84 for multiplying the output of the remainder circuit 83 by m; It comprises a division circuit 85 for calculating a quotient (integer value) when i is divided by m, and an addition circuit 86 for adding the output of the multiplication circuit 84 and the output of the division circuit 85.

The second selector 29 switches between the output from the index counter 24 and the output from the address table 81 in accordance with the flag D, selects one of the output data, and selects the logical address / real address. Output to the conversion circuit 34. The second selector 29 sets the flag D
Is 0, the index counter 24 is selected, and if the flag D is 1, the address table 81 is selected.

Next, the operation of outputting the block address and the operation of updating the address table of the address generation circuit 80 according to the first modification of the above configuration will be described.

If the flag D is 0 (in the case of processing for the first interleaved block), the second selector 29 selects the index counter 24, and the index value i output from the index counter 24 is output as a logical address as it is. You. Index counter 2
F (i) generating circuit 8 at the address specified by the table address (index value i) given from
The values output from 2 are stored.

When the flag D is 0 (in the case of processing for the second and subsequent interleaved blocks), the second selector 29 selects the address table 81. Then, the data stored at the address specified by the table address (index value i) given from the index counter 24 is output as a logical address. At the same time, the value output from the f (i) generation circuit 82 is stored in the table address from which the data is output.

By performing the above operation, the address generation circuit 80 of the first modification stores the array C {f _k-1 (i)} in the memory table 81, and stores the i-th block in the k-th block. When processing the th data, this array C
Is output as a logical address, and the array C is updated with f (C {f _k-1 (i)}).

Next, the operation of the address generation circuit 80 of the first modification will be described with reference to the timing chart of FIG. The timing chart shown in FIG. 12 shows an example in which the present invention is applied to a 2 × 3 block interleaver.

In FIG. 12, (a) is a block start position signal, (b) is an index value i output from the index counter 24, (c) is a flag D, (d) is an output value of the address table 81, (E) shows the output logical address value, and (f) shows the value generated from the f (i) generation circuit 82.

The address generation circuit 11 starts operating in response to a start signal, and performs processing based on a timing pulse.

The index counter 24 increments the timing pulse and updates the index value i. The index value i is initialized to 0 at the generation timing of the block start position signal. That is, in the case of a 2 × 3 block, counting from 0 to 5 is initialized to 0 next.

The flag D is set high only for the first block immediately after the start, and is set low thereafter.

The logical address output indicates that the flag D is high.
In the first block, the value becomes the index value i. Thereafter, the logical address output becomes the output value of the address table 81. The address value given to the address table 81 is determined by the f (i) generation circuit 82
Is the value generated from.

(Second Modification) The address generation circuit according to the second modification uses "f _k (i) = g (f _k ) between f _k (i) and f _k (i-1). Using the relationship (i−1) + f _k (1) ″, f _k (i), which is a logical address for the interleave memory 12, is calculated. Here, g (i) = i% (m N) + i / (m · n), and f _k (0) = 0.

More specifically, an address register (cur) for storing the value of f _k (i-1), an offset register (offset) for storing f _k (1), and a circuit for calculating g (i) And a circuit for calculating f (i),
f _k (i) is calculated. The operation algorithm is as follows.

[0116] Note that Y ← X indicates that the value of the X register is substituted into the Y register.

Specifically, FIG. 13 shows an address generation circuit 90 according to a second modification capable of realizing such an algorithm.

As shown in FIG. 13, the address generation circuit 90 includes a timing control section 21, a D flip-flop 91, an address register 92, an offset register 93, an addition circuit 94, and a g (i) generation circuit. 95,
An f (i) generation circuit 96, a selector 99, and a logical address / real address conversion circuit 34 are provided.

The address register 92 has an input terminal ID
T, output terminal Q, enable terminal EN, clear terminal CL
R and a reset terminal RST are provided. The address register 92 inputs the timing pulse generated by the timing control circuit 21 to the enable terminal EN,
When the timing pulse is supplied, the data input to the input terminal IDT is received and held for one clock, and the held data is output from the output terminal Q. The input data is supplied from the g (i) generation circuit 95. The output data is supplied to the logical address / real address conversion circuit 34 and the addition circuit 94 as a logical address. Further, the block start position signal generated by the timing control circuit 21 is input to the CLR terminal of the address register 92. When the block start position signal is supplied to the clear terminal CLR, the held data is cleared. A start signal from the timing control circuit 21 is supplied to the address register 92 by a reset terminal R.
Input to ST. When a start signal is supplied to the reset terminal RST, the held data is reset.

The offset register 93 has an input terminal D, an output terminal Q, an enable terminal EN, and a reset terminal R.
ST is provided. When the block start position signal generated by the timing control circuit 21 is input to the enable terminal EN and the block start position signal is supplied, the offset register 93 receives the input terminal IDT.
Receives the input data, holds the data, and outputs the held data. The input data is supplied from the selector 99. The output data is supplied to the addition circuit 94 and the f (i) generation circuit 96. Further, a start signal from the timing control circuit 21 is input to the offset terminal 93 to the reset terminal RST. When a start signal is supplied to the reset terminal RST, the held data is reset.

The addition circuit 94 adds the output of the address register 92 and the output of the offset register 93.

The g (i) generating circuit 95 applies the above-mentioned g (i) = i% (m ·
n) + i / (m · n). The specific circuit configuration is as shown in FIG.
Circuit 101 for calculating the remainder of (m · m) with respect to
A division circuit 102 for calculating a quotient (integer value) obtained by dividing the added value i by (nm), and a remainder circuit 10
1 and an adder 103 for adding the output of the divider 102. The value calculated by the g (i) generation circuit 95 is supplied to the input terminal IDT of the address register 92.

The f (i) generating circuit 96 applies the above-mentioned f (i) to the value output from the offset counter 93.
Is a circuit for calculating. The specific circuit configuration is the same as the circuit configuration shown in FIG. This f (i) generating circuit 9
The value calculated by 6 is supplied to the selector 99.

The value 1 and the output value of the f (i) generating circuit 96 are input to the selector 99. The selector 99 responds to the flag D output from the flag D generation circuit 22 by
Either the value 1 or the output value of the f (i) generating circuit 96 is supplied as input data to the offset register 93. Note that the flag D generation circuit 22 initializes the flag D to 0 by the start signal, and completes the processing of the data of the first interleaved block after the reset (that is, after the start signal, the block start position indicating the block start position). At the time when the position signal is received twice), the flag D is set to 1. Thereafter, this flag D is kept at 1 until the processing is stopped. Selector 99
Supplies the value 1 to the offset register 93 when the flag D is 0, and supplies the output value of the f (i) generating circuit 96 to the offset register 93 when the flag D is 1.

A timing pulse is input to the D flip-flop 91, and this timing pulse is delayed by one clock to generate an enable signal of output data.
Output.

The operation of each register will be described below.

Address register 92 operates as follows. (1) When the start signal is supplied, the value stored inside is always cleared to 0. (2) The value stored inside is cleared to 0 at the start timing of the interleave block. (3) The value of the interleave block is cleared. The g (i) generation circuit 95 at a timing other than the beginning
, And updates the value stored therein. The offset register 93 operates as follows. (1) When a start signal is supplied, the internally stored value is set to 1. (2) At the start timing of the interleave block, f
(I) The output value from the generation circuit 96 is input and the value stored inside is updated.

Next, the operation of the address generation circuit 90 of the second modification will be described with reference to the timing chart of FIG. The timing chart shown in FIG. 15 shows an example in which the present invention is applied to a 2 × 3 block interleaver.

In FIG. 15, (a) is a block start position signal, (b) is an index value i, (c) is a flag D,
(D) shows the output logical address value, and (e) shows the offset value output from the offset register 96.

The address generation circuit 90 starts operating in response to a start signal, and performs processing based on a timing pulse. The index value i is initialized to 0 at the generation timing of the block start position signal. That is, in the case of a 2 × 3 block, counting from 0 to 5 is initialized to 0 next.

The flag D is set high only for the first block immediately after the start, and is set low thereafter.

The logical address output indicates that the flag D is high.
In the first block, the value becomes the index value i. Thereafter, the logical address output becomes the output value of the address register 92. Also, the offset register 9
The address value given to 6 is a value generated from the f (i) generation circuit 82.

(Third Modification) A third modification is an address generation circuit provided with a reset function for resetting the value of a generated logical address every fixed block cycle.

The address generation circuit 11 shown in FIG.
0, and the address generation circuit 9 of the second modification shown in FIG.
0, when writing the first interleave block after the start of operation to the interleave memory 12, the index i
Is output as a logical address as it is. That is, i is given as the initial value of the logical address. Here, each address generation circuit outputs f _k (i) as a logical address for the k-th interleaved block, and this f _k (i) has a constant periodicity.
That is, the case where f _k (i) = i appears periodically. In the third modification, the number of processed interleaved blocks is counted, and when the count value reaches a fixed value, the logical address is forcibly reset to an initial value. By resetting the logical address that is forcibly generated at regular intervals in this way to an initial value, for example, an error occurs for some reason during signal processing, and an accurate logical address can be calculated. Even in the case of disappearance, the error propagation can be prevented from continuing for more than the period.

An outline of the proof that the function f _k (i) has periodicity will be described.

First, the function f _k (i) has the following two properties. (1) i, j, such that f _k (i) = f _k (j) (i ≠ j)
k does not exist.

It is clear from the fact that the data will be overwritten in the interleave processing if it exists. (2) There are k, l, and i such that f _k (i) = f _l (i). Since the domain and range of fk and fl are finite, be sure to use f _k
There are k, l, and i such that (i) = _fl (i).

According to (1), j ≦ i (when j = f _k (i) holds) is directed with 0 ≦ i, j <m × n as a node.
It can be said that there is no merging path in the directed graph as branch. According to (2), the directed graph
It can be seen that the directed branch in always forms a finite number of closed loops.

From the above, it can be said that f _k (i) has a periodicity whose cycle is the least common multiple of the number of elements of each closed loop.

Next, an example of an algorithm for obtaining the period p will be described. (Step S1) Prepare a table T of size m × n,
Reset so that T [i] = i. (Step S2) k ← 1 (Step S3) for (i = 0; i <m; i ++) T
(I) = f (T [i]); (Step S4) If T [i] = i for all i, if k is not at the required period p ₀ , then k ← k + 1 and (Step S3) Return to).

Steps S1 to S4 as described above
By performing the processing up to, the period p is obtained. Another example of the algorithm for obtaining the period p will be described. (Step S11) A table T of size m × n is prepared, and all entries are reset to 0. (Step S12) Prepare a size m × n table L,
Reset all entries to 1. (Step S13) k ← 0; (Step S14) The minimum i (0 where T [i] == 0
≦ i <m × n), the following processing is performed. (Step S15) T [i] ← 1 (Step S16) i ← f (i) (Step S17) k ++ (Step S18) If T [i] == 0, step S1
5, if T [i] == 1, L [i] == k and the process returns to step S13. (Step S19) The least common multiple of L [i] when T [i] == 1 is obtained for all i (0 ≦ i <m × n). This least common multiple is the period p.

FIGS. 16 to 18 show circuit configuration examples to which such a reset function is specifically applied.

FIG. 16 is an example of a circuit in which the address generation circuit 11 shown in FIG. 7 has a reset function. in this case,
There is provided a cycle counter 110 for counting a pulse indicating the start position of the interleave block for one cycle. And
The pulse output from the cycle counter 110 is supplied to the flag D generation circuit 22. Flag D generation circuit 22
Sets the flag D to 1 when a pulse is supplied from the cycle counter 110. By working this way,
In each cycle, the index value i output from the index counter 24 by the second selector 29 is output as a logical address as it is. By outputting the index value i as a logical address as it is, it is possible to cause each circuit to perform the same operation as that at the time of starting thereafter.

FIG. 17 is a circuit example in which the address generation circuit 80 of the first modification shown in FIG. 10 is provided with a reset function.

In this case, similarly, a cycle counter 110 for counting a pulse indicating the start position of the interleave block for one cycle is provided. And this cycle counter 11
The pulse output from 0 is supplied to the flag D generation circuit 22. The flag D generation circuit 22 includes a period counter 110
, The flag D is set to 1. By doing so, the index value i output from the index counter 24 by the second selector 29 is output as a logical address as it is for each cycle.
By outputting the index value i as a logical address as it is, it is possible to cause each circuit to perform the same operation as that at the time of starting thereafter.

FIG. 18 is a circuit example in which a reset function is provided in the address generation circuit 90 of the second modification shown in FIG.

In this case, a cycle counter 1 for counting the pulse indicating the start position of the interleave block for one cycle.
10 is provided. At the timing when the pulse is output from the period counter 110, the bare address register 9
2 and the offset register 93 are controlled as follows.

[0148] By doing so, the index value i output from the index counter 24 by the second selector 29 is output as a logical address as it is for each cycle. By outputting the index value i as a logical address as it is, it is possible to cause each circuit to perform the same operation as that at the time of starting thereafter.

[0149]

According to the interleave apparatus and the interleave method of the present invention, the i-th interleave block of the k-th interleave block is based on the address where the data arranged at the i-th place of the (k-1) -th interleave block is stored. The address of the data to be read is calculated, and from the calculated address, the i-th data of the k-th interleaved block output is read, and the i-th data of the (k + 1) -th interleaved block is calculated. Write.

As a result, in the present invention, the interleave memory used when performing interleaving can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an interleaving rule in a block interleaver.

FIG. 2 is a diagram for describing a logical address assigned to an interleave memory capable of storing m × n data;

FIG. 3 is a diagram for explaining that data reading and writing are simultaneously performed on one logical address;

FIG. 4 is a diagram for explaining an operation of an interleaver that performs 2 × 3 block interleaving;

FIG. 5 is a diagram showing addresses used when performing the above 2 × 3 block interleaving.

FIG. 6 is a configuration diagram of an interleaver.

FIG. 7 is a configuration diagram of an address generation circuit.

FIG. 8 is a configuration diagram of an f ⁻¹ (i) generation circuit.

FIG. 9 is a timing chart showing an operation of the address generation circuit. .

FIG. 10 is a configuration diagram of an address generation circuit according to a first modified example.

FIG. 11 is a configuration diagram of an f (i) generation circuit.

FIG. 12 is a timing chart showing an operation of the address generation circuit according to the first modification.

FIG. 13 is a configuration diagram of an address generation circuit according to a second modification.

FIG. 14 is a configuration diagram of a g (i) generation circuit.

FIG. 15 is a timing chart showing the operation of the address generation circuit according to the second modification.

FIG. 16 is a configuration diagram of an address generation circuit according to a third modification in which a reset function is provided in the address generation circuit shown in FIG. 7;

FIG. 17 is a configuration diagram of an address generation circuit according to a third modification in which a reset function is provided in the address generation circuit according to the first modification shown in FIG. 10;

FIG. 18 is a configuration diagram of an address generation circuit according to a third modification in which a reset function is provided in the address generation circuit according to the first modification shown in FIG. 10;

FIG. 19 is a conceptual diagram for describing a connection code.

FIG. 20 is a diagram for explaining an error correction process used in digital satellite broadcasting.

FIG. 21 is a diagram for describing an interleaver used in digital satellite broadcasting.

FIG. 22 is a diagram for describing dispersion of a berth error by an interleaver.

FIG. 23 is a diagram for describing an access order to an interleave memory.

FIG. 24 is a diagram for describing an access order of an interleaver using 2 × 3 blocks to an interleave memory.

FIG. 25 is a configuration diagram of an interleaver of a double buffer system.

[Explanation of symbols]

1 interleaver, 11, 80, 90 address generation circuit, 12 input buffer, 13 dummy data selector, 14 interleave memory

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5B001 AB02 AC05 AD06 AE04 5J065 AA03 AB01 AC02 AE06 AF03 AG06 AH02 AH03 AH04 AH06 AH17 5K014 AA01 BA00 FA16 GA02

Claims (14)

[Claims] 1. Interleave consisting of m × n data
Interleaving that performs block interleaving on a block-by-block basis
In the slave device, logical addresses from 0 to (m × n-1) are set, and 1
An interleaver that can store data for interleaved blocks
Write the input data to the above interleave memory
Only the data written in the interleave memory
Control unit that reads data according to a predetermined interleave rule
And the memory control unit is configured to output the i-th data of the k-th interleaved block.
Data logical address to function f_k(I) = f (f
_k-1(I)), and calculate the same
I-th address of the (k + 1) -th interleaved block
Writing data to be input to the interface
Leave equipment. Here, f (i) = n × (i% m) + (i
/ M), and f (i) is given by f _k(I)
It has such a relationship. f_Two(I) = f (f (i)) f_Three(I) = f (f_Two(I)) f_Four(I) = f (f_Three(I)) ・ ・ ・ f_k-1(I) = f (f_k-2(I)) f_k(I) = f (f_k-1(I)) Further, m and n are integers of 1 or more, and (x% y)
represents the remainder of dividing x by y, and (x / y) means x is converted by y
Represents the integer part of the quotient divided. 2. The memory control unit according to claim 1, wherein an f (i) generating circuit for calculating f (i) and a table address from 0 to (m × n−1) are set. _k-1 (i)} and a second table storing an array {f _k (i)} in which table addresses from 0 to (m × n-1) are set and the table addresses are arranged in the above-mentioned table address order. Calculating f _k (i), which is the logical address of the i-th output data of the k-th interleaved block, by calculating f _k-1 (f (i)) The interleaving device according to claim 1, wherein: 3. The memory control section is configured to set an f (i) generation circuit for calculating f (i), a table address from 0 to (m × n−1), and to arrange an array {f _k-1 (i)}, and calculating f (f _k-1 (i)) to calculate the logic of the i-th output data of the k-th interleaved block. 2. The interleave device according to claim 1, wherein the address f _k (i) is calculated. 4. The memory control unit includes: an f (i) generating circuit for calculating f (i); and a g (i) = i% (mn) + i / (mn) for calculating g (i). i) having a generating circuit, a first register for storing f _k (i-1), and a second register for storing f _k (1); g (f _k (i-1) + f _k 2. The interleave apparatus according to claim 1, wherein (1)) is calculated to calculate f _k (i), which is a logical address of the i-th output data of the k-th interleave block. 5. The interleave apparatus according to claim 1, wherein an initial value of a logical address input to the interleave memory is set at the i-th of the first interleave block. 6. The interleave apparatus according to claim 5, wherein a logical address input to the ith interleave memory of the first interleave block is i. 7. The interleave device according to claim 5, wherein the logical address is reset to the initial value for each fixed number of interleave blocks. 8. Interleaving consisting of m × n data
Interleaving that performs block interleaving on a block-by-block basis
In the interleaving method, 0 to (m × n-1) is stored in the interleave memory.
Logical address is set, and the input data is written to the interleave memory.
Data written in the interleave memory
When reading in accordance with the interleaving rule, the data output at the i-th of the k-th interleaved block
Data logical address to function f_k(I) = f (f
_k-1(I)), and calculate the same
I-th address of the (k + 1) -th interleaved block
Writing data to be input to the interface
Leave method. Here, f (i) = n × (i% m) + (i
/ M), and f (i) is given by f _k(I)
It has such a relationship. f_Two(I) = f (f (i)) f_Three(I) = f (f_Two(I)) f_Four(I) = f (f_Three(I)) ・ ・ ・ f_k-1(I) = f (f_k-2(I)) f_k(I) = f (f_k-1(I)) Further, m and n are integers of 1 or more, and (x% y)
represents the remainder of dividing x by y, and (x / y) means x is converted by y
Represents the integer part of the quotient divided. 9. A method of calculating f _k-1 (f (i)) to calculate f _k (i), which is a logical address of the i-th output data of the k-th interleaved block. The interleaving method according to claim 8, wherein 10. A method of calculating f (f _k−1 (i)) to calculate f _k (i), which is a logical address of data output at the i-th of the k-th interleave block. The interleaving method according to claim 8, wherein 11. By calculating g (f _k (i−1) + f _k (1)), i of the k-th interleaved block is calculated.
F which is the logical address of the data to be output
9. The interleaving method according to claim 8, wherein _k (i) is calculated. 12. The interleaving method according to claim 8, wherein an initial value of a logical address for data input to the i-th interleave memory of the first interleave block is set. 13. The logical address input to the ith interleave memory of the first interleave block is represented by i
13. The interleaving method according to claim 12, wherein: 14. For each of a fixed number of interleaved blocks,
13. The interleaving method according to claim 12, wherein a logical address is reset to the initial value.