JP2003037118A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor which has a positive threshold voltage and low parasitic resistances by controlling the threshold voltage of the nitride compound semiconductor field effect transistor. SOLUTION: In the regions between a source electrode 17 and a gate electrode 110 and between a drain electrode 18 and the gate electrode 110, insulation layers 111, 112 accompanied with a compressive stress are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an n-type field effect transistor made of a nitride-based compound semiconductor material which is excellent in withstand voltage characteristics and high frequency power characteristics, and particularly realizes a positive threshold voltage and a small parasitic resistance. The present invention relates to an n-type field effect transistor.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter referred to as FET = Field) made of a conventional nitride compound semiconductor material.
Effect Transistor). FIG. 5 is an explanatory diagram showing a first typical structure of a conventional FET. On a sapphire (0001) substrate 50, AlN (40
nm) buffer layer 51, GaN (3 μm) channel layer 52, and Al _0.25 Ga _0.75 N (3 nm) spacer layer 5
3. Al _0.25 Ga _0.75 doped with a predetermined concentration of Si _donor
An N (8 nm) carrier supply layer 54 and a GaN (4 nm) Schottky layer 55 are sequentially epitaxially grown (for example, MOCVD or RF MBE) to form a semiconductor multilayer structure 56.

In this multilayer structure, due to the difference in the lattice constants of Al _0.25 Ga _0.75 N and GaN in the thermal equilibrium state,
Al _0.25 Ga _0.75 N spacer layer 53 and carrier supply layer 5
An extensible strain is generated during 4. Due to the piezoelectric effect of Al _0.25 Ga _0.75 N, the same strain causes Al _0.25 Ga
Positive charges are induced at the interface between the _0.75 N spacer layer 53 and the GaN channel layer 52. Also, Al _0.25 Ga _0.75 N and Ga
A positive charge is induced at the same interface due to the difference in spontaneous polarization of N. Further, the _donor in the Al _0.25 Ga _0.75 N carrier supply layer 54 becomes an ion having a positive charge.

A two-dimensional electron gas having a function of neutralizing these positive charges is formed in the channel layer 52 near the interface with the spacer layer 53. On the surface of the semiconductor multi-layer structure thus manufactured, ohmic contact regions of the source electrode 57 and the drain electrode 58 are formed of, for example, Ti / Al, and are electrically connected to the two-dimensional electron gas formed in the channel layer 52. It is connected to the. Further, for example, WSiN / Au is sequentially deposited on the surface of the Schottky layer 55 to form the gate electrode 510.

FIG. 6 is an explanatory view showing a second typical structure of a conventional FET. Sapphire (0001) substrate 60
A buffer layer 61 of AlN (40 nm) and GaN (3 μ
m) of the channel layer 62 is sequentially epitaxially grown (for example, MOCVD or RF MBE) to form a semiconductor multilayer structure 66. A portion of the surface of the channel layer 62 having a predetermined thickness is doped with Si donor having a predetermined concentration. In the present multilayer structure, the donor in the channel layer 62 becomes an ion having a positive charge.

An electron gas having a function of neutralizing this positive charge is formed in the channel layer 62. On the surface of the channel layer 62, donors that have become positive ions exist, but electron gas does not exist, and a Schottky barrier is formed by the surface depletion layer. On the surface of the semiconductor multilayer structure thus manufactured, ohmic contact regions of the source electrode 67 and the drain electrode 68 are formed by, for example, Ti / Al or the like, and are electrically connected to the electron gas formed in the channel layer 62. Has been done.

Further, for example, WS is formed on the surface of the channel layer 62.
A gate electrode 610 is formed by sequentially depositing iN / Au. In the FET having this structure, the thickness of the depletion layer in the channel layer is changed by changing the gate voltage applied to the gate electrode, and the drain current is modulated.

In any of the above-mentioned two conventional structures, electron gas exists in the channel layer immediately below the gate electrode without applying a bias voltage to the gate electrode, and the electric potential is electrically generated between the source electrode and the drain electrode. Conduct. It is necessary to apply a negative voltage to the gate electrode in order to cut off electrical conduction between the source electrode and the drain electrode. That is, each of the above-described conventional structures is a normally-on type transistor having a negative threshold voltage.

On the other hand, from the viewpoint of circuit design, when the bias voltage is not applied to the gate electrode, the source electrode and the drain electrode are not electrically connected to each other. It is essential to realize a transistor having a characteristic that electrical conduction occurs between drain electrodes, that is, a normally-off type transistor having a positive threshold voltage.

As a means for realizing a normally-off type transistor having a positive threshold voltage within the above-mentioned conventional structure, for example, in the first conventional structure, a spacer is formed when the semiconductor multilayer structure 56 is formed. The AlN composition of the layer 53 and the carrier supply layer 54 (0.25 in the first conventional structure) is reduced to reduce the tensile strain generated in these layers, and the spacer layer 53 and the GaN channel layer are formed by the piezoelectric effect. A method of reducing the amount of positive charges induced at the interface of 52, a method of reducing the doping concentration of the donor in the carrier supply layer 54, or a method of forming a semiconductor immediately below the gate electrode 510 before forming the gate electrode 510. A method of locally etching the multilayer structure 56 or a combination of these methods is possible.

In the second conventional structure, when the semiconductor multilayer structure 66 is formed, the portion of the surface of the channel layer 62 that is doped with Si donor is thinned, or the doping concentration of the donor is reduced. Before the gate electrode 610 is formed or the gate electrode 610 is formed, the semiconductor multilayer structure 66 in the region directly under the gate electrode 610 is locally etched, and S on the surface side of the channel layer 62 in only that region is locally etched.
A method of thinning a portion where i-dona is doped, or a combination of these methods is considered.

However, these methods have the following problems. Si is used when forming a semiconductor multilayer structure.
In the method of controlling the thickness of the layer containing the donor concentration, the donor concentration thereof, or the AlN composition of the spacer layer and the barrier layer in the first conventional structure, the bias voltage is not applied to the gate electrode. There is no electron gas in the channel layer immediately below the gate electrode, but almost no electron gas exists in the channel layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

Therefore, the parasitic resistance increases remarkably and it is impossible to realize excellent transistor operation. Further, in the method of locally etching the semiconductor multilayer structure immediately below the gate electrode before forming the gate electrode, the electron gas concentration in the portion of the channel layer adjacent to the region immediately below the gate electrode is kept high. Although the parasitic resistance does not increase, it is impossible to accurately control the etching depth, and thus it is impossible to manufacture a transistor having uniform characteristics.

[0014]

As described above, conventionally, it is difficult to accurately realize a normally-off type transistor made of a nitride compound semiconductor material, having a small parasitic resistance and a positive threshold voltage. It was The present invention is to solve such a problem, and provides a transistor made of a normally-off type nitride compound semiconductor material having a small parasitic resistance and a positive threshold voltage with good reproducibility and controllability. The purpose is to

[0015]

In order to achieve such an object, the field effect transistor according to claim 1 of the present invention has a buffer layer 11 and a channel layer on a substrate 10, as shown in FIG. A semiconductor multilayer structure 16 is formed by sequentially depositing 12, a spacer layer 13, a carrier supply layer 14, and a Schottky layer 15, and a source electrode 17, a drain electrode 18, and a gate electrode 110 are formed on the surface of the semiconductor multilayer structure 16. In a field effect transistor which is used, a semiconductor multilayer structure 16 between a source electrode and a gate electrode is provided.
It is characterized in that the insulating layers 111 and 112 accompanied by compressive stress are formed with a shape covering the entire surface and the entire surface of the semiconductor multilayer structure 16 between the drain electrode and the gate electrode.

The field effect transistor according to claim 2 of the present invention has a buffer layer 21, a channel layer 22, a spacer layer 23, a carrier supply layer 24 and a Schottky layer on a substrate 20, as illustrated in FIG. In a field effect transistor in which a semiconductor multilayer structure 26 is formed by sequentially depositing 25, and a source electrode 27 and a drain electrode 28 are formed on the surface of the semiconductor multilayer structure 26, A barrier layer 29 accompanied by compressive stress is formed between drain electrodes, a gate electrode 210 is locally formed on the barrier layer 29, and the entire surface of the barrier layer 219 between the source electrode and the gate electrode and the drain are formed. The insulating layer 211 having a compressive stress with a shape covering the entire surface of the barrier layer 29 between the electrode and the gate electrode.
And 212 are formed.

In the field effect transistor according to claim 3 of the present invention, as shown in FIG. 3, the semiconductor multilayer structure 36 is formed by sequentially depositing the buffer layer 31 and the channel layer 32 on the substrate 30. The source electrode 37,
In the field effect transistor in which the drain electrode 38 and the gate electrode 310 are formed on the surface of the semiconductor multilayer structure 36, in the semiconductor multilayer structure 3 between the source electrode and the gate electrode.
6 is characterized in that insulating layers 311 and 312 with compressive stress are formed with a shape that covers the entire surface and the entire surface of the semiconductor multilayer structure 36 between the drain electrode and the gate electrode. .

Furthermore, in the field effect transistor according to claim 4 of the present invention, as illustrated in FIG. 4, a semiconductor multilayer structure 46 is formed by sequentially depositing a buffer layer 41 and a channel layer 42 on a substrate 40. The source electrode 47,
In the field effect transistor in which the drain electrode 48 is formed on the surface of the semiconductor multilayer structure 46, a barrier layer 49 accompanied by compressive stress is formed between the source electrode and the drain electrode on the surface of the semiconductor multilayer structure 46, and the barrier layer is formed. A gate electrode 410 is locally formed on the surface of the barrier layer 49 to cover the entire surface of the barrier layer 49 between the source electrode and the gate electrode and the entire surface of the barrier layer 49 between the drain electrode and the gate electrode. Layers 411 and 41 with stress
2 is formed.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A field effect transistor according to the present invention comprises an insulating layer having compressive stress on the surface of a semiconductor multilayer structure, the entire surface of the semiconductor multilayer structure between a source electrode and a gate electrode, and a drain electrode / gate electrode. Deposition is performed with a shape that covers the entire surface of the semiconductor multilayer structure in between. The region directly below the insulating layer of the semiconductor multilayer structure is accompanied by tensile strain as a reaction of stress in the insulating layer, whereas the region immediately below the gate electrode is accompanied by compressive strain.

Due to the effect of compressive strain generated in the region immediately below the gate electrode of the semiconductor multi-layer structure, the threshold voltage of the transistor is changed in the positive direction by the piezoelectric effect as compared with the case without the insulating layer. By controlling the stress generated in the insulating layer and the thickness of the insulating layer to generate a predetermined strain in the semiconductor multilayer structure, a transistor having a desired positive threshold voltage is realized. Further, due to the tensile strain generated in the region immediately below the insulating layer, the electron concentration in the channel layer in this region increases due to the piezoelectric effect.

Since the boundary between the region with the tensile strain and the region with the compressive strain in the semiconductor multilayer structure coincides with the boundary between the gate electrode and the insulating layer, the electron concentration in the channel layer is high. The region is formed in self-alignment with the gate electrode. Therefore, the present invention realizes a field effect transistor in which the parasitic resistance due to the region is suppressed. Furthermore, since it is possible to control the stress of the insulating layer and the thickness of the insulating layer with high accuracy and reproducibility,
A field effect transistor having the above characteristics is provided with good reproducibility and controllability.

[0022]

Embodiments of the present invention will be described with reference to the drawings. [Embodiment 1] FIG. 1 is an explanatory view showing a first embodiment of the present invention. In the figure, sapphire (0001)
AlN (40 nm) buffer layer 11 on the substrate 10, Ga
N (3 μm) channel layer 12, Al _0.25 Ga _0.75 N (3
nm) spacer layer 13 and Al _0.25 Ga _0.75 N (8 nm) carrier supply layer 1 doped with a predetermined concentration of Si donor.
4, GaN (4 nm) Schottky layer 15 is sequentially epitaxially grown (for example, MOCVD or RF MBE).
Etc.), and the semiconductor multilayer structure 16 is formed.

Ohmic contact regions of the source electrode 17 and the drain electrode 18 are formed on the surface of the multi-layer structure thus manufactured, for example, by locally depositing Ti / Al and heat-treating, and the channel layer 12 is formed. It is electrically connected to the formed two-dimensional electron gas. Continuing,
By locally depositing WSiN / Au, for example, the gate electrode 110 having a length of 0.1 μm is formed.

Further, an insulating layer with compressive stress of, for example, 1 × 10 ¹⁰ dyn / cm ² is deposited on the entire surface with a thickness of, for example, 0.5 μm, and further, for example, by a reactive ion etching method. By removing the insulating layer deposited on the source electrode 17, the drain electrode 18 and the gate electrode 110, the electrical connection to each electrode is achieved and the surface of the semiconductor multilayer structure 16 between the source electrode and the gate electrode 16 is formed. Insulating layers 111 and 112 having a compressive stress are formed with a shape covering the entire surface and the entire surface of the semiconductor multilayer structure 16 between the drain electrode and the gate electrode, thereby forming the field effect transistor according to the present embodiment. To be done.

Since the operating principle of the field effect transistor of this embodiment is the same as that of the first conventional structure, detailed description thereof will be omitted. In this embodiment, compressive strain is generated in the semiconductor multilayer structure immediately below the gate electrode, and its magnitude is determined by the stress in the insulating layer and the ratio of the thickness of the insulating layer to the gate length. In the present embodiment, the magnitude of the compressive strain is the total amount of negative charges generated by the piezoelectric effect due to the compressive strain, and the amount of positive charges generated by ionization of the donor in the carrier supply layer 14 and the channel. The total amount of positive charges due to the difference in spontaneous polarization among the layer 12, the spacer layer 13, and the carrier supply layer 14 is exceeded.

Therefore, the two-dimensional electron gas does not exist in the channel layer immediately below the gate electrode when the gate voltage is not applied to the gate electrode, and the transistor operation having a positive threshold value is realized. Further, in this embodiment, the insulating layer 1
An expansive strain is generated in the semiconductor multilayer structure immediately below 11 and 112, which causes a positive charge due to the piezoelectric effect. Insulating layer 1 to neutralize it
The two-dimensional electron gas concentration in the channel layer 12 immediately below 11 and 112 increases.

The region where the two-dimensional electron gas concentration is high in the channel layer 12 is formed in a self-aligned manner with respect to the gate electrode, that is, the region where the two-dimensional electron gas concentration is high and the region where the two-dimensional electron gas is absent. The position of the boundary matches the position of the boundary between the region where the tensile strain is generated and the region where the compressive strain is generated, in other words, the position of the boundary between the gate electrode 110 and the insulating layers 111 and 112. The parasitic resistance of the field effect transistor according to this embodiment is significantly reduced as compared with the conventional structure. In addition, since the magnitude of the stress in the insulating layers 111 and 112, the thickness of the insulating layer, and the gate length are controlled with extremely high accuracy and high reproducibility, the field effect transistor according to the present embodiment has the following features. Realizes transistor operating characteristics with high accuracy and high reproducibility.

[Embodiment 2] FIG. 2 is an explanatory view showing a second embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 indicate the same or equivalent members. That is, a buffer layer 21 of AlN (40 nm), a channel layer 22 of GaN (3 μm), and Al on a sapphire (0001) substrate 20.
Spacer layer 23 of _0.25 Ga _0.75 N (3 nm), Al _0.25 Ga _0.75 N (8 nm) doped with a predetermined concentration of Si donor
The carrier supply layer 24 and the GaN (4 nm) Schottky layer 25 are sequentially epitaxially grown (for example, by MOCVD).
Or RF MBE) to form a semiconductor multilayer structure 26.

On the surface of the semiconductor multilayer structure thus manufactured, ohmic contact regions of the source electrode 27 and the drain electrode 28 are formed by locally depositing Ti / Al and heat-treating, for example, and the channel layer 22 is formed. Is electrically connected to the two-dimensional electron gas formed in. Subsequently, the barrier layer 29 is deposited on the entire surface of the portion between the source electrode and the drain electrode of the semiconductor multilayer structure 26 with a thickness of, for example, 5 nm, and further, for example, WSiN / Au is locally deposited to form a long layer, for example. A gate electrode 210 having a thickness of 0.1 μm is formed.

Further, for example, 1 × 10 ¹⁰ dyn / cm ²
An insulating layer with compressive stress is deposited on the entire surface with a thickness of, for example, 1.5 μm, and is further deposited on the source electrode 27, the drain electrode 28, and the gate electrode 210 by, for example, a reactive ion etching method. By removing the insulating layer adhering to the electrodes, electrical connection to each electrode is achieved and the entire surface of the barrier layer 29 between the source electrode and the gate electrode and the entire surface of the barrier layer 29 between the drain electrode and the gate electrode are achieved. Insulating layers 111 and 112 having a compressive stress are formed in accordance with the shape for covering, and thus the field effect transistor according to the present embodiment is formed.

The principle of operation of the field effect transistor of this embodiment is the same as that of the first conventional structure, so a detailed description will be omitted. Similar to the first embodiment, also in the present embodiment, compressive strain is generated in the semiconductor multilayer structure immediately below the gate electrode, and the magnitude thereof depends on the stress in the insulating layer and the thickness of the insulating layer and the gate length. Determined by the ratio. In this embodiment, the magnitude of the compressive strain is such that the total amount of negative charges generated by the piezoelectric effect due to it is
The sum of the positive charge amount generated by ionization of the donor in the carrier supply layer 24 and the positive charge amount due to the difference in spontaneous polarization in the channel layer 22, the spacer layer 23 and the carrier supply layer 24 is exceeded.

Therefore, the two-dimensional electron gas does not exist in the channel layer immediately below the gate electrode in the state where the gate voltage is not applied to the gate electrode, and the transistor operation having a positive threshold value is realized. Further, similarly to the first embodiment, in this embodiment, tensile strain is generated in the semiconductor multilayer structure immediately below the insulating layers 211 and 212, which causes positive charge due to the piezoelectric effect. Occur. In order to neutralize it, the two-dimensional electron gas concentration in the channel layer 22 directly below the insulating layers 211 and 212 increases.

The region where the two-dimensional electron gas concentration is high in the channel layer 22 is formed in self-alignment with the gate electrode, that is, the region where the two-dimensional electron gas concentration is high and the region where the two-dimensional electron gas is absent. The boundary position matches the position of the boundary between the region where the tensile strain is generated and the region where the compressive strain is generated, in other words, the position of the boundary between the gate electrode 210 and the insulating layers 211 and 212. The parasitic resistance of the field effect transistor according to this embodiment is significantly reduced as compared with the conventional structure.

Further, in this embodiment, the barrier layer 29 is located immediately below the gate electrode. As a result, the gate leakage current when the same gate voltage is applied is remarkably suppressed as compared with the first embodiment, so that more excellent transistor operating characteristics are realized. In addition, as in the first embodiment, the magnitude of stress in the insulating layers 211 and 212, the thickness of the insulating layer, and the gate length are controlled with extremely high precision and high reproducibility. In the field effect transistor according to this embodiment, the transistor operating characteristics with high accuracy and high reproducibility are realized.

[Embodiment 3] FIG. 3 is an explanatory view showing a third embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 indicate the same or equivalent members. That is, a buffer layer 31 of AlN (40 nm) and a channel layer 32 of GaN (3 μm) are sequentially epitaxially grown (for example, MOCVD or RF MB) on a sapphire (0001) substrate 30.
E) and the semiconductor multilayer structure 36 is formed. The surface of the channel layer 32 having a predetermined thickness is doped with Si donor having a predetermined concentration.

On the surface of the semiconductor multi-layer structure 36 thus manufactured, the source electrode 3 made of Ti / Al or the like is used.
7, an ohmic contact region of the drain electrode 38 is formed and electrically connected to the electron gas formed in the channel layer 32. Subsequently, for example, WSiN / Au is locally deposited to form a gate electrode 310 having a length of 0.1 μm, for example.

Further, for example, 1 × 10 ¹⁰ dyn / cm ²
An insulating layer with compressive stress is deposited on the entire surface with a thickness of, for example, 0.5 μm, and is further formed on the source electrode 37, the drain electrode 38, and the gate electrode 310 by, for example, a reactive etching method. By removing the attached insulating layer, electrical connection to each electrode is achieved, and the entire surface of the semiconductor multilayer structure 36 between the source electrode and the gate electrode and the surface of the semiconductor multilayer structure 36 between the drain electrode and the gate electrode are covered. Insulating layers 311 and 312 with compressive stress are formed with a shape covering the entire surface,
Thus, the field effect transistor according to this example is formed.

Since the operating principle of the field effect transistor of this embodiment is similar to that of the second conventional structure, detailed description thereof will be omitted. Similar to the first and second embodiments, also in this embodiment, compressive strain is generated in the semiconductor multi-layer structure immediately below the gate electrode, and its magnitude depends on the stress in the insulating layer and the thickness of the insulating layer. It is determined by the ratio of gate lengths. In the present embodiment, the magnitude of the compressive strain is such that the total amount of negative charges generated by the piezoelectric effect exceeds the amount of positive charges generated by the ionization of the donor in the channel layer 34.

Therefore, no electron gas is present in the channel layer immediately below the gate electrode without applying a gate voltage to the gate electrode, and a transistor operation having a positive threshold value is realized. Further, similarly to the first and second embodiments, in this embodiment, a tensile strain is generated in the semiconductor multilayer structure immediately below the insulating layers 311 and 312, which causes a positive strain due to the piezoelectric effect. Is generated. In order to neutralize it, the electron density in the channel layer 32 directly below the insulating layers 311 and 312 increases.

The region having a high electron density in the channel layer 32 is formed in a self-aligned manner with respect to the gate electrode, that is, the boundary between the region having a high electron density and the region where the electron gas does not exist is extensible. Since the position of the boundary between the strained region and the region where the compressive strain is generated, in other words, the position of the boundary between the gate electrode 310 and the insulating layers 311 and 312, is matched, the field effect transistor according to the present embodiment. The parasitic resistance of is significantly lower than that of the conventional structure.

In addition, since the magnitude of the stress in the insulating layers 311 and 312, the thickness of the insulating layer, and the gate length are controlled with extremely high precision and high reproducibility, the electric field according to the present embodiment is controlled. In the effect transistor, transistor operating characteristics with high accuracy and high reproducibility are realized.

[Embodiment 4] FIG. 4 is an explanatory view showing a fourth embodiment of the present invention. In the figure, the same symbols as those in FIG. 1 indicate the same or equivalent members. That is, a buffer layer 41 of AlN (40 nm) and a channel layer 42 of GaN (3 μm) are sequentially epitaxially grown (for example, MOCVD or RF MB) on a sapphire (0001) substrate 40.
E) and the semiconductor multilayer structure 46 is formed. The surface of the channel layer 42 having a predetermined thickness is doped with Si donor having a predetermined concentration.

On the surface of the semiconductor multi-layer structure 46 thus manufactured, the source electrode 4 made of, for example, Ti / Al or the like is used.
7, an ohmic contact region of the drain electrode 48 is formed, and is electrically connected to the electron gas formed in the channel layer 42. Subsequently, the barrier layer 49 is deposited on the entire surface of the portion between the source electrode and the drain electrode of the semiconductor multilayer structure 46 with a thickness of, for example, 5 nm, and further, for example, WSiN / Au is locally deposited, so that, for example, a long layer A gate electrode 410 having a thickness of 0.1 μm is formed.

Further, for example, 1 × 10 ¹⁰ dyn / cm ²
The insulating layer with compressive stress is deposited on the entire surface with a thickness of 0.5 μm, and is further deposited on the source electrode 47, the drain electrode 48, and the gate electrode 410 by reactive etching, for example. By removing the attached insulating layer, electrical connection to each electrode is achieved, and the entire surface of the barrier layer 49 between the source electrode and the gate electrode and the barrier layer 4 between the drain electrode and the gate electrode 4 are formed.
Insulating layers 411 and 412 with a compressive stress are formed with a shape that covers the entire surface of the surface, and thus the field effect transistor according to the present embodiment is formed.

Since the operating principle of the field effect transistor of this embodiment is the same as that of the second conventional structure, detailed description will be omitted. Similar to the first to third embodiments, also in the present embodiment, compressive strain is generated in the semiconductor multilayer structure immediately below the gate electrode, and its magnitude depends on the stress in the insulating layer and the thickness of the insulating layer. It is determined by the ratio of gate lengths. In the present embodiment, the magnitude of the compressive strain is such that the total amount of negative charges generated by the piezoelectric effect exceeds the amount of positive charges generated by ionization of the donor in the channel layer 42.

Therefore, no electron gas is present in the channel layer immediately below the gate electrode when no gate voltage is applied to the gate electrode, and a transistor operation having a positive threshold value is realized. Further, similarly to the second embodiment, in this embodiment, tensile strain is generated in the semiconductor multilayer structure immediately below the insulating layers 411 and 412, which causes positive charge due to the piezoelectric effect. Occur. In order to neutralize it, the channel layer 4 directly below the insulating layers 411 and 412
The electron density in 2 increases.

The region having a high electron density in the channel layer 32 is formed in a self-aligned manner with respect to the gate electrode, that is, the position of the boundary between the region having a high electron density and the region where no electron gas exists is extensible. Since the position of the boundary between the strained region and the region where the compressive strain is generated, in other words, the position of the boundary between the gate electrode 410 and the insulating layers 411 and 412, is matched, the field effect transistor according to the present embodiment. The parasitic resistance of is significantly lower than that of the conventional structure.

Further, in this embodiment, the barrier layer 49 is located immediately below the gate electrode as in the second embodiment. As a result, the gate leakage current when the same gate voltage is applied is remarkably suppressed as compared with the third embodiment, so that more excellent transistor operating characteristics are realized. In addition, since the magnitude of stress in the insulating layers 411 and 412, the thickness of the insulating layer, and the gate length are controlled with extremely high accuracy and high reproducibility, the field effect transistor according to this embodiment has Realizes transistor operating characteristics with high accuracy and high reproducibility.

As described above, the gist of the present invention is to form the insulating layer with compressive stress between the source electrode / gate electrode and between the drain electrode / gate electrode. It is obvious that the present invention also includes a field effect transistor in which the material and the forming method thereof are changed. As a modification, for example, Ti / Al is locally deposited on the source electrode and the drain electrode, and a refractory metal made of, for example, WSi is added to the Ti / A.
A modification is possible in which it is formed by locally heat-depositing it with a shape that covers the surface and side surfaces of l and then heat-treating it. Further, the gate electrode may be formed by lift-off after sequentially depositing Ni / Au, for example.

Further, in the first and third embodiments, the effect of the present invention is explained by the method of forming the gate electrode first and then forming the insulating layer accompanied by compressive stress. It is possible to first change the formation of the insulating layer accompanied by compressive stress, the formation of the gate opening, and then the formation of the gate electrode. The present invention can be applied not only to the field effect transistor having the semiconductor multilayer structure shown in the embodiments but also to the field effect transistor having another semiconductor multilayer structure having the same function.

[0051]

As described above in detail based on the embodiments, the present invention involves a predetermined compressive stress and a predetermined thickness between the source electrode / gate electrode and between the drain electrode / gate electrode. By forming an insulating layer, a compressive strain is generated in the portion of the semiconductor multilayer structure directly below the gate electrode, and an expansive strain is generated in the portion of the semiconductor multilayer structure directly below the insulating layer. Along with this, a field effect transistor having a low parasitic resistance is provided. This provides a field-effect transistor made of a normally-off type nitride compound semiconductor material having excellent transistor characteristics.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a first embodiment according to the present invention.

FIG. 2 is an explanatory diagram showing a second embodiment according to the present invention.

FIG. 3 is an explanatory diagram showing a third embodiment according to the present invention.

FIG. 4 is an explanatory diagram showing a fourth embodiment according to the present invention.

FIG. 5 is an explanatory diagram showing a first conventional example.

FIG. 6 is an explanatory diagram showing a second conventional example.

[Explanation of symbols]

10, 20, 30, 40, 50, 60 Substrates 11, 21, 31, 41, 51, 61 Buffer layers 12, 22, 32, 42, 52, 62 Channel layers 13, 23, 53 Spacer layers 14, 24, 54 , Carrier supply layers 15, 25, 55, Schottky layers 16, 26, 36, 46, 56, 66 semiconductor multilayer structure 17, 27, 37, 47, 57, 67 source electrodes 18, 28, 38, 48, 58, 68 Drain electrodes 29, 49 Barrier layers 100, 210, 310, 410, 510, 610 Gate electrodes 111, 112, 211, 212, 311, 312, 4
11,412 insulating layer

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kenji Shiojima             2-3-1, Otemachi, Chiyoda-ku, Tokyo             Inside Telegraph and Telephone Corporation F-term (reference) 5F102 FA01 FA02 GB01 GC01 GD01                       GJ10 GK04 GL04 GM04 GM07                       GM08 GQ01 GR07 GR09 GT03                       GV05 GV08 HC01 HC10

Claims (4)

[Claims] 1. A semiconductor multilayer structure is formed by sequentially depositing a buffer layer, a channel layer, a spacer layer, a carrier supply layer, and a Schottky layer on a substrate, and a source electrode, a drain electrode, and a gate electrode are the semiconductor multilayer structure. In the field effect transistor formed on the structure surface, a compressive property is provided with a shape covering the entire surface of the semiconductor multilayer structure surface between the source electrode and the gate electrode and the entire surface of the semiconductor multilayer structure surface between the drain electrode and the gate electrode. A field-effect transistor characterized in that an insulating layer with stress is formed. 2. A semiconductor multilayer structure is formed by sequentially depositing a buffer layer, a channel layer, a spacer layer, a carrier supply layer and a Schottky layer on a substrate, and a source electrode and a drain electrode are formed on the surface of the semiconductor multilayer structure. In the formed field effect transistor, a barrier layer is formed between the source electrode and the drain electrode on the surface of the semiconductor multilayer structure, a gate electrode is locally formed on the barrier layer, and a barrier between the source electrode and the gate electrode is formed. A field effect transistor, characterized in that a break line layer with compressive stress is formed with a shape covering the entire surface of the layer and the entire surface of the barrier layer between the drain electrode and the gate electrode. 3. A field effect transistor in which a semiconductor multilayer structure is formed by sequentially depositing a buffer layer and a channel layer on a substrate, and a source electrode, a drain electrode and a gate electrode are formed on the surface of the semiconductor multilayer structure. , An insulating layer with compressive stress is formed with a shape covering the entire surface of the semiconductor multilayer structure between the source electrode and the gate electrode and the entire surface of the semiconductor multilayer structure between the drain electrode and the gate electrode. Characteristic field effect transistor. 4. A field effect transistor in which a semiconductor multilayer structure is formed by sequentially depositing a buffer layer and a channel layer on a substrate, and a source electrode and a drain electrode are formed on the surface of the semiconductor multilayer structure. A barrier layer is formed between the source electrode and the drain electrode on the surface of the multilayer structure, and a gate electrode is locally formed on the barrier layer,
An insulating layer with compressive stress is formed with a shape covering the entire surface of the barrier layer between the source electrode and the gate electrode and the entire surface of the barrier layer between the drain electrode and the gate electrode. Field effect transistor.