JP3984471B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having an insulated gate using a nitride semiconductor as an active layer and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 19 shows a cross-sectional structure of a conventional Schottky gate type field effect transistor (FET) made of a group III-V nitride semiconductor.
[0003]
As shown in FIG. 19, a channel layer 102 made of gallium nitride (GaN) and a carrier supply layer 103 made of n-type aluminum gallium nitride (AlGaN) are sequentially formed on a substrate 101 made of sapphire. A two-dimensional electron gas layer made of a potential well and having a very high electron mobility is formed in the vicinity of the heterointerface with the carrier supply layer 103 at the upper part of the channel layer 102, whereby the FET is made to have a high electron mobility transistor (HEMT). ).
[0004]
[Problems to be solved by the invention]
However, in the conventional Schottky gate type FET, since the breakdown voltage of the gate electrode is determined by the Schottky characteristic, the reverse breakdown voltage of the gate electrode is also limited. In addition, since the forward applied voltage to the gate electrode is limited to about 2 V, there is a problem that a high-power semiconductor device (power device) having a high current driving capability cannot be obtained.
[0005]
An object of the present invention is to solve the above-described conventional problems and to increase the current driving capability of a semiconductor device having a gate electrode and made of a nitride semiconductor.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has a configuration in which a gate electrode in a semiconductor device made of a nitride semiconductor is an insulating gate, and a gate insulating film is formed by oxidizing the deposited nitride semiconductor itself. To do.
[0007]
  Specifically, the semiconductor device according to the present invention includes:A substrate,substrateofFirst nitride semiconductor formed onActive layer consisting ofWhen,Formed on the active layer and has a larger energy gap than the first nitride semiconductorFirst2A nitride semiconductor layer of2Formed on the nitride semiconductor layerThe oxidation rate is higher than that of the second nitride semiconductor layerFirst3An insulating oxide layer formed by oxidizing the nitride semiconductor layer, and a gate electrode formed on the insulating oxide layer.
[0008]
  According to the semiconductor device of the present invention, the first2The insulating oxide layer formed on the nitride semiconductor layer is2On the nitride semiconductor layer3Since the nitride semiconductor layer itself is formed by oxidation, the film quality of the insulating oxide layer is good, and the insulating oxide layer and its lower first layer are formed.2The interface in contact with the nitride semiconductor layer is also extremely clean. As a result, almost no leakage current is generated in the gate electrode formed on the insulating oxide layer, and the current-voltage characteristic is not regulated by the Schottky characteristic, so that a high breakdown voltage and high current driving capability can be obtained. .In addition, since the oxidation rate of the second nitride semiconductor layer is lower than the oxidation rate of the third nitride semiconductor layer, it is easy to selectively oxidize only the third nitride semiconductor layer. Furthermore, a high electron mobility transistor (HEMT) having a high breakdown voltage and a high current driving capability in which the second nitride semiconductor layer serves as a carrier supply layer and the first nitride semiconductor serves as a channel layer is reliably realized. Can do.
[0011]
  In the semiconductor device of the present invention, the first2The nitride semiconductor layer preferably contains aluminum (Al). As described above, aluminum gallium nitride (AlGaN) obtained by adding aluminum to gallium nitride (GaN), which is a typical nitride semiconductor material, is oxidized at the time of forming the insulating oxide layer because its oxidation rate is smaller than that of gallium nitride. In addition to being difficult, the energy gap is larger than that of gallium nitride, so that it becomes a potential barrier layer.
[0013]
  The semiconductor device of the present invention is the first2Formed between the nitride semiconductor layer and the insulating oxide layer.3An antioxidant layer made of a fourth nitride semiconductor smaller than the nitride semiconductor layer ofthingIs preferred. In this way,3When the nitride semiconductor layer is oxidized to form an insulating oxide layer, the fourth nitride semiconductor layer substantially stops the oxidation, so that the thickness of the insulating oxide layer to be a gate insulating film can be easily controlled. It becomes.
[0014]
In this case, the antioxidant layer is preferably made of aluminum nitride.
[0015]
The semiconductor device of the present invention preferably further includes an insulating film formed between the insulating oxide layer and the gate electrode. In this way, since the leak current generated in the gate electrode can be reliably suppressed, a high voltage can be applied to the gate electrode, so that the current driving capability of the semiconductor device can be further enhanced.
[0016]
In this case, the insulating film is preferably made of a silicon oxide film or a silicon nitride film. In this case, since the film quality of the insulating film becomes extremely dense, high insulating properties can be obtained.
[0017]
  The semiconductor device of the present invention is the first2Source formed in a region on the gate length side on the nitride semiconductor layerElectrodes andA drain electrode, and a gate electrode and a source in the insulating oxide layer;Electrodes andIt is preferable that a thick film portion having a thickness larger than the thickness of the lower portion of the gate electrode is provided at least between the drain electrode and the drain electrode. In this way, the thick filmRudenWhen the pole is a drain electrode, the drain withstand voltage of the drain electrode is increased, and the drain leakage current is decreased. Therefore, the operating voltage of the semiconductor device can be increased, so that high output can be easily achieved. it can.
[0018]
  A first method for manufacturing a semiconductor device according to the present invention is provided on a substrate.An active layer made of the first nitride semiconductor and a band gap larger than that of the first nitride semiconductorFirst2Nitride semiconductor layerAnd sequentiallyA first step of forming, and a first step2On the nitride semiconductor layerOxidation rate is higher than that of the second nitride semiconductor layerFirst3After forming the nitride semiconductor layer,3By oxidizing the nitride semiconductor layer of3A second step of forming an insulating oxide layer made of the nitride semiconductor layer, a third step of forming a gate electrode on the insulating oxide layer, and a region on the gate length direction side in the insulating oxide layer. Etching is performed to form an opening in the insulating oxide layer, and the source is formed on the formed opening.Electrodes andAnd a fourth step of forming a drain electrode.
[0019]
  According to the first semiconductor device manufacturing method,2On top of the nitride semiconductor layer3Forming a nitride semiconductor layer of3By oxidizing the nitride semiconductor layer of3Since the insulating oxide layer made of the nitride semiconductor layer is formed and the gate electrode is formed on the formed insulating oxide layer, the semiconductor device according to the present invention can be obtained reliably.
[0023]
  In the first method for manufacturing a semiconductor device, the first step and the second step are performed between the first step and the second step.2The oxidation rate is increased on the nitride semiconductor layer.3Preferably, the method further includes a step of forming an antioxidant layer made of a fourth nitride semiconductor smaller than the nitride semiconductor layer. Thus, the first insulating oxide layer that is a gate insulating film is formed.3A nitride semiconductor layer and a second layer formed thereunder2Between the first and second nitride semiconductor layers3In order to form the antioxidant layer made of the fourth nitride semiconductor whose oxidation rate is lower than that of the nitride semiconductor layer, the antioxidant layer3It is less oxidized than the nitride semiconductor layer of3Since it is easy to oxidize only the nitride semiconductor layer, it is easy to control the film thickness of the insulating oxide layer that becomes a gate insulating film that greatly affects the operation characteristics of the transistor.
[0024]
In this case, the antioxidant layer preferably contains aluminum.
[0025]
  The first semiconductor device manufacturing method further includes a step of forming an insulating film on the insulating oxide layer between the second step and the third step, and the fourth step includes an insulating film. Source inElectrodes andIt is preferable to include a step of forming an opening also in a region where the drain electrode is formed.
[0026]
In this case, the insulating film is preferably made of a silicon oxide film or a silicon nitride film.
[0027]
  Further, in the first method for manufacturing a semiconductor device, the second step is the first step.3Forming an insulating oxide layer in at least a region for forming a gate electrode in the nitride semiconductor layer, a region for forming a gate electrode, and a sourceElectrodes andForming a thick film portion having a thickness larger than that of the insulating oxide layer in the insulating oxide layer by selectively oxidizing a region between the drain electrode and the region where the drain electrode is formed. preferable.
[0028]
  A second semiconductor device manufacturing method according to the present invention is provided on a substrate.An active layer made of the first nitride semiconductor and an energy gap larger than that of the first nitride semiconductorFirst2Nitride semiconductor layerAnd sequentiallyA first step of forming, and a first step2On the nitride semiconductor layerOxidation rate is higher than that of the second nitride semiconductor layerFirst3A second step of forming the nitride semiconductor layer, and3A third step of forming an oxidation protective film in the ohmic electrode formation region on the nitride semiconductor layer, and using the oxidation protective film as a mask,3By oxidizing the nitride semiconductor layer of3A fourth step of forming an insulating oxide layer in a region excluding the ohmic electrode formation region in the nitride semiconductor layer, and after removing the oxidation protective film,3A fifth step of forming an ohmic electrode on the ohmic electrode formation region of the nitride semiconductor layer, and a sixth step of selectively forming a gate electrode on the insulating oxide layer.
[0029]
  According to the second semiconductor device manufacturing method,3An insulating oxide layer is formed in a region excluding the ohmic electrode formation region of the nitride semiconductor layer, and then the first3An ohmic electrode is formed on the ohmic electrode forming region in the nitride semiconductor layer. For this reason3The ohmic electrode formation region in the nitride semiconductor layer is not oxidized, and as a result, the ohmic electrode3It can be formed without removing the nitride semiconductor layer. Therefore, the second3No processing of the nitride semiconductor layer is required.
[0030]
In the second method for manufacturing a semiconductor device, the oxidation protective film is preferably made of silicon. In the second method for manufacturing a semiconductor device, the oxidation protective film is preferably an insulating film.
[0031]
  In the second method for manufacturing a semiconductor device, the second semiconductor device is provided between the second step and the third step.3On the nitride semiconductor layer.3Forming a protective film covering the element formation region of the nitride semiconductor layer, and using the formed protective film as a mask,2Nitride semiconductor layer and first3Forming a device isolation film in the periphery of the device formation region by oxidizing the nitride semiconductor layer, and the third step includes a step of forming the oxidation protection film from the protection film. preferable.
[0033]
  In the second method for manufacturing a semiconductor device, the first step and the second step are performed between the first step and the second step.2The oxidation rate is increased on the nitride semiconductor layer.3Preferably, the method further includes a step of forming an antioxidant layer made of a fourth nitride semiconductor smaller than the nitride semiconductor layer.
[0034]
In this case, the antioxidant layer preferably contains aluminum.
[0035]
  In the first or second semiconductor device manufacturing method, the first2The nitride semiconductor layer preferably contains aluminum.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.
[0037]
FIG. 1 shows a cross-sectional structure of an insulated gate high electron mobility transistor (HEMT) made of a group III-V nitride semiconductor, which is a semiconductor device according to a first embodiment of the present invention.
[0038]
As shown in FIG. 1, for example, on a substrate 11 made of silicon carbide (SiC), a buffer made of aluminum nitride (AlN) that relaxes lattice mismatch between the substrate 11 and an epitaxial layer grown on the substrate 11. Carrier (electrons) is supplied to the channel layer 13, which is made of the layer 12, made of gallium nitride, and which is an active layer on which the two-dimensional electron gas layer is formed, and the n-type aluminum gallium nitride (AlGaN). The carrier supply layer 14 is sequentially formed.
[0039]
Nitride grown on the carrier supply layer 14 in the gate electrode formation region above the carrier supply layer 14 on the element formation region surrounded by the element isolation film 15 made of an insulator reaching the buffer layer 12 An insulating oxide layer 16B in which the semiconductor layer itself made of gallium is oxidized is selectively formed.
[0040]
A gate electrode 17 made of a laminate of titanium (Ti), platinum (Pt), and gold (Au) is formed on the insulating oxide layer 16B. A source / drain electrode 18 made of titanium (Ti) and aluminum (Al) in ohmic contact with the carrier supply layer 14 is formed in a region on the gate supply direction side of the gate electrode 17 on the carrier supply layer 14.
[0041]
As described above, the HEMT according to the present embodiment uses the insulating oxide layer 16B formed by oxidizing the nitride semiconductor layer grown on the carrier supply layer 14 as the gate insulating film. There are no impurities due to contamination or the like at the interface between the carrier supply layer 14 and the carrier supply layer 14, so that a good interface is formed. In addition, since the insulating oxide layer 16B is formed by oxidizing nitride, the film quality is extremely fine and has high insulating properties.
[0042]
FIG. 2 shows current-voltage characteristics of the HEMT according to the first embodiment. The horizontal axis represents the voltage value Vds between the source and drain, and the vertical axis represents the current value per gate width. Since the HEMT according to the present embodiment has an excellent insulating characteristic of the insulating oxide layer 16B which is a gate insulating film, the drain withstand voltage reaches 200 V or higher, and a gate-source voltage Vgs of 5 V or higher is applied in the forward direction. However, it can be seen that no leak current is generated from the gate electrode 17 and that a good current-voltage characteristic is exhibited.
[0043]
Hereinafter, a method for manufacturing a HEMT having an insulated gate configured as described above will be described with reference to the drawings.
[0044]
3 (a) to 3 (c), 4 (a), and 4 (b) show cross-sectional structures in order of steps of the method for manufacturing an insulated gate HEMT according to the first embodiment of the present invention. ing.
[0045]
First, as shown in FIG. 3A, a buffer layer 12 made of, for example, aluminum nitride having a thickness of about 100 nm is formed on a substrate 11 made of silicon carbide by a metal organic chemical vapor deposition (MOCVD) method. A channel layer 13 made of gallium nitride having a thickness of about 3 μm, a carrier supply layer 14 made of n-type aluminum gallium nitride that has a thickness of about 15 nm and is doped with silicon (Si), and a thickness of about 50 nm to 100 nm By sequentially growing the insulating film forming layer 16A made of gallium nitride, an epitaxial laminated body made of a nitride semiconductor is formed.
[0046]
Next, as shown in FIG. 3B, a protective film (not shown) made of silicon that masks the element formation region is formed by lithography and etching, and then an oxidizing atmosphere is applied to the substrate 11. Then, a thermal oxidation process is performed for about 1 to 2 hours, and the element isolation film 15 is selectively formed on the epitaxial laminated body.
[0047]
Next, as shown in FIG. 3C, after the protective film is removed, the insulating film forming layer 16A is insulated from the insulating film forming layer 16A by performing a thermal oxidation treatment for about several minutes in an oxidizing atmosphere. An oxide layer 16B is formed.
[0048]
Next, as shown in FIG. 4A, a gate electrode formation film is formed by laminating titanium and platinum with a film thickness of about 50 nm and gold with a film thickness of about 200 nm by, for example, sputtering. Subsequently, the gate electrode forming film is selectively patterned by lithography and dry etching to form the gate electrode 17 from the gate electrode forming film. After that, the region on the gate length direction side in the insulating oxide layer 16B is selectively etched to provide the opening 16a in the insulating oxide layer 16B, thereby exposing the carrier supply layer 14 from the opening 16a.
[0049]
Next, as shown in FIG. 4B, titanium having a thickness of about 20 nm and aluminum having a thickness of about 200 nm are stacked on the exposed portion of the carrier supply layer 14 from the opening 16a by, for example, sputtering. To do. Subsequently, a predetermined patterning is performed on the deposited metal film by lithography and dry etching, and further heat treatment is performed to form a source / drain electrode 18 in ohmic contact with the carrier supply layer 14 from the metal film.
[0050]
As described above, in the method for manufacturing the HEMT according to the first embodiment, the insulating film forming layer 16A made of gallium nitride is grown on the upper surface of the epitaxial multilayer, and the grown insulating film forming layer 16A is thermally oxidized. Thus, an insulating oxide layer 16B to be a gate insulating film is formed.
[0051]
In the first embodiment, the thickness of the insulating oxide layer 16B is adjusted by the heating time for the insulating film forming layer 16A. Comparing the oxidation rate between the insulating film forming layer 16A made of gallium nitride (GaN) and the carrier supply layer 14 made of aluminum gallium nitride (AlGaN), when the Al composition is 0.3, the oxidation rate of gallium nitride Is about twice as high as the oxidation rate of aluminum gallium nitride, which can suppress the oxidation of the carrier supply layer 14 located below the insulating oxide layer 16B.
[0052]
(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0053]
FIG. 5 shows a cross-sectional structure of an insulated gate HEMT made of a group III-V nitride semiconductor, which is a semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same components as those shown in FIG.
[0054]
As shown in FIG. 5, for example, on a substrate 11 made of silicon carbide, carriers are transferred to a buffer layer 12 made of aluminum nitride, a channel layer 13 made of gallium nitride, and a channel layer 13 made of n-type aluminum gallium nitride. A carrier supply layer 14 for supplying (electrons) and an antioxidant layer 20 made of aluminum nitride are sequentially formed.
[0055]
On the element formation region surrounded by the element isolation film 15 made of an insulator and in the gate electrode formation region on the antioxidant layer 20, the semiconductor layer itself made of gallium nitride grown on the antioxidant layer 20 is oxidized. The insulating oxide layer 16B thus formed is selectively formed.
[0056]
A gate electrode 17 made of a laminate of titanium, platinum and gold is formed on the insulating oxide layer 16B. A source / drain electrode 18 made of titanium and aluminum that is in ohmic contact with the antioxidant layer 20 is formed in a region on the antioxidant layer 20 on the gate length direction side.
[0057]
As described above, the HEMT according to the second embodiment is characterized in that the antioxidant layer 20 made of aluminum nitride is formed between the insulating oxide layer 16 </ b> B serving as the gate insulating film and the carrier supply layer 14. To do. As a result, as in the first embodiment, an excellent interface is formed at the interface between the insulating oxide layer 16B and the antioxidant layer 20 because no impurities due to contamination exist at all. In addition, since the insulating oxide layer 16B is formed by oxidizing nitride, the film quality is extremely fine and has excellent insulating properties.
[0058]
The antioxidant layer 20 functions as an oxidation stopper layer during the oxidation process in the insulating oxide layer 16B.
[0059]
FIG. 6 shows current-voltage characteristics of the HEMT according to the second embodiment. The horizontal axis represents the voltage value Vds between the source and drain, and the vertical axis represents the current value per gate width. Since the HEMT according to the present embodiment has an excellent insulating characteristic of the insulating oxide layer 16B which is a gate insulating film, the drain withstand voltage reaches 200 V or higher, and a gate-source voltage Vgs of 5 V or higher is applied in the forward direction. However, no leak current is generated from the gate electrode 17 and good current-voltage characteristics are exhibited.
[0060]
Hereinafter, a method for manufacturing a HEMT having an insulated gate configured as described above will be described with reference to the drawings.
[0061]
7 (a) to 7 (c), 8 (a), and 8 (b) show cross-sectional structures in order of steps of the method for manufacturing an insulated gate HEMT according to the second embodiment of the present invention. ing.
[0062]
First, as shown in FIG. 7A, a buffer layer 12 made of aluminum nitride having a thickness of about 100 nm and a gallium nitride having a thickness of about 3 μm are formed on a substrate 11 made of silicon carbide by MOCVD. A channel layer 13, a carrier supply layer 14 made of n-type aluminum gallium nitride that has a thickness of about 15 nm and dopants silicon, an antioxidant layer 20 made of aluminum nitride having a thickness of about 20 nm to 50 nm, and a film thickness Are grown sequentially with an insulating film forming layer 16A made of gallium nitride having a thickness of about 50 nm to 100 nm, thereby forming an epitaxial stacked body made of a nitride semiconductor.
[0063]
Next, as shown in FIG. 7B, a protective film (not shown) made of silicon that masks the element formation region is formed by lithography and etching, and then an oxidizing atmosphere is applied to the substrate 11. Then, a thermal oxidation process is performed for about 1 to 2 hours, and the element isolation film 15 is selectively formed on the epitaxial laminated body.
[0064]
Next, as shown in FIG. 7C, after the protective film is removed, the insulating film forming layer 16A is insulated from the insulating film forming layer 16A by performing thermal oxidation treatment for about several minutes in an oxidizing atmosphere. An oxide layer 16B is formed.
[0065]
Also in the second embodiment, the thickness of the insulating oxide layer 16B is adjusted by the heating time for the insulating film forming layer 16A. However, the oxidation rate of aluminum nitride constituting the antioxidant layer 20 is the same as the oxidation rate of gallium nitride. Compared with the extremely small 1/50, it can be considered that the oxidation treatment on the insulating film forming layer 16A is stopped at the antioxidant layer 20. Therefore, even if all of the insulating film forming layer 16A is oxidized, the carrier supply layer 14 is not oxidized, and the film thickness of the insulating oxide layer 16B is substantially adjusted by the film thickness of the insulating film forming layer 16A. Will be able to. As a result, it is possible to greatly improve the film thickness controllability of the insulating oxide layer 16B, which greatly affects the operating characteristics of the element having an insulating gate.
[0066]
Next, as shown in FIG. 8A, a gate electrode formation film is formed by laminating titanium and platinum with a film thickness of about 50 nm and gold with a film thickness of about 200 nm by sputtering, for example. Subsequently, the gate electrode forming film is selectively patterned by lithography and dry etching to form the gate electrode 17 from the gate electrode forming film. Thereafter, the region on the gate length direction side in the insulating oxide layer 16B is selectively etched to provide the opening 16a in the insulating oxide layer 16B, thereby exposing the antioxidant layer 20 from the opening 16a.
[0067]
Next, as shown in FIG. 8B, titanium having a thickness of about 20 nm and aluminum having a thickness of about 200 nm are stacked on the exposed portion of the antioxidant layer 20 from the opening 16a by, for example, sputtering. To do. Subsequently, a predetermined patterning is performed on the deposited metal film by lithography and dry etching, and further heat treatment is performed to form the source / drain electrodes 18 in ohmic contact with the antioxidant layer 20 from the metal film.
[0068]
Further, the antioxidant layer 20 is not limited to aluminum nitride, and may contain gallium or indium as a III-V group element. However, in order to reduce the oxidation rate, it is preferable to relatively increase the aluminum composition in the antioxidant layer 20.
[0069]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
[0070]
FIG. 9 shows a cross-sectional configuration of an insulated gate HEMT made of a III-V nitride semiconductor, which is a semiconductor device according to the third embodiment of the present invention. 9, the same components as those shown in FIG. 1 are denoted by the same reference numerals.
[0071]
As shown in FIG. 9, for example, on a substrate 11 made of silicon carbide, a buffer layer 12 made of aluminum nitride that relaxes lattice mismatch between the substrate 11 and an epitaxial layer grown on the substrate 11, and gallium nitride A channel layer 13 as an active layer on which a two-dimensional electron gas layer is formed, a carrier supply layer 14 made of n-type aluminum gallium nitride for supplying carriers (electrons) to the channel layer 13, and aluminum nitride The anti-oxidation layer 20 made of is sequentially formed.
[0072]
On the element formation region surrounded by the element isolation film 15 made of an insulator reaching the buffer layer 12, the gate electrode formation region on the antioxidant layer 20 is made of gallium nitride grown on the antioxidant layer 20. An insulating oxide layer 16B in which the semiconductor layer itself is oxidized is selectively formed, and silicon oxide (SiO 2) is further formed on the insulating oxide layer 16B.₂ An upper gate insulating film 21 is formed. As a result, in the third embodiment, the gate insulating film 26 includes the lower gate insulating film made of the insulating oxide layer 16B and the upper gate insulating film 21.
[0073]
A gate electrode 17 made of a laminate of titanium, platinum and gold is formed on the gate insulating film 26. A source / drain electrode 18 made of titanium and aluminum that is in ohmic contact with the antioxidant layer 20 is formed in a region on the gate length direction side of the gate electrode 17 on the antioxidant layer 20.
[0074]
As described above, the HEMT according to the third embodiment uses the insulating oxide layer 16B formed by oxidizing the nitride semiconductor layer grown on the carrier supply layer 14 as the lower gate insulating film. Since there is no impurity due to contamination or the like at the interface between the oxide layer 16B and the carrier supply layer 14, a good interface is formed. In addition, since the insulating oxide layer 16B is formed by oxidizing nitride, the film quality is extremely fine and has high insulating properties.
[0075]
Further, in the third embodiment, since the upper gate insulating film 21 made of silicon oxide is provided between the gate electrode 17 and the insulating oxide layer 16B, the leakage current due to the gate electrode 17 hardly occurs. . As a result, since a relatively high voltage can be applied to the gate electrode 17, the current driving capability of the HEMT can be further enhanced.
[0076]
FIG. 10 shows current-voltage characteristics of the HEMT according to the third embodiment. The horizontal axis represents the voltage value Vds between the source and drain, and the vertical axis represents the current value per gate width. In the HEMT according to the present embodiment, the gate insulating film 26 includes the insulating oxide layer 16B and the upper gate insulating film 21, and the insulating characteristics thereof are extremely excellent. Therefore, the drain breakdown voltage reaches 200V or more. In addition, it can be seen that even when a gate-source voltage Vgs of 8 V or more is applied in the forward direction, no leak current is generated from the gate electrode 17 and a good current-voltage characteristic is exhibited.
[0077]
Hereinafter, a method for manufacturing a HEMT having an insulated gate configured as described above will be described with reference to the drawings.
[0078]
11 (a) to 11 (c), FIG. 12 (a), and FIG. 12 (b) show cross-sectional structures in the order of steps of the method for manufacturing an insulated gate HEMT according to the third embodiment of the present invention. ing.
[0079]
First, as shown in FIG. 11A, by MOCVD, a buffer layer 12 made of, for example, aluminum nitride having a thickness of about 100 nm and a gallium nitride having a thickness of about 3 μm are formed on a substrate 11 made of silicon carbide. A channel layer 13, a carrier supply layer 14 made of n-type aluminum gallium nitride having a thickness of about 15 nm and doped with silicon (Si), and an antioxidant layer 20 made of aluminum nitride having a thickness of about 20 nm to 50 nm. By sequentially growing an insulating film forming layer 16A made of gallium nitride having a thickness of about 50 nm to 100 nm, an epitaxial stacked body made of a nitride semiconductor is formed.
[0080]
Next, a protective film (not shown) made of silicon that masks the element formation region is formed by lithography and etching, and then the substrate 11 is thermally oxidized in an oxidizing atmosphere for about 1 to 2 hours. The element isolation film 15 is selectively formed on the epitaxial multilayer.
[0081]
Next, as shown in FIG. 11B, after the protective film is removed, the insulating film forming layer 16A is insulated from the insulating film forming layer 16A by performing a thermal oxidation treatment for about several minutes in an oxidizing atmosphere. An oxide layer 16B is formed. Subsequently, the upper gate insulating film 21 made of silicon oxide having a thickness of about 10 nm is formed on the insulating oxide layer 16B by, for example, the CVD method.
[0082]
Here, also in the third embodiment, the film thickness of the insulating oxide layer 16B is adjusted by the heating time for the insulating film forming layer 16A. However, as in the second embodiment, the antioxidant layer 20 is formed of the insulating film. By providing it below the formation layer 16A, the film thickness of the insulating oxide layer 16B can be substantially adjusted by the film thickness of the insulation film formation layer 16A. As a result, it is possible to greatly improve the film thickness controllability of the insulating oxide layer 16B, which greatly affects the operating characteristics of the element having an insulating gate.
[0083]
Next, as shown in FIG. 12A, a gate electrode formation film is formed by laminating titanium and platinum having a film thickness of about 50 nm and gold having a film thickness of about 200 nm by sputtering, for example. Subsequently, the gate electrode forming film is selectively patterned by lithography and dry etching to form the gate electrode 17 from the gate electrode forming film. As a result, a gate insulating film 26 composed of the upper gate insulating film 21 and the lower gate insulating film made of the insulating oxide layer 16B is formed below the gate electrode 17. Thereafter, the upper gate insulating film 21 and the insulating oxide layer 16B are selectively etched in regions on the gate length direction side to provide openings 16a in the upper gate insulating film 21 and the insulating oxide layer 16B. The antioxidant layer 20 is exposed from the opening 16a.
[0084]
Next, as shown in FIG. 12B, titanium having a thickness of about 20 nm and aluminum having a thickness of about 200 nm are stacked on the exposed portion of the antioxidant layer 20 from the opening 16a by, for example, sputtering. To do. Subsequently, a predetermined patterning is performed on the deposited metal film by lithography and dry etching, and further heat treatment is performed to form the source / drain electrodes 18 in ohmic contact with the antioxidant layer 20 from the metal film.
[0085]
As described above, the HEMT manufacturing method according to the third embodiment includes the gate insulating film 26, the insulating oxide layer 16B in which the insulating film forming layer 16A made of gallium nitride is thermally oxidized, and the insulating oxide layer 16B. The upper gate insulating film 21 is formed on the upper gate insulating film 21. Thereby, as described above, the leakage current due to the gate electrode 17 can be prevented, and the voltage applied to the gate electrode 17 can be increased, so that the current driving capability of the HEMT can be improved.
[0086]
In the third embodiment, silicon oxide is used for the upper gate insulating film 21 of the gate insulating film 26, but is not limited to silicon oxide. That is, any material having good adhesion to the oxide insulating layer 16B and having higher insulating properties than the oxide insulating layer 16B may be used. For example, silicon nitride (Si_ThreeN_Four) May be used.
[0087]
(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.
[0088]
FIG. 13 shows a cross-sectional structure of an insulated gate HEMT made of a III-V nitride semiconductor, which is a semiconductor device according to the fourth embodiment of the present invention. In FIG. 13, the same components as those shown in FIG.
[0089]
As shown in FIG. 13, for example, on a substrate 11 made of silicon carbide, a buffer layer 12 made of aluminum nitride that relaxes lattice mismatch between the substrate 11 and an epitaxial layer grown on the substrate 11, and gallium nitride A channel layer 13 as an active layer on which a two-dimensional electron gas layer is formed, and a carrier supply layer 14 made of n-type aluminum gallium nitride (AlGaN) and supplying carriers (electrons) to the channel layer 13. Are sequentially formed.
[0090]
Gallium nitride grown on the carrier supply layer 14 is formed on the element formation region surrounded by the element isolation film 15 made of an insulator reaching the buffer layer 12 and in the gate electrode formation region on the carrier supply layer 14. An insulating oxide layer 16B is selectively formed by oxidizing the insulating film forming layer 16A itself.
[0091]
A gate electrode 47 made of a laminate of titanium, platinum and gold is formed on the insulating oxide layer 16B, and the carrier supply layer 14 is formed in a region on the gate length direction side of the gate electrode 17 on the carrier supply layer 14. A source electrode 18s and a drain electrode 18d made of titanium and aluminum are formed in ohmic contact with each other.
[0092]
In the fourth embodiment, as shown in FIG. 13, in the region between the gate electrode 17 and the drain electrode 18d, the thick film portion in which the insulating oxide layer 16B is thicker than the lower portion of the gate electrode 17 16c.
[0093]
As described above, the HEMT according to the fourth embodiment uses the insulating oxide layer 16B formed by oxidizing the insulating film forming layer 16A made of gallium nitride grown on the carrier supply layer 14 as the gate insulating film. Therefore, since there is no impurity due to contamination or the like at the interface between the insulating oxide layer 16B, the carrier supply layer 14, and the insulating film forming layer 16A, a good interface is formed. In addition, since the insulating oxide layer 16B is formed by oxidizing nitride, the film quality is extremely fine and has high insulating properties.
[0094]
Further, since the thick film portion 16c is formed in the insulating oxide layer 16B between the gate electrode 17 and the drain electrode 18d, the drain breakdown voltage of the HEMT is increased and the drain leakage current is reduced. As a result, since the operating voltage of the HEMT can be increased, high output can be easily achieved.
[0095]
FIG. 14 shows current-voltage characteristics of the HEMT according to the fourth embodiment. The horizontal axis represents the voltage value Vds between the source and drain, and the vertical axis represents the current value per gate width. The HEMT according to the present embodiment is excellent in the insulating characteristics of the insulating oxide layer 16B, which is a gate insulating film, and is a thick film in which the insulating oxide layer 16B is thickened between the gate electrode 17 and the drain electrode 18d. Since the portion 16c is provided, the drain breakdown voltage reaches 250V or more. Further, it can be seen that even when a gate-source voltage Vgs of 6 V or more is applied in the forward direction, no leakage current is generated from the gate electrode 17 and a good current-voltage characteristic is exhibited.
[0096]
Hereinafter, a method for manufacturing a HEMT having an insulated gate configured as described above will be described with reference to the drawings.
[0097]
15 (a) to 15 (d) and FIGS. 16 (a) to 16 (c) show cross-sectional structures in order of steps of the method for manufacturing an insulated gate HEMT according to the fourth embodiment of the present invention. ing.
[0098]
First, as shown in FIG. 15A, by a MOCVD method, a buffer layer 12 made of, for example, aluminum nitride having a thickness of about 100 nm and a gallium nitride having a thickness of about 3 μm are formed on a substrate 11 made of silicon carbide. The channel layer 13, the carrier supply layer 14 made of n-type aluminum gallium nitride having a thickness of about 15 nm and doped with silicon, and the insulating film forming layer 16 A made of gallium nitride having a thickness of about 50 nm to 100 nm are sequentially formed. By growing, an epitaxial laminated body made of a nitride semiconductor is formed.
[0099]
Next, as shown in FIG. 15B, a protective film 41 made of silicon masking the element formation region is formed by lithography and etching, and then the substrate 11 is oxidized in an oxidizing atmosphere for 1 to 2 hours. The element isolation film 15 is selectively formed on the epitaxial laminated body by performing a thermal oxidation treatment to the extent.
[0100]
Next, as shown in FIG. 15C, an opening is formed between the gate electrode formation region and the drain electrode formation region in the protective film 41 by lithography and etching, and the insulating film formation layer 16A is formed. Exposed. Thereafter, the exposed edge film forming layer 16A is subjected to a thermal oxidation process in an oxidizing atmosphere for about several minutes, so that an insulating film is formed between the gate electrode forming region and the drain electrode forming region in the insulating film forming layer 16A. The thick film forming portion 16b is formed by partially oxidizing the formation layer 16A itself.
[0101]
Next, as shown in FIG. 15D, the protective film 41 is removed, and subsequently, the insulating film forming layer 16A is subjected to a thermal oxidation treatment for about several minutes in an oxidizing atmosphere to thereby form the insulating film forming layer 16A. Further, the insulating film forming layer 16A itself is oxidized by further oxidizing the thick film forming portion 16b, and the insulating oxide layer 16B having the thick film portion 16c is formed between the gate electrode forming region and the drain electrode forming region. Form.
[0102]
Next, as shown in FIG. 16A, titanium and platinum with a film thickness of about 50 nm and gold with a film thickness of about 200 nm are stacked by sputtering, for example, and then, lithography and dry etching are used. The gate electrode 17 is formed from the gate electrode formation film by performing predetermined patterning on the deposited gate electrode formation film.
[0103]
Next, as shown in FIG. 16B, the region on the gate length direction side in the insulating oxide layer 16B is selectively etched to provide an opening 16a in the insulating oxide layer 16B. The carrier supply layer 14 is exposed from the portion 16a.
[0104]
Next, as shown in FIG. 16C, titanium having a thickness of about 20 nm and aluminum having a thickness of about 200 nm are formed on the exposed portion of the carrier supply layer 14 from the opening 16a by, for example, sputtering. Laminate. Subsequently, a predetermined patterning is performed on the deposited metal film by a lithography method and a dry etching method, and a heat treatment is further performed, so that the source electrode 18s and the drain electrode 18d that are in ohmic contact with the carrier supply layer 14 from the metal film, respectively. Form.
[0105]
Thus, according to the fourth embodiment, the insulating oxide layer 16B by thermal oxidation is formed to be partially thick by providing the thick film portion 16c between the gate electrode 17 and the drain electrode 18d. ing. As a result, as described above, the drain breakdown voltage of the HEMT can be increased and the drain leakage current can be suppressed.
[0106]
In the fourth embodiment, the thick film forming portion 16b is formed before the insulating oxide layer 16B is formed. On the contrary, the insulating oxide layer 16B is formed with a substantially uniform thickness. After that, the thick film portion 16c may be formed.
[0107]
Further, although silicon is used for the protective film 41, any material that can prevent oxidation of the nitride-based semiconductor layer may be used. For example, silicon oxide or silicon nitride may be used instead of silicon.
[0108]
(Fifth embodiment)
Hereinafter, a method for manufacturing a HEMT according to a fifth embodiment of the present invention will be described with reference to the drawings.
[0109]
17 (a) to 17 (c), 18 (a), and 18 (b) show cross-sectional structures in order of steps of a method for manufacturing an insulated gate HEMT according to the fifth embodiment of the present invention. ing.
[0110]
First, as shown in FIG. 17A, by a MOCVD method, a buffer layer 12 made of, for example, aluminum nitride having a thickness of about 100 nm and a gallium nitride having a thickness of about 3 μm are formed on a substrate 11 made of silicon carbide. A channel layer 13, a carrier supply layer 14 made of n-type aluminum gallium nitride that has a thickness of about 15 nm and dopants silicon, an antioxidant layer 20 made of aluminum nitride having a thickness of about 20 nm to 50 nm, and a film thickness Is grown sequentially with an insulating film forming layer 16A made of gallium nitride having a thickness of about 50 nm to 100 nm, thereby forming an epitaxial laminated body made of a nitride semiconductor.
[0111]
Next, as shown in FIG. 17B, a protective film 41A made of silicon that masks the element formation region is formed by lithography and etching, and then the substrate 11 is oxidized in an oxidizing atmosphere in an amount of 1-2. The element isolation film 15 is selectively formed on the epitaxial multilayer by performing thermal oxidation for about an hour.
[0112]
Next, as shown in FIG. 17C, an oxidation protective film 41B that masks the ohmic electrode formation region in the insulating film forming layer 16A is formed from the protective film 41A by lithography and etching. Subsequently, by using the formed oxidation protection film 41B as a mask, the insulating film forming layer 16A is subjected to a thermal oxidation process for about several minutes in an oxidizing atmosphere, so that the insulating film forming layer 16A is changed from the insulating film forming layer 16A. An insulating oxide layer 16B having a conductive region 16d is formed in the ohmic electrode formation region.
[0113]
Here, also in the fifth embodiment, the film thickness of the insulating oxide layer 16B is adjusted by the heating time for the insulating film forming layer 16A. However, as in the second embodiment, the antioxidant layer 20 is formed of the insulating film. By providing it below the formation layer 16A, the film thickness of the insulating oxide layer 16B can be substantially adjusted by the film thickness of the insulation film formation layer 16A. As a result, it is possible to greatly improve the film thickness controllability of the insulating oxide layer 16B, which greatly affects the operating characteristics of the element having an insulating gate.
[0114]
Next, as shown in FIG. 18A, the oxidation protection film 41B is removed, and thereafter, titanium and platinum with a film thickness of about 50 nm and gold with a film thickness of about 200 nm are stacked by, for example, sputtering, Subsequently, the gate electrode 17 is formed from the gate electrode formation film by performing predetermined patterning on the deposited gate electrode formation film by lithography and dry etching.
[0115]
Next, as shown in FIG. 18B, titanium having a thickness of about 20 nm and aluminum having a thickness of about 200 nm are stacked on the insulating oxide layer 16B and the conductive region 16d by, for example, sputtering. . Subsequently, the deposited metal film is subjected to predetermined patterning by a lithography method and a dry etching method, and further subjected to heat treatment to form a source / drain electrode 18 in ohmic contact with the conductive region 16d from the metal film.
[0116]
As described above, in the HEMT manufacturing method according to the fifth embodiment, when the insulating oxide layer 16B is formed from the insulating film forming layer 16A by thermal oxidation, the ohmic electrode forming region in the insulating film forming layer 16A is treated as an oxidation protective film. An insulating oxide layer 16B is formed in a state masked by 41B. As a result, the ohmic electrode formation region in the insulating film formation layer 16A is not oxidized and remains as the conductive region 16d that maintains good electrical characteristics. Therefore, the source / drain electrode 18 can be formed as a good ohmic electrode with low contact resistance. it can.
[0117]
In the fifth embodiment, silicon is used for the protective film 41A, but any material that can prevent oxidation of the nitride-based semiconductor layer may be used. For example, silicon oxide or silicon nitride may be used. good.
[0118]
In the fifth embodiment, the oxidation protection film 41B masking the conductive region 16d of the insulating film formation layer 16A is formed from the protection film 41A for forming the element isolation film 15. However, the present invention is not limited to this. Absent. That is, in the step shown in FIG. 17C, the oxidation protection film 41B may be formed of another member. As an example, when the element isolation film 15 is formed by using a mesa isolation method in which the element isolation region is removed by etching instead of oxidizing the epitaxial stacked body, the oxidation protection film 41B is newly formed. There is a need.
[0119]
Furthermore, in each of the first to fifth embodiments, gallium nitride (GaN) is used for the insulating oxide layer 16B. However, the present invention is not limited to this. If a high-quality oxide layer can be formed, aluminum gallium nitride, indium gallium nitride ( A so-called gallium nitride-based semiconductor such as InGaN) or indium aluminum gallium nitride (InAlGaN) may be used.
[0120]
Further, although the insulating oxide layer 16B is formed by performing thermal oxidation on the insulating film forming layer 16A, any method that can form a good oxide film having excellent insulating properties may be used. For example, the insulating film forming layer 16A The insulating oxide layer 16B may be formed by ion implantation or plasma doping.
[0121]
In each of the embodiments except for the fourth embodiment, the insulating oxide layer 16B is oxidized on the entire insulating film forming layer 16A, but is performed on the upper portion of the insulating film forming layer 16A. Gallium nitride may remain in the lower part. In the fourth embodiment, the thick film portion 16c of the insulating oxide layer 16B is oxidized so as to reach the lower portion of the insulating film forming layer 16A. However, gallium nitride may remain in the lower portion.
[0122]
Further, the insulating film forming layer 16A made of gallium nitride is formed on the carrier supply layer 14 made of aluminum gallium nitride, but the thickness of the carrier supply layer 14 is increased so that only the upper portion thereof is selectively oxidized. Then, the insulating oxide layer 16B may be formed from the carrier supply layer 14 itself.
[0123]
Further, as a semiconductor device having an insulating gate, a HEMT using gallium nitride for the channel layer 13 and n-type aluminum gallium nitride for the carrier supply layer 14 is used. Instead, for example, gallium nitride, nitride It may be a HEMT or FET using aluminum gallium, indium gallium nitride, indium aluminum gallium nitride, or the like. However, in the case of HEMT, a material whose energy gap is larger than that of the channel layer 13 is usually used for the carrier supply layer 14. As is well known, the gallium nitride compound semiconductor has a larger energy gap in the semiconductor when the composition contains aluminum (Al), and the semiconductor energy gap becomes larger when the composition contains indium (In). Get smaller.
[0124]
Moreover, although silicon carbide was used for the substrate 11, gallium nitride or sapphire (Al₂ O_Three And the like, as long as the channel layer 13 made of a group III-V nitride semiconductor can be epitaxially grown.
[0125]
Further, the gate electrode 17 and the source / drain electrode 18 are not limited to the metals described above.
[0126]
Moreover, the formation order of the gate electrode 17 and the source / drain electrode 18 is not ask | required, and any may be formed first.
[0127]
In addition, the element isolation film 15 is formed by selectively oxidizing an epitaxial stacked body made of a nitride semiconductor, but may be formed by a mesa isolation method in which the element isolation portion is removed by etching.
[0128]
Further, instead of patterning the deposited metal film, the source / drain electrode 18 forms a mask pattern having a source / drain electrode formation region as an opening, and the opening is filled on the mask pattern. It may be formed by a so-called lift-off method in which a metal film is deposited and then the resist pattern is removed.
[0129]
【The invention's effect】
  According to the semiconductor device and the manufacturing method thereof according to the present invention,2The insulating oxide layer formed on the nitride semiconductor layer is2On the nitride semiconductor layer3Since the nitride semiconductor layer itself is formed by oxidation, the film quality of the insulating oxide layer is good, and the insulating oxide layer and its lower first layer are formed.2The interface in contact with the nitride semiconductor layer is also extremely clean. As a result, it is possible to prevent the occurrence of leakage current in the gate electrode formed on the insulating oxide layer, and the voltage characteristics are not regulated by the Schottky characteristics, so that the insulated gate semiconductor device has a high withstand voltage and a high current driving capability. Can be obtained.
[Brief description of the drawings]
FIG. 1 is a structural cross-sectional view showing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a graph showing current-voltage characteristics in the semiconductor device according to the first embodiment of the present invention.
FIGS. 3A to 3C are cross-sectional structural views in the order of steps showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS.
4A and 4B are structural cross-sectional views in order of steps showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention.
FIG. 6 is a graph showing current-voltage characteristics in a semiconductor device according to a second embodiment of the present invention.
FIGS. 7A to 7C are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS.
FIGS. 8A and 8B are structural cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention. FIGS.
FIG. 9 is a structural cross-sectional view showing a semiconductor device according to a third embodiment of the present invention.
FIG. 10 is a graph showing current-voltage characteristics in a semiconductor device according to a third embodiment of the present invention.
FIGS. 11A to 11C are structural cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS.
FIGS. 12A and 12B are structural cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention. FIGS.
FIG. 13 is a structural cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 14 is a graph showing current-voltage characteristics in a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 15A to 15D are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 16A to 16C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
FIGS. 17A to 17C are sectional views of a semiconductor device according to a fifth embodiment of the present invention in the order of steps showing a method for manufacturing a semiconductor device. FIGS.
FIGS. 18A and 18B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention in order of processes.
FIG. 19 is a structural cross-sectional view showing a HEMT having a conventional Schottky gate.
[Explanation of symbols]
11 Substrate
12 Buffer layer
13 Channel layer (active layer)
14 Carrier supply layer (first nitride semiconductor layer)
15 Device isolation membrane
16A Insulating film forming layer (second nitride semiconductor layer)
16B Insulating oxide layer
16a opening
16b Thick film forming part
16c Thick film part
16d conductive region
17 Gate electrode
18 Source drain electrode
18s source electrode
18d drain electrode
20 Antioxidation layer
21 Upper gate insulating film
26 Gate insulation film
41 Protective film
41A Protective film
41B Oxidation protection film

Claims (21)

A substrate,
An active layer made of a first nitride semiconductor formed on said substrate,
A second nitride semiconductor layer formed on the active layer and having a larger energy gap than the first nitride semiconductor;
An insulating oxide layer formed on the second nitride semiconductor layer and formed by oxidizing a third nitride semiconductor layer having a higher oxidation rate than the second nitride semiconductor layer ;
A semiconductor device comprising a gate electrode formed on the insulating oxide layer. The semiconductor device according to claim 1, wherein the second nitride semiconductor layer contains aluminum. An anti-oxidation layer formed between the second nitride semiconductor layer and the insulating oxide layer and made of a fourth nitride semiconductor having an oxidation rate smaller than that of the third nitride semiconductor layer is further provided. The semiconductor device according to claim 1 . The semiconductor device according to claim 3 , wherein the antioxidant layer is made of aluminum nitride.   The semiconductor device according to claim 1, further comprising an insulating film formed between the insulating oxide layer and the gate electrode. 6. The semiconductor device according to claim 5 , wherein the insulating film is made of a silicon oxide film or a silicon nitride film. A source electrode and a drain electrode formed in a region on the gate length direction side on the second nitride semiconductor layer;
The insulating oxide layer has a thick film portion having a thickness larger than a thickness of a lower portion of the gate electrode in at least one of the gate electrode and the source and drain electrodes. The semiconductor device according to claim 1. A first step of sequentially forming an active layer made of a first nitride semiconductor and a second nitride semiconductor layer having an energy gap larger than that of the first nitride semiconductor on a substrate;
After the formation of the third nitride semiconductor layer of high oxidation rate than the second nitride semiconductor layer on the second nitride semiconductor layer, oxidizing the third nitride semiconductor layer formed A second step of forming an insulating oxide layer made of the third nitride semiconductor layer;
A third step of forming a gate electrode on the insulating oxide layer;
A fourth step of selectively etching a region on the gate length direction side of the insulating oxide layer to form an opening in the insulating oxide layer, and forming a source electrode and a drain electrode on the formed opening; A method for manufacturing a semiconductor device, comprising: Between the first step and the second step,
Characterized in that it further comprises a step of forming an oxidation preventing layer oxidation rate becomes a fourth semiconductor smaller than the third nitride semiconductor layer on the second nitride semiconductor layer A method for manufacturing a semiconductor device according to claim 8 . The method for manufacturing a semiconductor device according to claim 9 , wherein the antioxidant layer contains aluminum. Between the second step and the third step,
Further comprising forming an insulating film on the insulating oxide layer;
9. The method of manufacturing a semiconductor device according to claim 8 , wherein the fourth step includes a step of forming an opening in a region of the insulating film where the source electrode and the drain electrode are formed. . 12. The method of manufacturing a semiconductor device according to claim 11 , wherein the insulating film is made of a silicon oxide film or a silicon nitride film. The second step includes
Forming the insulating oxide layer in at least a region for forming the gate electrode in the third nitride semiconductor layer;
By selectively oxidizing a region between the region where the gate electrode is formed and the region where the drain electrode is formed among the source electrode and the drain electrode, the thickness of the insulating oxide layer becomes the insulating oxide layer. The method for manufacturing a semiconductor device according to claim 8 , further comprising a step of forming a larger thick film portion. The method for manufacturing a semiconductor device according to claim 8 , wherein the second nitride semiconductor layer contains aluminum. A first step of sequentially forming an active layer made of a first nitride semiconductor and a second nitride semiconductor layer having an energy gap larger than that of the first nitride semiconductor on a substrate;
A second step of forming a third nitride semiconductor layer of the oxidation rate is greater than said second nitride semiconductor layer and the second nitride semiconductor layer on,
A third step of forming an oxidation protective film in the ohmic electrode formation region on the third nitride semiconductor layer;
As a mask the oxide protective layer, the third by oxidizing the nitride semiconductor layer, a fourth step of forming an insulating oxide layer in the region except for the ohmic electrode formation region in the third nitride semiconductor layer When,
A fifth step of forming an ohmic electrode on the ohmic electrode formation region in the third nitride semiconductor layer after removing the oxidation protective film;
And a sixth step of selectively forming a gate electrode on the insulating oxide layer. The method of manufacturing a semiconductor device according to claim 15 , wherein the oxidation protection film is made of silicon. The method of manufacturing a semiconductor device according to claim 15 , wherein the oxidation protection film is an insulating film. Between the second step and the third step,
On the third nitride semiconductor layer, forming a protective film covering the device formation region of the nitride semiconductor layer of the third,
And a step of oxidizing the second nitride semiconductor layer and the third nitride semiconductor layer using the formed protective film as a mask to form an element isolation film in a peripheral portion of the element formation region. ,
16. The method of manufacturing a semiconductor device according to claim 15 , wherein the third step includes a step of forming the oxidation protective film from the protective film. Between the first step and the second step,
Characterized in that it further comprises a step of forming an oxidation preventing layer oxidation rate becomes a fourth semiconductor smaller than the third nitride semiconductor layer on the second nitride semiconductor layer The method for manufacturing a semiconductor device according to claim 15 . The method of manufacturing a semiconductor device according to claim 19 , wherein the antioxidant layer contains aluminum. The method for manufacturing a semiconductor device according to claim 15 , wherein the second nitride semiconductor layer contains aluminum.

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