JP2003029292A - Liquid crystal display device and electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a more inexpensive liquid crystal display device by making the range of mounting semiconductor chips for driving a liquid crystal small, thin, and compact. SOLUTION: On a liquid crystal display panel 16 wherein a transparent electrode on a COM (common electrode) side transparent substrate 502 is connected with an electrode terminal on a SEG (segmented electrode) side transparent substrate 501; all the electrode terminals are arranged on the SEG side transparent substrate; and a multi-layer substrate 14 with face down bonded liquid crystal driving semiconductor chips 4 are mounted as SEG side liquid crystal driving circuits, a power circuit integrated with a COM multi-layer substrate 608 integrating the liquid crystal driving semiconductor chips 4 as a COM side liquid crystal driving circuit with the power supply circuit is packaged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a plurality of liquid crystal driving semiconductor chips mounted thereon.

[0002]

2. Description of the Related Art Mounting of a liquid crystal driving driver IC in a conventional liquid crystal display device will be described with reference to FIGS.
The driver I will be described with reference to FIGS. 108 and 109.
C50041 is a tape carrier package (hereinafter TCP
It is mounted on 50042 and is connected to the panel 16 via a connecting member 19. The input wiring 50044 to the driver IC 50041 and the output wiring 50045 from the driver IC 50041 in the TCP 50042 are on the same substrate surface of 50042, and the connection with the panel 16 is the output wiring pattern 5 on the TCP 50042 substrate surface.
The tip portion 50046 of the 0045 and the panel terminal 18 are connected to each other using a connecting member 19.

Mounting of a liquid crystal driving driver IC in another conventional liquid crystal display device will be described with reference to FIGS. 106, 107, 108, 109, 110, and 111. The driver IC 50041 is TCP5.
Mounted on 0042, panel 16 and anisotropic conductive film 500
It is connected via 49. The input wiring 50044 to the driver IC 50041 and the output wiring 50045 from the driver IC 50041 in the TCP 50042 are on the same substrate surface of the TCP 50042, and the connection with the panel 16 is the tip portion 50046 of the output wiring pattern 50045 on the TCP 50042 substrate surface and the panel terminal. 500
18 is connected using an anisotropic conductive film 50049. The anisotropic conductive film 50049 is mainly composed of conductive particles 500.
50 and an adhesive 50051
The thickness (H) of 0051 is larger than the particle diameter (D) of the conductive particles 50050. This allows TCP50
When the thickness (K) of the tip end portion 50046 of the terminal 042 is larger than the particle diameter (D) of the conductive particles 50050, FIG.
The connection state as shown in 1 is established, and the conductive particles are crushed to establish conduction. However, when the thickness (k) of the connection terminal 13 is smaller than the particle diameter (D) of the conductive particles 50050 as shown in FIG. 112, the adhesive 500 is applied to the anisotropic conductive film 50049.
In this case, 51 is not sufficiently removed, and the electrical connection by the conductive particles 50050 cannot be established.

Further, the input wiring 50044 to the driver IC 50041 is connected to another board (hereinafter referred to as a bus board) 50043 for supplying an input signal and a power source by soldering. This bus board 50043 is a two-layer board and enables cross wiring of bus wiring. However, details of the wiring and the connecting portion are omitted in the drawing. Here, as shown in FIG. 108, TCP50042
, And the bus substrate 50043 are outside the panel outline, and the area related to semiconductor chip mounting is wide. In addition, the bus board is required as a separate component, which increases the cost. In addition, using FIG.
The (Chip On Glass) method will be described. FIG. 109 is a sectional view of a main part of a mounting portion of a semiconductor chip by the COG method. If the bus wiring 50048 is to be installed on the panel substrate, cross wiring with the input wiring 50047 to the driver IC 50041 for driving the liquid crystal must be performed on the panel substrate. Further, since the wiring uses a metal film thin film of Au, Ni or the like, it is necessary to widen the wiring width in order to reduce the resistance value. Therefore,
The area related to semiconductor chip mounting has become wider,
Since it is a metal thin film and the cross wiring process is performed, the cost is very high.

In a conventional liquid crystal display device, a display pixel is composed of a matrix electrode composed of row electrodes and column electrodes, and a TAB (Tape) arranged around the liquid crystal display element.
Connected the display drive signal of the mounted semiconductor element to the electrode terminal of the display element by an anisotropic conductive adhesive or a conductive rubber connector,
We are supplying.

113 and 114 show an example of a mounting structure of a liquid crystal display device in which a semiconductor element mounted by TAB is connected to a liquid crystal display element.

In the figure, TCP 5015 for driving liquid crystal
In No. 1, a semiconductor element 111 for driving a liquid crystal is mounted on a flexible wiring member 50152 by a so-called TAB method. The T provided on one side of the TCP50151
The CP output terminal 50153 is connected to the terminal portion of the liquid crystal display 110 with the anisotropic conductive adhesive 115, and the TCP input terminal 50154 and the drive control circuit board 5 provided on the other sides.
0155 is connected by soldering.

Further, the liquid crystal display panel in the conventional liquid crystal display device has a liquid crystal sandwiched between two as shown in FIG. 116 and FIG. 117 which is a sectional view taken along line EF of FIG.
Of the transparent substrates, for example, the common electrode (hereinafter referred to as COM) side transparent substrate 502 is longer than the segment electrode (hereinafter referred to as SEG) side transparent substrate 501, and is larger than the width of the COM side transparent substrate 502. Also, by making the width of the SEG-side transparent substrate 501 wider, the two transparent substrates 502 and 501 are superposed and the liquid crystal is sealed by the sealant 508, and the SEG-side transparent is formed up to the portion not overlapping with the other. The SEG transparent electrode 505 formed on the substrate 501 and the COM transparent electrode 506 formed on the COM-side transparent substrate 502 were extended and used as connection terminals with the liquid crystal drive circuit.

In the conventional liquid crystal display device, is a power supply circuit for supplying an image signal and a power supply to the liquid crystal driving semiconductor chip mounted on the TCP formed on the COM side bus substrate 50052 shown in FIG. 106? , Or a separate power supply circuit board is configured and soldered by using a tape electric wire, etc.
It was configured to be connected to the OM side bus board 50052.

[0010]

However, the above-mentioned prior art requires a separate wiring board (bus board) for supplying an input signal and a power source to the driver IC, or a cross wiring of metal thin films. Further, the mounting range is considerably wide, and it is difficult to provide an inexpensive and compact liquid crystal display device.

Therefore, the present invention has been made to solve the above-mentioned drawbacks.

An object of the invention is to provide a liquid crystal display device in which the mounting range of the liquid crystal driving semiconductor chip is small, thin, compact and inexpensive.

Further, according to the above-mentioned prior art, the liquid crystal driving semiconductor element 111 is mounted on the TC by the TAB mounting method.
In the P form, the liquid crystal display elements 110 are connected to the electrode terminals in a column order (parallel to the pixels and in order). A drive control circuit board 50155 for connecting the TCPs and supplying a liquid crystal drive power source and a control signal (hereinafter referred to as a bus line).
Connect to.

In the case of a liquid crystal display device having such a mounting structure, particularly in a color display device, triple pixel density is required to obtain the same resolution as black and white display. Therefore, the number of TCPs required is tripled. Become. Along with this, the number of TCP interconnections increases and the connection reliability decreases. Further, the wiring rule of the drive control circuit board 50155 becomes finer due to the increase in the number of terminals, and the board has to be multi-layered. Therefore, not only the liquid crystal display device cannot be downsized, but also the number of parts increases and the cost becomes high. Become.

Further, FIG. 115 is shown in JP-A-2-21482.
FIG. 7 is a diagram showing a structure of a conventional color liquid crystal display device disclosed in Japanese Patent Laid-Open No. 6-63, in which T
CP50151-1 to 50151-3 are mounted in three layers, but the connection points to the drive control circuit board 50155 are the same as in the structure shown in FIG. 98, and the number of connections increases due to the increase in pixel density, and connection defects cannot be reduced. . In addition, there is a problem in that the semiconductor element is bulged in the thickness direction and the size cannot be reduced by stacking the TCPs in multiple stages. Therefore,
The present invention is intended to solve the above-mentioned drawbacks, and an object of the present invention is to provide a liquid crystal display device having a structure which is inexpensive and can be miniaturized even in a color liquid crystal display device having high definition and high density pixels. It is to be.

Further, the above-mentioned conventional technique is shown in FIGS.
7, FIG. 108, FIG. 116, and FIG. 117, which are cross-sectional views of FIG. 116, two transparent substrates sandwiching the liquid crystal 509, for example, the SEG side transparent substrate 501 and the COM.
TCP corresponding to each of the side transparent substrates 502
TCP5004 because there is a terminal to mount 50042
2 is connected to the COM-side transparent substrate 502 and the SEG-side transparent substrate 501, first, the SEG-side transparent substrate 501 is T
A liquid crystal display panel 16 having a CP50042 mounted thereon and including a COM-side transparent substrate 502 and a SEG-side transparent substrate 501.
After flipping over, TCP50 on COM side transparent substrate 502
I had to implement 042. Also, TCP5
After mounting 0042, the UV-curable resin mold 21 is provided to protect the exposed portions of the transparent electrodes of the terminals of the COM-side transparent substrate 502 and the SEG-side transparent substrate 501.
However, since it is necessary to turn over after applying the SEG side TCP side and apply the COM side TCP side, the mold 21 of the UV curable resin applied on the SEG side TCP side is prevented from dripping. For SEG side T
After the UV-curable resin mold 21 is applied to the CP side, it is cured and then turned over and the UV-curable resin mold 21 is applied and cured to the COM side TCP side. It was necessary to devise such as making the mold 21 itself to have less dripping. For this reason, the process is complicated and the cost of the manufacturing apparatus and the product is increased. As a prior art for avoiding this problem, Japanese Utility Model Laid-Open No. 63-62823,
As disclosed in JP-A-3-233519, an upper substrate provided with an SEG electrode and a lower substrate provided with a COM electrode facing the SEG electrode and extending in a direction intersecting with each other are bonded to each other, and In a liquid crystal display device having a gap between both substrates filled with liquid crystal, an upper substrate is formed larger than a lower substrate, and an SEG electrode terminal is provided on the upper substrate, and a surface of the same upper substrate on which the SEG electrode terminal is provided. On the side, a COM electrode terminal is provided at a position corresponding to the COM electrode of the lower substrate, and a conductive material is provided outside the sealing material for enclosing the liquid crystal in the gap between the upper substrate and the lower substrate (on the side without the liquid crystal). , Connecting the COM electrode of the lower substrate and the COM electrode terminal of the upper substrate. However, in these prior arts, since the conductive material that connects the electrode of the lower substrate and the electrode terminal of the upper substrate is outside the sealing material that encloses the liquid crystal, that is, on the side without the liquid crystal, the conductive material directly contacts the air. Corrosion or problems such as corrosion of the conductive material due to the use of chemicals in the liquid crystal display manufacturing process are likely to occur.
Also, in order to prevent this, even if it is protected with a resin mold, etc., a space is likely to be created around the conductive material, and the resin etc. completely surrounds the conductive material, and the conductive material and air or the conductive material and chemicals There is a problem that it is difficult to completely cut off the contact.

Furthermore, since the conventional liquid crystal display device has a separate power supply circuit, a step of connecting the power supply circuit is required, and the electric wire connecting the power supply circuit and the liquid crystal display device tends to be long, There is a drawback that noise easily enters from the outside to the power supply and the image signal.

An object of the present invention is to provide a liquid crystal display device which solves the above-mentioned drawbacks, enables simplification and automation of the manufacturing process of the liquid crystal display device, has high display quality, is compact and is inexpensive.

[0019]

A liquid crystal display device of the present invention has a semiconductor chip for driving a liquid crystal mounted on the surface of a multilayer substrate,
At least the surface of the multi-layer substrate having the input wiring pattern to the chip and the output wiring pattern from the chip,
A back surface having terminals connected to the terminals of the liquid crystal panel and at least one intermediate layer is provided between the front surface and the back surface, and the input wiring or the output wiring or a part of both wirings is provided in the intermediate layer. A multi-layer substrate, which is provided as a wiring pattern and has respective wirings connected through through holes, is electrically connected to a panel terminal, and the plurality of multi-layer substrates are electrically connected by a conductive connecting means. Is characterized by.

The liquid crystal display device of the present invention is characterized by using a multi-layer substrate on which a power supply circuit and a liquid crystal driving integrated circuit are mounted.

Further, in the liquid crystal display device of the present invention, the electrode on one transparent substrate of the two transparent substrates constituting the liquid crystal display panel is connected to the electrode on the other transparent substrate, and the other transparent substrate. It is characterized in that a connection terminal for connecting the liquid crystal drive circuit is formed only on.

Further, in the liquid crystal display device of the present invention, of the two transparent substrates constituting the liquid crystal display panel, the electrode on one transparent substrate is connected to the electrode on the other transparent substrate, and the other transparent substrate is connected. In a liquid crystal display panel in which a connection terminal for connecting a liquid crystal drive circuit is formed, a means for connecting an electrode on one transparent substrate to an electrode on another transparent substrate is provided between two transparent substrates. It is characterized by using a conductive material which also serves as a sealing material for enclosing the sandwiched liquid crystal.

Further, the liquid crystal display device of the present invention is characterized in that a substrate for supplying power and signals is installed at a corner portion of the liquid crystal display panel where the X-side drive circuit and the Y-side drive circuit are in contact with each other. To do.

[0024]

According to the structure of the liquid crystal display device of the present invention,
By forming bus lines and connection terminals on a multi-layer substrate, mounting multiple semiconductor elements on them, and connecting them to the electrodes of the display element, the drive control circuit board becomes unnecessary and the number of semiconductor elements can be reduced. Performance is improved and the device can be downsized.

[0025]

[Embodiment 1] This embodiment will be described below with reference to FIGS. 1, 2, 3, and 4.

FIG. 1 is an exploded perspective view of a multilayer substrate of one embodiment in which a liquid crystal driving semiconductor chip is face-down bonded to the surface of the multilayer substrate in the liquid crystal display device of the present invention.

Reference numerals 1, 2, and 3 are layers of the multi-layer (three-layer) substrate of this embodiment, 1 is a first layer, 2 is a second layer, and 3 is a third layer. The chip 4 is formed on the first layer 1 by a known method (for example, a method of connecting a semiconductor Au bump to a substrate using Ag paste, a method of using an anisotropic conductive film, a flip chip method of using a solder bump, etc.). Is face-down bonded to the surface of. After bonding, a mold 20 is provided around the liquid crystal driving semiconductor chip 4 and between the liquid crystal driving semiconductor chip 4 and the surface of the first layer 1 for corrosion prevention and reinforcement. The molding material may be epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound thereof, and may be a solvent type, a thermosetting type, a photocuring type, or a combination thereof. On the surface of the first layer 1, the input wiring 5 corresponding to the input pad of the liquid crystal driving semiconductor chip 4 is patterned. Further, the input wiring 5 is connected to the bus wiring 10 of the second layer 2 through the through hole 6. Further, a land 7 is formed at the tip of the input wiring 5 for wire bonding with another adjacent similar multilayer substrate.

On the surface of the first layer 1, output wirings 8 corresponding to the output pads of the liquid crystal driving semiconductor chip 4 are patterned. Here, since the panel terminal pitch is larger than the output pad pitch of the liquid crystal driving semiconductor chip 4, the pattern is widened and wired on the first layer 1 so that the respective output pads correspond to the panel terminals. ing. Further, a through hole 9 is formed at the tip of the output wiring 8, passes through the through hole 11 of the second layer 2, and through the through hole 12 of the third layer 3, the connection terminal 1 to the panel is formed.
Connected to 3.

Each of the first layer 1, the second layer 2 and the third layer 3 is a low temperature co-fired ceramic substrate of alumina base material. The thickness of each was 0.25 mm. The input wiring 5, the output wiring 8, and the bus wiring 10 are Au, A
It is a fired product of a metal paste such as g, AgPd, or Cu.
Further, the through holes 6, 9, 11, 12 are also Au,
It is a fired product of a metal paste such as Ag, AgPd, or Cu. Similarly, the land 7 and the connection terminal 13 are Au, A
It is a fired product of a metal paste such as g, AgPd, or Cu.
Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually about 0.001 mm to 0.05 mm, but in order to reduce the resistance value, it is 0.05 mm to 0.2 mm.
You may make it about.

However, the input wiring 5 on the surface of the first layer 1,
Depending on the wiring pitch, dimensional accuracy, etc., the land 7, the output wiring 8, and the connection terminals 13 on the back surface of the third layer 3 may be Au, A
A pattern may be formed by photolithography or the like after the entire surface of a metal paste such as g, AgPd, or Cu is printed. The pattern thickness at this time is about 0.001 mm to 0.2 mm. Alternatively, instead of the printing method, after vapor deposition of Au, Ag, Cu, etc., or thin film formation by sputtering etc., photolithography,
You may form a pattern by processes, such as plating. The pattern thickness at this time is about 0.0005 mm to 0.1 mm.

Since the ceramic substrate after firing has excellent dimensional stability against temperature and humidity, the connecting portion between the liquid crystal driving semiconductor chip 4 and the multilayer substrate 14 and the multilayer substrate 1
The connection reliability of the connection portion between the connection terminal 13 of No. 4 and the panel terminal 18 is high.

A glass epoxy plate, which is a composite material of glass fiber and epoxy resin, may be used as a separate material for the first layer 1, the second layer 2 and the third layer 3. . Here, a glass epoxy plate having a thickness of 0.1 mm was used, but a glass epoxy plate having a thickness of about 0.05 mm to 0.8 mm can be used. Each of the input wiring 5, the output wiring 8, the bus wiring 10, the land 7, and the connection terminal 13 is formed by patterning a metal such as copper by a known subtractive method or an additive method for each layer, and the through holes 6, 9,
Reference numerals 11 and 12 are formed of a metal such as copper by a known plating method or the like, or formed by stacking each layer. Thickness of patterned metal is 0.001mm to 0.035m
Although it is about m, in order to cope with low resistance and large current,
It may be about 0.035 mm to 0.2 mm. Each wiring Input wiring 5, Output wiring 8, Bus wiring 10, Land 7, Connection terminal 13, Through holes 6, 9, 11, 1
The surface of 2 is Ni, Au, Cr, Co, Pd, Sn, P
The plating treatment of b, In or the like may be performed alone or in combination, and the plating thickness is about 0.00005 mm to 0.05 mm. When the glass epoxy plate is used, the thickness can be made thinner than the ceramic substrate, and the material used, the manufacturing process, etc. are general and the cost is low. In addition to the glass fibers, a composite material of aramid fibers or a mixed material thereof, and a polyimide resin or a BT (bismaleide triazine) resin in addition to the epoxy resin may be used.

Furthermore, each of the first layer 1, the second layer 2 and the third layer 3 is made of polyimide (P
I), polyethylene terephthalate (PET), polyether sulfone (PES), polycarbonate (P
C), polyester (PS), cellulose triacetate (TA
C), polysulfone (PS), acrylic, epoxy,
An organic resin film made of polyether ether ketone (PEEK), polyarylate, or the like or a composite of some of them may be used. Here, a polyimide film having an organic resin film thickness of 0.025 mm was used, but the film thickness was 0.001 mm to 0.5.
The thing of about mm can be used. Each of the input wiring 5, the output wiring 8, the bus wiring 10, the land 7, and the connection terminal 13 is formed by patterning a metal such as copper for each layer by a known subtractive method or an additive method, and through holes 6, 9, 11, 12 is formed of a metal such as copper by a known plating method or the like for each layer or after superimposing each layer.
Alternatively, a metal foil such as copper coated with PI (a known casting method or the like) may be similarly patterned and laminated. Thickness of patterned metal is 0.001mm
Is about 0.035 mm, but it may be about 0.035 mm to 0.2 mm in order to cope with low resistance and large current. Each wiring 5, 8, 10, land 7,
The surfaces of the connection terminal 13 and the through holes 6, 9, 11, 12 are Ni, Au, Cr, Co, Pd, Sn, Pb, In.
The plating thickness may be 0.0001 mm to 0.05 m.
It is about m. When the organic resin film is used, the thickness can be made thinner than the ceramic substrate, the glass epoxy plate, etc., the connection with the panel terminal 18 by the connection member 19 can be facilitated, and the connection reliability and the connection process can be simplified.

FIG. 2 shows an embodiment in which the multilayer substrate of the embodiment shown in FIG. 1 is connected to a liquid crystal display panel.

FIG. 3 is an enlarged view of the main part of the connection portion shown in FIG.

FIG. 4 shows a cross section of the main part of the connection portion of FIG.

A liquid crystal display type panel (for example, 640 * 48)
16 are connected to the panel terminals 18 in the X-side and five in the Y-side, respectively. However, in FIG. 2, 12 on the X side and 5 on the Y side are not shown. Terminal 13 of multilayer board 14
The panel terminal 18 and the panel terminal 18 are connected by a connecting member 19. The connecting member 19 not only secures electrical connection but also serves to fix the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., or a mixture of some of them, alloy, or composite metal particles by plating, etc., N in plastic particles (polystyrene, polycarbonate, acrylic, etc.)
i, Co, Pd, Au, Ag, Cu, Fe, Sn, Pb
And the like, or particles obtained by plating some of them, carbon particles, and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. When this anisotropic conductive film is disposed between the panel terminal 18 and the connection terminal 13 of the multilayer substrate 14 and the anisotropic conductive film is a thermosetting type or a blend type of thermoplastic and thermosetting type, Are hardened and connected by pressing a heating and pressing head against the multilayer substrate 14. When a UV curable type is used for this anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminal 18 (glass side) side to cure. Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles may be solder particles, Ni, Au, Ag, Cu, Pb, Sn, etc. alone or a mixture of some of them, alloys, or composite metal particles by plating or the like, plastic particles (polystyrene, polycarbonate, acrylic, etc.) and Ni. , Co, P
These are particles of d, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive adhesive is in a liquid or paste form, and the panel terminal 18 is formed by a known method such as a printing method or a dispensing method using a dispenser.
Place it on the connection part of. When a thermosetting type or a blend type of thermoplastic and thermosetting type is used for the anisotropic conductive adhesive, the heating and pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive adhesive, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminal 18 (glass side) side to cure.

A mold 21 is provided to protect the exposed portion of the panel terminal 18 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. This mold material is epoxy, acrylic,
Urethane, polyester, etc. may be used alone or as a mixture or compound thereof, and may be solvent type, thermosetting type, photocuring type or the like or a combination thereof.

The connection of the bus wiring between the adjacent multilayer substrates 14 is wire-bonded by the wire 15 via the land 7. As wire 15, Au, A
l, Cu and other metals or alloys of these metals (Be, S
i, Mg, etc. are also included). The width to be wire-bonded is within the width of the multi-layer substrate, and the panel 16 is compactly mounted within the outer shape of the panel 16 as shown in FIG.

The connecting member 19 used here is shown in FIG.
The anisotropic conductive film as shown in 1 may be used, and mainly the conductive particles 3
2 and the adhesive 33, and the thickness (h) of the adhesive 33 is smaller than the particle diameter (d) of the conductive particles 32. Further, as shown in FIG. 22, the anisotropic conductive film 31 may be formed on the separator 34 (sheet (film) such as Teflon (registered trademark), PET, paper, etc.).
The conductive particles 32 are solder particles, Ni, Au, Ag, C
Composite metal particles such as u, Pb, Sn, etc., mixed or plural, alloys, or plated metal particles, plastic particles (polystyrene, polycarbonate, acrylic, etc.) with Ni,
Particles such as Au, Cu, and Fe plated individually or in plural, carbon particles, etc., having a particle diameter (d) of 0.001
It is about mm to 0.020 mm. The adhesive 27 is styrene butadiene styrene (SBS).
It is an adhesive agent of single type, epoxy type, acrylic type, polyester type, urethane type, etc., or a mixture or a plurality of types thereof, and a thickness (h) is 0.0005 mm to 0.018.
It is about mm.

This anisotropic conductive film 31 is disposed between the panel terminal 18 and the connection terminal 13 of the multilayer substrate 14, and the anisotropic conductive film 31 is thermosetting or a blend type of thermoplastic and thermosetting. When the above adhesive is used, the heating and pressing head is pressed against the multi-layer substrate 14 to effect curing connection. When a UV curable type adhesive is used for the anisotropic conductive film 31, a pressure head is pressed against the multilayer substrate 14 and UV irradiation is applied from the panel terminal 18 (glass side) side to cure and connect. is doing. Even when the thickness (k) of the connection terminal 13 of the multilayer substrate 14 is smaller than the particle diameter (d) of the conductive particles 32 (particularly remarkable when the connection terminal pitch is 0.1 mm or less), the adhesive 33 is sufficient. Since the panel terminal 18 and the connection terminal 13 of the multi-layer substrate 14 are electrically connected by the conductive particles 32, the panel terminal 18 and the connection terminal 13 are securely connected (see FIG. 24). The adhesive 33 holds this connection state, and secures sufficient connection reliability.

As another connecting member, as shown in FIG. 23, a liquid or paste-like anisotropic conductive adhesive 35 containing conductive particles 32 and an adhesive 33 is used as a printing method, a dispensing method using a dispenser, etc. It is arranged at the connecting portion of the panel terminal 18 by the above method. At this time, the anisotropic conductive adhesive 35 is controlled in viscosity and thixotropy so that the thickness (h) of the adhesive 33 becomes smaller than the particle diameter (d) of the conductive particles 32. By a method similar to the pressure-bonding connection of the film, connection with high connection reliability can be performed as shown in FIG.

A mold 21 is provided to protect the exposed portion of the panel terminal 18 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material may be epoxy, acrylic, urethane, polyester, etc., or a mixture or compound of some of them, and may be a solvent type, a thermosetting type, a photocuring type or a combination thereof.

The connection of the bus wiring between the adjacent multilayer substrates 14 is wire-bonded by the wire 15 via the land 7. As wire 15, Au, A
l, Cu and other metals or alloys of these metals (Be, S
i, Mg, etc. are also included). The width to be wire-bonded is within the width of the multi-layer substrate, and the panel 16 is compactly mounted within the outer shape of the panel 16 as shown in FIG.

As described above, by using the multi-layer substrate of this embodiment, the cross wiring of the bus wiring is conventionally performed by using another bus substrate in the TAB method, but the cross wiring is performed in the same multi-layer substrate. It has been processed. Therefore,
By making the wiring in the board high density, it is possible to make it more compact than the TAB method, and it is possible to reduce the cost because another bus board is not used.

Further, in the conventional COG method, since the bus wiring is cross-wired on the panel substrate, a large area for the bus wiring is required, and a metal wiring is required to reduce the wiring resistance value, and the cost is reduced. While it becomes high,
By using the multilayer substrate of this embodiment, it is possible to save the bus wiring area and reduce the cost as compared with the COG method.

[Embodiment 2] This embodiment will be described with reference to FIG.

FIG. 5 is an exploded perspective view showing a multilayer substrate of one embodiment in which a liquid crystal driving semiconductor chip is wire-bonded to the surface of the multilayer substrate in the liquid crystal display device of the present invention.

On the surface of the first layer 1 of the multi-layer substrate, the input wiring 5 corresponding to the input / output pads of the liquid crystal driving semiconductor chip 4 is formed.
And a land 22 for wire bonding on the output wiring 8.
Are formed. Others, patterns, through holes,
The method of forming the multilayer substrate, the configuration, and the structure are the same as in the first embodiment.

The back surface of the liquid crystal driving semiconductor chip is fixed to the front surface of the multi-layer substrate, and the land 22 on the front surface of the first layer 1 of the multi-layer substrate corresponding to each of the input / output pads of the liquid crystal driving semiconductor chip 4 is wire-bonded. . Wire 23
The same one as that used for connection between the multi-layered substrates of the first embodiment can be used. Although not shown, the bonding portion and the wire portion are molded for protection and reinforcement as in the first embodiment.

Furthermore, the connection of the bus wiring between the adjacent multi-layer substrates is wire-bonded as in the first embodiment. Similarly, although not shown, the bonding portion and the wire portion are molded for protection and reinforcement as in the first embodiment.

As described above, even by using the multilayer substrate of this embodiment, the conventional TAB system and COG system are
Similar to the first embodiment, it is possible to reduce the size and cost. [Embodiment 3] This embodiment will be described with reference to FIG.

In the liquid crystal display device of the present invention, as shown in FIG. 6, the multilayer substrate 14 in which the liquid crystal driving semiconductor chip 4 is face-down bonded to the surface of the multilayer substrate is anisotropically connected to the panel terminal 18 of the liquid crystal display panel. The conductive conductive film 19 is used for connection. The main part of the connecting portion is the same as that in FIG. 4 of the first embodiment. However, the tip of the input wiring of the first layer 1 of the multilayer substrate is not a land for wire bonding but has a shape suitable for heat sealing or for connecting a flexible substrate.

The connection of the bus wiring between the adjacent multi-layered boards 14 is made by using the connection board 24. Connection board 24
A heat seal or a flexible substrate can be used as the material.

The width to which the connection board 24 is connected is the multilayer board 1
4, and is similarly compactly mounted so that it fits within the outer shape of the panel 16 as shown in FIG. 4 of the first embodiment.

As described above, by using the multi-layer substrate of this embodiment, the conventional TAB system and COG system are
Similar to the first embodiment, it is possible to reduce the size and cost. Further, regarding the connection of the liquid crystal driving semiconductor chip to the surface of the multi-layer substrate and the electrical connection between the adjacent multi-layer substrates, it is also possible to use the combinations shown in Examples 1, 2, and 3 in combination. In each case, it is possible to make the device compact and reduce the price.

In addition, mounting the semiconductor chip used in this embodiment on a multi-layer substrate and mounting the multi-layer substrate on another display device or electronic printing device can be performed by changing the semiconductor chip type to a semiconductor chip for driving a plasma display. , Or by changing to an EL driving semiconductor chip, the same can be applied to a plasma display or an EL display device. Also, a semiconductor chip for driving a thermal head is similarly mounted on a multi-layer substrate, and the multi-layer substrate is similarly connected to the thermal head, so that the electronic printing apparatus can be applied.

[Embodiment 4] This embodiment will be described with reference to FIGS. 4, 7, 8, 9, and 10.

FIG. 7 is an exploded perspective view showing a multilayer substrate of another embodiment in which a liquid crystal driving semiconductor chip is face-down bonded to the surface of the multilayer substrate in the liquid crystal display device of the present invention.

Reference numerals 1, 2 and 3 are layers of the multi-layer (three-layer) substrate of this embodiment, 1 is a first layer, 2 is a second layer, and 3 is a third layer. The chip 4 is formed on the surface of the first layer 1 by a known method (for example, a method of connecting a semiconductor Au bump to a substrate using Ag paste, a method of using an anisotropic conductive film, a flip chip method by soldering, etc.). Is face-down bonded to. After bonding, a mold 20 is provided around the liquid crystal driving semiconductor chip 4 and between the liquid crystal driving semiconductor chip 4 and the surface of the first layer 1 for corrosion prevention and reinforcement. The molding material may be epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound thereof, and may be a solvent type, a thermosetting type, a photocuring type, or a combination thereof. On the surface of the first layer 1, the input wiring 5 corresponding to the input pad of the liquid crystal driving semiconductor chip 4 is patterned. The input wiring 5 is connected to the bus wiring 10 of the second layer 2 via the through hole 6 and the through hole 25. further,
It is connected to the connection terminal 27 on the back surface of the third layer through the through hole 26 of the third layer. This connection terminal 27
Has an appropriate shape, size, and thickness so as to be connected to the connection terminal 29 of the bus wiring 28 on the panel, and is approximately at a right angle to the side of the multilayer substrate 14 on which the connection terminals 13 with the panel are arranged. It is arranged on the side that has become. Although a single-row array is shown in the figure, a plurality of arrays may be provided.

On the surface of the first layer 1, the output wiring 8 corresponding to the output pad of the liquid crystal driving semiconductor chip 4 is patterned. Here, since the panel terminal pitch is larger than the output pad pitch of the liquid crystal driving semiconductor chip 4, the pattern is widened and wired on the first layer 1 so that the respective output pads correspond to the panel terminals. ing. Further, a through hole 9 is formed at the tip of the output wiring 8, passes through the through hole 11 of the second layer 2, and through the through hole 12 of the third layer 3, the connection terminal 1 to the panel is formed.
Connected to 3. Here, an example of a method of matching the pad pitch of the semiconductor chip and the terminal pitch of the panel in the multi-layer substrate of three layers is shown, but the matching may be performed not only in one layer but also in a plurality of layers (two or more layers).

The first layer 1, the second layer 2 and the third layer 3 are low temperature co-fired ceramic substrates of alumina base material. The thickness of each was 0.25 mm. The input wiring 5, the output wiring 8, and the bus wiring 10 are Au, A
It is a fired product of a metal paste of g, AgPd, Cu, etc. alone or some of their composites. Further, the through holes 6, 9, 11, 12, 25, 26 are similarly made of Au, Ag,
It is a fired product of a metal paste such as AgPd or Cu. The connection terminals 13 and 27 are also made of Au, Ag and AgP.
It is a fired product of a metal paste of d, Cu, etc. alone or some of their composites. Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually about 0.001 mm to 0.05 mm, but in order to reduce the resistance value,
It may be about 05 mm to 0.2 mm.

However, the input wiring 5 on the surface of the first layer 1,
The output wiring 8 and the connection terminals 13 and 2 on the back surface of the third layer 3
7 is Au, Ag, depending on the wiring pitch, dimensional accuracy, etc.
The pattern may be formed by photolithography or the like after printing the entire surface of a metal paste of AgPd, Cu or the like or a composite thereof. The pattern thickness at this time is 0.00
It is about 1 mm to 0.2 mm. Alternatively, instead of the printing method, a thin film may be formed by vapor deposition of Au, Ag, Cu or the like, sputtering, or the like, and then pattern formation may be performed by a process such as photolithography or plating. The pattern thickness at this time is 0.0
It is about 005 mm to 0.1 mm.

FIG. 8 is an exploded view of a main part for connecting the multilayer substrate of the embodiment shown in FIG. 7 to a liquid crystal display panel. Further, the cross section of the main part of the connection portion (xx cross section in FIG. 8) is as shown in FIG. 4 as in the first embodiment. In the panel 16, the connection terminal 18 and the bus wiring 28 are formed on the panel and the connection terminal 29 is patterned at the end of the panel 16 corresponding to the portion where the multilayer substrate 14 is mounted. In FIG. 8, a straight line pattern is shown, but it is also possible to effectively pattern the wiringable area to the full in consideration of lowering resistance such as wiring resistance and connection resistance. The bus wiring 28 on the panel functions as a bus wiring connecting the multi-layer substrates.

FIG. 9 is almost the same as the embodiment of FIG.
The connection terminals 13 of the multilayer substrate 14 are arranged inside the panel 16. The cross section of the main part of the connecting portion (y-y cross section in FIG. 9) is as shown in FIG. 10, and the wiring length from the panel terminal 18 to the inside of the panel is shorter than that of the embodiment of FIG. 4, and the wiring resistance value is reduced. effective.

The connection terminal 13 and the panel terminal 18, and the connection terminal 27 and the panel terminal 29 of the multilayer substrate 14 are connected by the connection member 19. Connection member 19
Secures electrical connection and at the same time fixes the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., or a mixture of some of them, alloy, or composite metal particles by plating, etc., N in plastic particles (polystyrene, polycarbonate, acrylic, etc.)
i, Co, Pd, Au, Ag, Cu, Fe, Sn, Pb
And the like, or particles obtained by plating some of them, carbon particles, and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive film is arranged between the panel terminal 18 and the connection terminals 13 and 27 of the multilayer substrate 14, and the anisotropic conductive film is of thermosetting type or blend type of thermoplastic and thermosetting type. In some cases, a heating / pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminals 18, 29 (glass side) side to cure. The shape of this pressure head is changed to the connection terminals 13 and 27.
If the U-shaped unitary body or a plurality of U-shaped bodies is formed in accordance with the arrangement shape, the input / output terminals of the multi-layer substrate 14 can be collectively connected to the panel terminals 18 and 29 in one pressing step.

Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb,
Ni, C in Sn, etc. alone or in a mixture of some of them, alloys, composite metal particles by plating, etc., plastic particles (polystyrene, polycarbonate, acrylic, etc.)
These are particles of o, Pd, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 16 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting type or a blend type of thermoplastic and thermosetting type is used for the anisotropic conductive adhesive, the heating and pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive adhesive, a pressure head is pressed against the multilayer substrate 14 and UV irradiation is performed from the panel terminals 18, 29 (glass side) side to cure. If the shape of the pressure head is made into a U-shape or a plurality of bodies according to the arrangement shape of the connection terminals 13 and 27, the input / output terminals of the multi-layer substrate 14 can be converted into the panel terminals 18 in a single pressure step. , 29
You can connect with each at once.

A mold 21 is provided to protect the exposed portions of the panel terminals 18, 28 and 29 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material is epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound of some of them, and is a solvent type, a thermosetting type, a photocuring type or the like or a combination type thereof.

As shown in FIG. 4, the panel 16 is compactly mounted so that it fits within the outer shape of the panel 16.

As described above, the bus wiring is formed on the panel as a means for establishing continuity between the multi-layered boards, because the bus wiring is formed simultaneously with other wiring patterns of the panel.
No additional steps are needed. Also, no separate parts such as heat seal are required. Further, since the input / output terminals can be collectively connected, the number of connecting steps can be reduced.

[Embodiment 5] This embodiment will be described with reference to FIGS. 4, 10, 11, 12, 13, and 14.

FIG. 11 shows the liquid crystal display device of the present invention.
FIG. 6 is a perspective view showing an exploded view of a multilayer substrate of another embodiment in which a liquid crystal driving semiconductor chip is face-down bonded on the surface of the multilayer substrate.

Reference numerals 1, 2 and 3 are layers of the multi-layer (three-layer) substrate of this embodiment, 1 is a first layer, 2 is a second layer, and 3 is a third layer. The chip 4 is formed on the surface of the first layer 1 by a known method (for example, a method of connecting a semiconductor Au bump to a substrate using Ag paste, a method of using an anisotropic conductive film, a flip chip method by soldering, etc.). Is face-down bonded to. After bonding, a mold 20 is provided around the liquid crystal driving semiconductor chip 4 and between the liquid crystal driving semiconductor chip 4 and the surface of the first layer 1 for corrosion prevention and reinforcement. The molding material may be epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound thereof, and may be a solvent type, a thermosetting type, a photocuring type, or a combination thereof. On the surface of the first layer 1, the input wiring 5 corresponding to the input pad of the liquid crystal driving semiconductor chip 4 is patterned. The input wiring 5 is connected to the bus wiring 10 of the second layer 2 via the through hole 6 and the through hole 25. further,
The bus wiring 10 is connected to the through hole 30 of the second layer 2, and further connected to the connection terminal 27 on the back surface of the third layer via the through hole 30 and the through hole 26 of the third layer. . The connection terminals 27 are arranged in the same arrangement as the connection terminals 13. The shape, size and thickness are also similar. In FIG. 11, the connection terminals 13 and 27 are shown to have the same shape and the same pitch, but they may be different within each terminal or between the terminals. Although the through holes 13 and 26 are shown as arranged in one line, they may be arranged in a plurality of lines.

On the surface of the first layer 1, the output wiring 8 corresponding to the output pad of the liquid crystal driving semiconductor chip 4 is patterned. Here, since the panel terminal pitch is larger than the output pad pitch of the liquid crystal driving semiconductor chip 4, the pattern is widened and wired on the first layer 1 so that the respective output pads correspond to the panel terminals. ing. Further, a through hole 9 is formed at the tip of the output wiring 8, passes through the through hole 11 of the second layer 2, and through the through hole 12 of the third layer 3, the connection terminal 1 to the panel is formed.
Connected to 3. Here, an example of a method of matching the pad pitch of the semiconductor chip and the terminal pitch of the panel in the multi-layer substrate of three layers is shown, but the matching may be performed not only in one layer but also in a plurality of layers (two or more layers).

Each of the first layer 1, the second layer 2 and the third layer 3 is an alumina-based low temperature co-fired ceramic substrate. The thickness of each was 0.25 mm. The input wiring 5, the output wiring 8, and the bus wiring 10 are Au, A
It is a fired product of a metal paste of g, AgPd, Cu, etc. alone or some of their composites. Further, the through holes 6, 9, 11, 12, 25, 26, 30 are similarly Au,
It is a fired product of a metal paste such as Ag, AgPd, or Cu. Similarly, the connection terminals 13 and 27 are also Au, Ag, and A.
It is a fired product of a metal paste of gPd, Cu, etc. alone or some of their composites. Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually about 0.001 mm to 0.05 mm, but it may be about 0.05 mm to 0.2 mm in order to reduce the resistance value.

However, the input wiring 5 on the surface of the first layer 1,
The output wiring 8 and the connection terminals 13 and 2 on the back surface of the third layer 3
7 is Au, Ag, depending on the wiring pitch, dimensional accuracy, etc.
The pattern may be formed by photolithography or the like after printing the entire surface of a metal paste of AgPd, Cu or the like or a composite thereof. The pattern thickness at this time is 0.00
It is about 1 mm to 0.2 mm. Alternatively, instead of the printing method, a thin film may be formed by vapor deposition of Au, Ag, Cu or the like, sputtering, or the like, and then pattern formation may be performed by a process such as photolithography or plating. The pattern thickness at this time is 0.0
It is about 005 mm to 0.1 mm.

FIG. 12 is an exploded view of a main part for connecting the multilayer substrate of the embodiment shown in FIG. 11 to a liquid crystal display panel. Further, the cross section of the main part of the connection portion (XX cross section in FIG. 12) is as shown in FIG. 4 as in the first embodiment. Panel 16
In, in correspondence with the portion where the multilayer substrate 14 is mounted,
The connection terminal 18 and the bus wiring 28 are patterned on the panel, and the connection terminal 29 is patterned at the end thereof. Connection terminal 1
8 and 29 are arranged on a straight line. In FIG. 12, the bus wiring 28 is simply indicated by a solid line, but the pattern width and the like are changed in consideration of the wiring resistance, the connection resistance, and the like to make the resistance value between the wirings uniform. The bus wiring 28 on the panel functions as a bus wiring connecting the multi-layer substrates.

The connection terminal 13 and the panel terminal 18, and the connection terminal 27 and the panel terminal 29 of the multilayer substrate 14 are connected by the connection member 19. Connection member 19
Secures electrical connection and at the same time fixes the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., or a mixture of some of them, alloy, or composite metal particles by plating, etc., N in plastic particles (polystyrene, polycarbonate, acrylic, etc.)
i, Co, Pd, Au, Ag, Cu, Fe, Sn, Pb
And the like, or particles obtained by plating some of them, carbon particles, and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive film is arranged between the panel terminal 18 and the connection terminals 13 and 27 of the multilayer substrate 14, and the anisotropic conductive film is of thermosetting type or blend type of thermoplastic and thermosetting type. In some cases, a heating / pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminals 18, 29 (glass side) side to cure. Since the connection terminals 13 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Also, 1
The input / output terminals of the multi-layer substrate 14 can be collectively connected to the panel terminals 18 and 29 by a single pressing step.

Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb,
Ni, C in Sn, etc. alone or in a mixture of some of them, alloys, composite metal particles by plating, etc., plastic particles (polystyrene, polycarbonate, acrylic, etc.)
These are particles of o, Pd, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 18 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting type or a blend type of thermoplastic and thermosetting type is used for the anisotropic conductive adhesive, the heating and pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive adhesive, a pressure head is pressed against the multilayer substrate 14 and UV irradiation is performed from the panel terminals 18, 29 (glass side) side to cure. This connection terminal 1
Since 3 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Further, the input / output terminals of the multi-layer substrate 14 can be connected to the panel terminals 18 and 29 collectively by one pressing step.

A mold 21 is provided to protect the exposed portions of the panel terminals 18, 28 and 29 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material is epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound of some of them, and is a solvent type, a thermosetting type, a photocuring type or the like or a combination type thereof.

As shown in FIG. 4, the panel 16 is compactly mounted so that it fits within the outer shape of the panel 16.

As described above, the bus wiring is formed on the panel as a means for establishing continuity between the multi-layered boards, because the bus wiring is formed at the same time as other wiring patterns of the panel.
No additional steps are needed. Also, no separate parts such as heat seal are required. Further, since the input / output terminals can be collectively connected, the number of connecting steps can be reduced.

FIG. 13 is almost the same as the embodiment of FIG. 12, but the connection terminals 13 of the multilayer substrate 14 are arranged inside the panel 16. A cross section of the main part of the connection portion (Y in FIG. 13)
The (-Y cross section) is as shown in FIG. 10, and the wiring length from the panel terminal 18 to the inside of the panel is shorter than that of the embodiment of FIG. 4, which has the effect of reducing the wiring resistance value.

The connection terminal 13 and the panel terminal 18, and the connection terminal 27 and the panel terminal 29 of the multilayer substrate 14 are connected by the connection member 19. Connection member 19
Secures electrical connection and at the same time fixes the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., or a mixture of some of them, alloy, or composite metal particles by plating, etc., N in plastic particles (polystyrene, polycarbonate, acrylic, etc.)
i, Co, Pd, Au, Ag, Cu, Fe, Sn, Pb
And the like, or particles obtained by plating some of them, carbon particles, and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive film is arranged between the panel terminal 18 and the connection terminals 13 and 27 of the multilayer substrate 14, and the anisotropic conductive film is of thermosetting type or blend type of thermoplastic and thermosetting type. In some cases, a heating / pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminals 18, 29 (glass side) side to cure. Since the connection terminals 13 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Also, 1
The input / output terminals of the multi-layer substrate 14 can be collectively connected to the panel terminals 18 and 29 by a single pressing step.

Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb,
Ni, C in Sn, etc. alone or in a mixture of some of them, alloys, composite metal particles by plating, etc., plastic particles (polystyrene, polycarbonate, acrylic, etc.)
These are particles of o, Pd, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 18 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting type or a blend type of thermoplastic and thermosetting type is used for the anisotropic conductive adhesive, the heating and pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive adhesive, a pressure head is pressed against the multilayer substrate 14 and UV irradiation is performed from the panel terminals 18, 29 (glass side) side to cure. This connection terminal 1
Since 3 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Further, the input / output terminals of the multi-layer substrate 14 can be connected to the panel terminals 18 and 29 collectively by one pressing step.

A mold 21 is provided to protect the exposed portions of the panel terminals 18, 28 and 29 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material is epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound of some of them, and is a solvent type, a thermosetting type, a photocuring type or the like or a combination type thereof.

As shown in FIG. 10, the panel 16 is compactly mounted so that it fits within the outer shape of the panel 16.

As described above, the bus wiring is formed on the panel as a means for establishing continuity between the multi-layered boards, because the bus wiring is formed at the same time as other wiring patterns of the panel.
No additional steps are needed. Also, no separate parts such as heat seal are required. Further, since the input / output terminals can be collectively connected, the number of connecting steps can be reduced.

FIG. 14 is almost the same as the embodiment of FIG. 12, but the bus wiring 28 on the panel is wired not only in the area where the multilayer substrate 14 is mounted but also in the area inside the panel which does not affect the display. ing. Therefore, the bus wiring 28
It is possible to increase the bus wiring width without increasing the mounting area of the multilayer substrate 14 so that the area that can be used for the wiring becomes wider and the wiring resistance value becomes smaller. Here, reducing the resistance value of the bus wiring has the effect of improving the display quality of the liquid crystal display device. The cross section (ZZ cross section in FIG. 14) of the main part of the connection portion is as shown in FIG. 10, and the liquid crystal display device having a good display quality can be obtained by making the mounting area of the multilayer substrate 14 more compact.

The connection terminal 13 and the panel terminal 18, and the connection terminal 27 and the panel terminal 29 of the multilayer substrate 14 are connected by the connection member 19. Connection member 19
Secures electrical connection and at the same time fixes the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., or a mixture of some of them, alloy, or composite metal particles by plating, etc., N in plastic particles (polystyrene, polycarbonate, acrylic, etc.)
i, Co, Pd, Au, Ag, Cu, Fe, Sn, Pb
And the like, or particles obtained by plating some of them, carbon particles, and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive film is arranged between the panel terminal 18 and the connection terminals 13 and 27 of the multilayer substrate 14, and the anisotropic conductive film is of thermosetting type or blend type of thermoplastic and thermosetting type. In some cases, a heating / pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is irradiated from the panel terminals 18, 29 (glass side) side to cure. Since the connection terminals 13 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Also, 1
The input / output terminals of the multi-layer substrate 14 can be collectively connected to the panel terminals 18 and 29 by a single pressing step.

As another connecting member, there is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb,
Ni, C in Sn, etc. alone or in a mixture of some of them, alloys, composite metal particles by plating, etc., plastic particles (polystyrene, polycarbonate, acrylic, etc.)
These are particles of o, Pd, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound thereof. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 18 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting type or a blend type of thermoplastic and thermosetting type is used for the anisotropic conductive adhesive, the heating and pressing head is pressed against the multi-layer substrate 14 for curing connection. When a UV curable type is used for this anisotropic conductive adhesive, a pressure head is pressed against the multilayer substrate 14 and UV irradiation is performed from the panel terminals 18, 29 (glass side) side to cure. This connection terminal 1
Since 3 and 27 are arranged in a straight line, the pressure head may have a single letter shape and can be connected by a simple crimp connection device. Further, the input / output terminals of the multi-layer substrate 14 can be connected to the panel terminals 18 and 29 collectively by one pressing step.

A mold 21 is provided to protect the exposed portions of the panel terminals 18, 28 and 29 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material is epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound of some of them, and is a solvent type, a thermosetting type, a photocuring type or the like or a combination type thereof.

As shown in FIG. 10, the panel 16 is compactly mounted so that it fits within the outer shape of the panel 16.

As described above, the bus wiring is formed on the panel as a means for establishing electrical continuity between the multi-layered boards, since this bus wiring is formed at the same time as other wiring patterns of the panel, no separate step is required. In addition, a separate component such as a heat seal is not required, and further, since the input / output terminals can be collectively connected, the number of connecting steps can be reduced, so that the liquid crystal display device can be supplied at a lower cost.

Further, by using the multi-layer substrate of this embodiment, it is possible to process the cross wiring in the same multi-layer substrate, which has conventionally been used for cross wiring of the bus wiring by using another bus substrate in the TAB method. ing. Therefore, by densifying the wiring in the board, the size can be made smaller than that of the TAB method, and the cost can be reduced because another bus board is not used.

Further, in the conventional COG method, since the bus wiring is cross-wired on the panel substrate, a large area for the bus wiring is required, and also metal wiring is required to reduce the wiring resistance value, and the cost is reduced. While it becomes high,
By using the multilayer substrate of this embodiment, it is possible to save the bus wiring area and reduce the cost as compared with the COG method.

[Sixth Embodiment] This embodiment will be described with reference to FIGS.
6, FIG. 17 and FIG.

FIG. 15 shows the liquid crystal display device of the present invention.
It is a perspective view which decomposed | disassembled and showed the multilayer substrate of one Example which carried out the face-down bonding of the two liquid crystal drive semiconductor chips on the surface of one multilayer substrate.

Reference numerals 1, 2, and 3 are layers of the multi-layer (three-layer) substrate of this embodiment, 1 is a first layer, 2 is a second layer, and 3 is a third layer. The chips 4 and 4'are known methods (for example, a method of connecting a semiconductor Au bump to a substrate using Ag paste, a method of using an anisotropic conductive film, or a flip chip method of using a solder bump).
Is face-down bonded to the surface of the first layer 1. After bonding, the periphery of the liquid crystal driving semiconductor chips 4, 4'and the liquid crystal driving semiconductor chips 4,
A mold 20 is provided between 4'and the surface of the first layer 1 for corrosion prevention and reinforcement. The molding material may be epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound thereof, and may be a solvent type, a thermosetting type, a photocuring type or a combination type thereof. Input wirings 5 and 5'corresponding to the input pads of the liquid crystal driving semiconductor chips 4 and 4'are patterned on the surface of the first layer 1. The input wirings 5 and 5 ′ are connected to the bus wiring 10 of the second layer 2 through the through holes 6. Further, lands 7 are formed at the tips of the input wirings 5 and 5'for wire bonding with other similar multilayer substrates adjacent to each other.

On the surface of the first layer 1, output wirings 8 and 8'corresponding to the output pads of the liquid crystal driving semiconductor chips 4 and 4'are patterned. Here, since the panel terminal pitch is larger than the output pad pitch of the liquid crystal driving semiconductor chips 4 and 4 ', the pattern is spread on the first layer 1 so that the respective output pads correspond to the panel terminals. Is wired. In addition, output wiring 8, 8 '
A through hole 9 is formed at the tip of the second layer 2, passes through the through hole 11 of the second layer 2, and is connected to the connection terminal 13 with the panel through the through hole 12 of the third layer 3.

The first layer 1, the second layer 2 and the third layer 3 are low temperature co-fired ceramic substrates of alumina base material. The thickness of each was 0.25 mm. Input wiring 5, 5 ', output wiring 8, 8', bus wiring 1
Reference numeral 0 is a fired product of a metal paste of Au, Ag, AgPd, Cu or the like. Similarly, the through holes 6, 9, 11, and 12 are also fired products of metal paste such as Au, Ag, AgPd, and Cu. Similarly, the land 7 and the connection terminal 13 are also fired products of metal paste such as Au, Ag, AgPd, and Cu. Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually about 0.001 mm to 0.05 mm, but in order to reduce the resistance value, it is 0.05 mm to 0.1 mm.
It may be about 2 mm.

However, the input wirings 5 and 5 ', the lands 7, the output wirings 8 and 8'on the front surface of the first layer 1 and the connection terminals 13 on the back surface of the third layer 3 depend on the wiring pitch, dimensional accuracy, and the like. May be patterned by photolithography or the like after the entire surface of a metal paste such as Au, Ag, AgPd or Cu is printed. The pattern thickness at this time is about 0.001 mm to 0.2 mm. Or instead of printing method, Au,
After forming a thin film by vapor deposition of Ag, Cu or the like, or by sputtering, a pattern may be formed by steps such as photolithography and plating. The pattern thickness at this time is 0.0005 mm
To about 0.1 mm.

As described above, bonding two liquid crystal driving semiconductor chips to one multi-layered substrate is as compared with two bonding of one liquid crystal driving semiconductor chip to one multi-layered substrate. Since the input / output wiring can be efficiently arranged and the semiconductor chips can also be arranged efficiently, the required area of the multilayer substrate can be reduced, and the cost of parts can be reduced. Also, separate the multi-layer substrate (dicing,
(Break or the like) and man-hours for setting and resetting a multi-layer substrate for bonding and molding a semiconductor chip can be reduced, and the cost can be reduced.

FIG. 16 shows an embodiment in which the multilayer substrate of the embodiment shown in FIG. 15 is connected to a liquid crystal display panel.

FIG. 17 is an enlarged view of the main part of the connecting portion shown in FIG.

FIG. 18 shows a cross section of the main part of the connection portion shown in FIG.

A liquid crystal display panel (for example, 640 * 480)
The dot display 16 indicates the multi-layer substrate 14 of the embodiment shown in FIG.
It is connected to 8. However, in FIG. 16, four on the X side and Y
The five on the side are not shown. The terminal 13 and the panel terminal 18 of the multilayer substrate 14 are connected by the connecting member 19. The conductive member 19 not only secures electrical connection but also serves to fix the multilayer substrate 14 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., single or plural mixtures, alloys, composite metal particles by alloying or plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.) with Ni, Au,
These are particles of single or multiple plating such as Cu and Fe, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound. This anisotropic conductive film is arranged between the panel terminal 18 and the connection terminal 13 of the multilayer substrate 14,
When a thermosetting or a blend type adhesive of thermoplasticity and thermosetting is used for the anisotropic conductive film, it is cured and connected by pressing a heating and pressing head against the multilayer substrate 14. When a UV curable type adhesive is used for the anisotropic conductive film, a pressure head is pressed against the multilayer substrate 14 and UV is applied from the panel terminal 18 (glass side) side to cure.

Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb,
Ni, Au, C on composite metal particles or plastic particles (polystyrene, polycarbonate, acrylic, etc.) obtained by mixing Sn, etc. singly or in combination, alloys, or plating
These are particles of u, Fe, etc., which are plated alone or in plural, carbon particles and the like. Also, this adhesive is styrene butadiene styrene (SBS) type, epoxy type, acrylic type,
It is a single compound or a mixture or compounds of polyester compounds and urethane compounds. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 16 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting or a blend type adhesive of thermoplasticity and thermosetting is used as the anisotropic conductive adhesive, the heating and pressing head is pressed against the multilayer substrate 14 for curing and connection. When a UV curable adhesive is used as the anisotropic conductive adhesive, the pressure head is pressed against the multilayer substrate 14 to remove the panel terminal 18
UV irradiation is performed from the (glass side) side to cure.

A mold 21 is provided to protect the exposed portion of the panel terminal 18 from corrosion. In addition, the mold 21 also has a role of fixing the multilayer substrate 14 to the panel. The molding material may be epoxy, acrylic, urethane, polyester, etc., or a mixture or compound of some of them, and may be a solvent type, a thermosetting type, a photocuring type or a combination thereof.

The connection of the bus wiring between the adjacent multilayer substrates 14 is wire-bonded by the wire 15 via the land 7. As wire 15, Au, A
l, Cu and other metals or alloys of these metals (Be, S
i, Mg, etc. are also included). The width to be wire-bonded is within the width of the multi-layer substrate, and the panel 16 is compactly mounted within the outer shape of the panel 16 as shown in FIG.

Here, since one liquid crystal driving semiconductor chip bonded to one multi-layer substrate is used, one liquid crystal driving semiconductor chip bonded to one multi-layer substrate is connected. In some cases, the number of connecting points between the multilayer substrates has been reduced to eight (from fourteen to six). Along with this, the number of members of the wire 15 and the number of wire bonding steps can be reduced.

As described above, by using the multi-layer substrate of this embodiment, the cross wiring of the bus wiring is conventionally performed by using another bus substrate in the TAB method, but the cross wiring is performed in the same multi-layer substrate. It has been processed. Therefore,
By making the wiring in the board high density, it is possible to make it more compact than the TAB method, and it is possible to reduce the cost because another bus board is not used.

Further, in the conventional COG method, the bus wiring is cross-wired on the panel substrate, so that a large area for the bus wiring is required, and metal wiring is required to reduce the wiring resistance value, and the cost is reduced. While it becomes high,
By using the multilayer substrate of this embodiment, it is possible to save the bus wiring area and reduce the cost as compared with the COG method.

[Embodiment 7] This embodiment will be described with reference to FIG.

FIG. 19 shows the liquid crystal display device of the present invention.
It is a perspective view which decomposed | disassembled and showed the multilayer substrate of one Example which wire-bonded the two semiconductor chips for liquid crystal drive to the surface of one multilayer substrate.

On the surface of the first layer 1 of the multilayer substrate, wire bonding lands are formed on the input wirings 5 and 5'and the output wirings 8 and 8'corresponding to the input / output pads of the liquid crystal driving semiconductor chips 4 and 4 '. 22 is formed. In addition, the pattern, the through hole, the method of forming the multilayer substrate, the configuration, and the structure are the same as those in the first embodiment.

The back surface of the liquid crystal driving semiconductor chip is fixed to the front surface of the multi-layer substrate, and the land 22 on the front surface of the first layer 1 of the multi-layer substrate corresponding to the input / output pads of the liquid crystal driving semiconductor chips 4 and 4'is provided. Wire bond. As the wire 23, the same wire as that used for the connection between the multilayer substrates of the sixth embodiment can be used. Although not shown, the bonding portion and the wire portion are molded with the same molding material as in the sixth embodiment.

Furthermore, the connection of the bus wiring between the adjacent multilayer substrates is wire-bonded as in the sixth embodiment. Similarly, although not shown, the bonding portion and the wire portion are molded with the same molding material as in the sixth embodiment.

As described above, by using the multilayer substrate of this embodiment, the conventional TAB system and COG system
Similar to the sixth embodiment, it is possible to reduce the size and cost. [Embodiment 8] This embodiment will be described with reference to FIG.

FIG. 20 shows the liquid crystal display device of the present invention.
As in the sixth embodiment, two liquid crystal driving semiconductor chips 4,
The panel terminal 1 of the liquid crystal display panel is a multilayer substrate 14 in which 4'is face-down bonded onto the surface of one multilayer substrate.
8 is connected using a connecting member 19. The main part of the connecting portion is the same as that in FIG. 18 of the sixth embodiment. However, the tip of the input wiring of the first layer 1 of the multilayer substrate is not a land for wire bonding but has a shape suitable for heat sealing or for connecting a flexible substrate.

The connection of the bus wiring between the adjacent multilayer substrates 14 is made by using the connection substrate 24. Connection board 24
A heat seal or a flexible substrate can be used as the material.

The width of connection of the connection board 24 is equal to that of the multilayer board 1.
Within the width of 4, and as shown in FIG.
Similarly, it is compactly mounted so that it fits within the outer shape of the panel 16.

As described above, by using the multilayer substrate of this embodiment, the conventional TAB system and COG system
Similar to the sixth embodiment, it is possible to reduce the size and cost. Further, regarding the connection of the liquid crystal driving semiconductor chip to the surface of the multilayer substrate and the electrical connection between the adjacent multilayer substrates, it is also possible to use the combinations shown in Examples 6, 7 and 8 in combination. In each case, it is possible to make the device compact and reduce the price.

In addition, mounting the semiconductor chip of this embodiment on a multi-layer substrate and mounting the multi-layer substrate on another display device or electronic printing device can be performed by changing the type of the semiconductor chip to a semiconductor chip for driving a plasma display, or E
By changing to the L driving semiconductor chip, it can be similarly applied to a plasma display or an EL display device. Also, a semiconductor chip for driving a thermal head is similarly mounted on a multi-layer substrate, and the multi-layer substrate is similarly connected to the thermal head, so that the electronic printing apparatus can be applied. [Ninth Embodiment] The present embodiment will be specifically described below with reference to FIGS.

FIG. 25 is a sectional view showing an embodiment of a mounting structure in which a semiconductor device mounted on a multilayer substrate is connected to a liquid crystal display device in the liquid crystal display device of the present invention, and FIG. It is a top view. FIG. 27 is a detailed plan view of the terminal connecting portion of the above liquid crystal display element. FIG. 28 is a block diagram of a color liquid crystal display device when configured using the above mounting structure.

In FIG. 25, a liquid crystal display device 110 is a display substrate having a row electrode group, a column electrode group and a color filter formed on the inner surface thereof, and a liquid crystal composition is sealed between them to form an electrode terminal group 113. Has been formed.

The multilayer substrate 1121 shown in FIGS. 25 and 26,
The liquid crystal drive output lines P11 to P3n and the bus line 1122 are patterned and formed on the substrate 1122, and are laminated by vertically connecting the respective substrate layers. Semiconductor device 111
Reference numerals 1, 1112 and 1113 denote liquid crystal driving ICs having bumps formed on their connection terminals.
Are connected to the connection terminals formed on the multilayer substrate 112 by face-down mounting. In this embodiment, three semiconductor elements 1111 and 11 are provided so as to correspond to three color pixels.
Although 12 and 1113 are mounted, the number of elements suitable for increasing or decreasing the number of pixels may be selected.

In the multi-layer substrate 112, the terminals for connecting the respective semiconductor elements are on the surface layer, the input / output line P11 of the semiconductor element 1111 is on the first layer, and the input / output line P21 of the semiconductor element 1112 is on the second layer. Input / output lines P31 of 1113 are formed on the third layer, and bus lines are formed on the surface of the third layer. Although the multilayer substrate 112 of this embodiment has a three-layer structure, it goes without saying that any number of layers may be used as long as an efficient wiring pattern can be formed. Further, as the substrate constituting the multi-layer substrate 112, in this embodiment, ceramic is used in consideration of expansion and contraction due to thermal expansion, but a polyimide film which is a flexible base material may be used.

As is clear from FIG. 25, according to the semiconductor element mounting structure of this embodiment, since the wiring and the bus line for driving the liquid crystal display element 110 are formed in the board, the drive control circuit board is It becomes unnecessary and the number of constituent parts is extremely small, and the parts cost can be greatly reduced.

As shown in FIG. 27, the connection between the multi-layer substrate 1121 and the liquid crystal display element 110 is performed by each color pixel R (red) 1
311, G (green) 1312, B (blue) 1313 drawn out for each liquid crystal display element electrode terminal group 113, and semiconductor elements 1111 (for R), 1112 (G) corresponding to each pixel.
Liquid crystal drive output line P11
(Output of semiconductor element 1111) P21 (semiconductor element 111
2 output), P31 (output of the semiconductor element 1113), and the multi-layered substrate terminal group 114 formed on the extension thereof are aligned and 180 ° C. is applied by the crimping machine through the anisotropic conductive adhesive 115.
It is connected under a pressure bonding condition of 0 Kg / Cm ² and 20 seconds.

Since the color display has a drawback that the driving method is high duty and there is more crosstalk than the black and white display and the contrast is lowered, the output of independent semiconductor elements for each color electrode is provided by the connection method of this embodiment. Since wiring can be connected and an appropriate drive waveform can be supplied, crosstalk is reduced and high-contrast display can be obtained.

FIG. 28 is a block diagram showing an embodiment of a color liquid crystal display device using the above-described mounting structure according to this embodiment. The display element 110 is, for example, an STN type color liquid crystal display of 640.times.480 dots display. , Semiconductor element 11
Reference numerals 11 to 11112 denote liquid crystal driving segment drivers having 160 outputs.

The multi-layer substrates 1121 to 1124 have the semiconductor elements 1111 to 11112 as R (red), G (green) and B (blue).
The liquid crystal display element 1 has three elements mounted for each color.
Four electrodes are mounted in parallel on the electrode terminals formed on the outer periphery of 10. Further, the multi-layer substrates 1121 to 1124 on which the semiconductor elements 1111 to 11112 are mounted are connected to each other at four points in order to supply power and control signals.

When a color liquid crystal display device is constructed by the above-mentioned mounting structure, the mounting structure of semiconductor elements has a high density and a compact liquid crystal display device can be realized. In addition, the connection location between the liquid crystal display elements is reduced to 1/3 as compared with the conventional case, and the connection reliability is improved.

A liquid crystal display device was constructed by the mounting structure of the semiconductor element according to the present example, and a reliability test was conducted. TS test (-30 ° C., 80 ° C.) 1000 cycles, TH
No problem occurred even after 1000 hours of testing (60 ° C., 90% RH), and very good connection reliability could be realized.

[Embodiment 10] FIG. 29 is a main sectional view showing a mounting structure of a semiconductor device of this embodiment, and shows an embodiment using a liquid crystal display device 203 (hereinafter referred to as LCD) as an electronic device. .

In FIG. 29, an LSI 201 is mounted in a predetermined position on a multilayer substrate 202 equipped with an internal conductive layer 221, an input wiring 204, an output wiring 205, a via hole 261, a bump 206, etc. in a face-down manner. Input / output terminals of the LSI 201 are connected to the input wiring 204 and the output wiring 205. The mounted LSI 201 is fixed with an adhesive 208 as necessary,
Further, reliability such as moisture resistance can be improved. An internal conductive layer 221 is provided inside the multi-layer substrate 202, and each board is electrically connected to the front and back sides through through holes or the like to input each signal.
The function of transmitting noise to the circuit 04 and the internal conducting portion 221 are set to the ground level to play a role of preventing noise. The bump 206 portion of the multilayer substrate 202 and the terminal 231 of the LCD 203 are electrically connected using the ACF 209. In the figure, the ACF 209 is used in a limited space near the bump 206, but it may be used over the entire surface of the multilayer substrate 202. FIG. 30 shows one of the multilayer substrates 202 of the mounting structure of this embodiment.
FIG. In the figure, the output wiring 205 connected to the output terminal of the LSI 201 is the via hole 2
Conduction is made from the front surface to the back surface of the multilayer substrate through 61 and is connected to the bump 206. 31 shows the multilayer substrate 20.
FIG. 2 is a plan view of one of No. 2 and shows the back surface. In the figure, bumps 206 which receive signals from the LSI output terminals are formed in a line in a necessary number of thousands. To reduce the output terminal pitch to accommodate the fine pitch, the
This can be realized by increasing the staggered arrangement of rows to 3 rows and 4 rows. The features of each component / member in this embodiment are as follows. LSI 201 ... Uses a structure in which the external size is close to a square, and the external shape is long and slender with the ratio of the short side to the long side of 1: 5 or more, and the latter has the input terminals and the output terminals concentrated on one side as much as possible. Use bumps for each terminal. Multilayer substrate 202 ... Ceramics, glass epoxy resin, etc. are used as the material. The number of layers is 3. Electronic element 203 ... An electronic element such as a liquid crystal display element. Input wiring 204 ... Au only, AgPd, Cu base N
i / Au plated output wiring 205 ... Same as the input wiring 204. Two forming methods were used: a method of filling the inside of the through hole with a conductive material, followed by half-cutting, and a method of forming on the side surface of the multilayer substrate by printing. Output terminal 205a ... Same as above Bump 206 ... Same as input wiring 204. It is desirable that the bump shape is a circle, a quadrangle, etc. and that the climbing portion has a flat surface. The size of the bump naturally changes depending on the wiring pattern pitch, but it is desirable to maximize the size while maintaining the insulating property. Mold 208 ... Epoxy adhesive ACF 209 ... Thermosetting ACF: Hitachi Chemical Co., Ltd. product number AC6000 series, 7000 series adhesive 211 ... UV curing adhesive, thermosetting epoxy adhesive FIG. It is a top view which shows one Example of the LCD module using the mounting structure and mounting method of the semiconductor element of invention. In the figure, a plurality of multilayer substrates 202 are mounted on the terminals of the LCD 203. In this embodiment, each multilayer substrate 20
The two are connected by wire bonding using a conductive wire of Au, Cu, Al or the like, but a method using heat sealing or FPC may be used. Large LC as shown in the figure
Even in D, a very compact mounting area is realized by using this mounting structure.

[Embodiment 11] FIG. 33 is a main cross-sectional view showing a mounting structure of a semiconductor device of this embodiment, and shows an embodiment using an LCD 203 as an electronic device. As compared with the tenth embodiment, the bump 206 on the multilayer substrate 202 is LCD2.
The feature is that it is mounted so as to come to the 03 side.

[Embodiment 12] FIG. 34 is a main sectional view showing a mounting structure of a semiconductor element of the present embodiment, and shows an embodiment using an LCD 203 as an electronic element. The feature of the tenth embodiment is that the output wiring 205 of the multilayer substrate 202 is electrically connected not by the via hole but by the side wiring 251 and is connected to the bump 206 on the back surface.

[Embodiment 13] FIG. 35 is a plan view showing an embodiment of a thermosensitive electronic printing device (hereinafter referred to as an electronic printing device) using the mounting structure of a semiconductor element of the present invention. In the figure, a thermal printer head 2 which is an electronic printing element
A plurality of multilayer substrates 202 are mounted on the terminals of 13.
FIG. 36 is a plan view showing the electronic printing apparatus of this embodiment, which realizes a very compact mounting area as in the case of the LCD.

[Embodiment 14] FIG. 37 is a plan view showing an embodiment of an electronic printing apparatus using the semiconductor element mounting structure of the present invention. One multilayer substrate 202 as compared with the thirteenth embodiment
The feature is that it is a single integrated substrate.

[Embodiment 15] FIG. 38 is a sectional view showing an embodiment of an electronic printing apparatus using a semiconductor element mounting structure of the present invention. A feature is that a multilayer substrate 202 similar to that of the twelfth embodiment is used for the thirteenth embodiment.

[Embodiment 16] FIG. 39 is a main sectional view showing an embodiment of the mounting structure of the semiconductor element of the present invention. It is an example using a liquid crystal display element as an electronic element. Figure 3
9, the LSI 201 is mounted in a predetermined position on the multilayer substrate 202 equipped with the internal conductive layer 221, the input wiring 204, and the output wiring 205 by a face-down method.
Each input / output terminal of 201 is connected to the input wiring 204 and the output wiring 205. LSI2 mounted
If desired, 02 may be further fixed with an adhesive 208 to improve reliability such as moisture resistance. An internal conductive layer 221 is provided inside the multi-layer substrate 202, and has a role of transmitting front and back of each substrate through a through hole or the like to the input wiring 204 and transmitting each signal, and a role of the internal conductive portion 221 becoming a ground level to prevent noise. Is playing.

The output wiring 205 of the multi-layer substrate 202 is extended and formed so as to wrap around to the side surface of the multi-layer substrate 202, and the side surface portion of the output terminal 204a is connectable to another electronic element.
Is formed as. The output terminal 205a and the electronic element 203 (liquid crystal display element in the present embodiment, hereinafter referred to as LCD) are mounted using an ACF 209 so that the planes of the multilayer substrate 202 and the electronic element (LCD) 203 are substantially vertical and electrically. It is connected to the. After the multi-layer substrate 202 is mounted, the multi-layer substrate 202 and the electronic device (LCD) 203 may be adhesively fixed to each other with an adhesive agent 211 in order to improve strength. With this mounting method, the mounting area dimension A at the end of the electronic element 203 can be kept within 2 mm. Figure 4
0 is a plan view of the liquid crystal display device.
It is desirable that the size of the portion A in FIG.
When the back surface is equipped with a backlight, the mounting structure of this embodiment can be used to greatly reduce the size of the portion A, so that the commerciality of the LCD module can be greatly improved.

The features of each component / member in this embodiment are as follows. LSI 201 ... Uses a structure in which the external size is close to a square, and the external shape is long and slender with the ratio of the short side to the long side of 1: 5 or more, and the latter has the input terminals and the output terminals concentrated on one side as much as possible. Use bumps for each terminal. Multilayer substrate 202 ... Ceramics, glass epoxy resin, etc. are used as the material. The number of layers is 3. Electronic element 203 ... An electronic element such as a liquid crystal display element. Input wiring 204 ... Au only, AgPd, Cu base N
Those with i / Au plating, etc. Output wiring 205 ... Same as the input wiring 204. Output terminal 205a ... Same as above. As a forming method, there were used a method of forming a through hole (via hole) and then cutting at a central portion thereof to form a terminal, and a method of forming a conductor pattern by printing on a side surface of the substrate. Mold 208 ... Epoxy adhesive. ACF 209 ... Thermosetting ACF: Use a product number AC6000 series, 7000 series manufactured by Hitachi Chemical Co., Ltd., having a conductive particle density of 1000 particles / mm ² or more before pressure bonding. Adhesive 211 ... UV curable adhesive, thermosetting epoxy adhesive.

[Embodiment 17] FIG. 41 shows an embodiment of a liquid crystal display device using the semiconductor element mounting structure of the present invention. In the figure, a plurality of multilayer substrates 202 are mounted on the terminals of the LCD 203 by using the semiconductor element mounting structure of the present invention. The connection between the substrates was performed by wire bonding using a metal wire of Au, Cu, Al or the like, but the connection may be performed by a method of using ACF in heat sealing or FPC. Even in a large LCD as shown in the figure, by using this mounting structure, a very compact mounting area is realized.

[Embodiment 18] FIG. 42 shows an embodiment of a thermal electronic printing apparatus (hereinafter referred to as an electronic printing apparatus) using the semiconductor element mounting structure of the present invention. The multilayer substrate 20 is provided on the terminal of the head 213.
2 is implemented. As with the LCD, it has a very compact mounting area.

[Embodiment 19] This embodiment will be described below with reference to FIG.

FIG. 43 shows a semiconductor element mounting method according to the present invention. In the arrangement of input terminals and output terminals, only the output terminal group is arranged on one side around the semiconductor element, and only the output terminal group is arranged. The semiconductor element 3 in which the input terminal groups are arranged on one side or two sides orthogonal to the side where
04, 301, 302, and 3 are exploded perspective views of the multilayer substrate 311 of the embodiment in which 04 is face-down bonded to the multilayer substrate 311 in which the opening 320 is provided in the first layer 301.
Reference numeral 03 denotes each layer of the multilayer (three-layer) wiring board of the present embodiment.
1 is a first layer, 2 is a second layer, 3 is a third layer, an opening 320 is provided in the first layer 301, and the second layer 3
On the surface of 02, the input wiring 305 corresponding to the input electrode of the semiconductor element 304 is patterned. In addition, the input wiring 305 is connected to the third layer 3 through the through hole 306.
No. 03 bus line 309. Furthermore, another similar multilayer substrate 311 adjacent to the tip of the input wiring 305 is provided.
And a land 307 for connecting the bus wire to the bus wire are formed.

Furthermore, the output wiring 308 of the second layer 302.
An output terminal through hole 324 is formed at the tip of the, and is connected to the external connection terminal 310 through the through hole of the third layer 303.

Each of the layers 301, 302 and 303 is exemplified by a low temperature co-fired ceramic substrate of alumina base material. The thickness of each is as thin as 0.25 mm, and the input wiring 305, the output wiring 308, and the bus wiring 3 are used.
Reference numeral 09 is a fired product of a metal paste of Au, Ag, AgPd, Cu or the like. Similarly, the through holes 306 and 324 are similarly fired products of a metal paste such as Au, Ag, AgPd, and Cu. In addition, the land 307 and the external connection terminal 310
Is also a fired product of a metal paste of Au, Ag, AgPd, Cu or the like. Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually 0.001 mm to 0.05.
mm, but 0.05 mm to reduce the resistance
To about 0.2 mm.

However, the surface input wiring 3 of the first layer 301
05, the land 307, the output wiring 30 of the second layer 302
8 and the external connection terminals 310 on the back surface of the third layer 303 are Au, Ag, Ag depending on the wiring pitch, dimensional accuracy, etc.
A pattern may be formed by photolithography or the like after the entire surface of a metal paste such as Pd or Cu is printed. At this time, the pattern thickness is preferably about 0.001 mm to 0.2 mm. Alternatively, instead of the printing method, after vapor deposition of Au, Ag, Cu, etc., or thin film formation by sputtering etc., photolithography,
You may form a pattern by processes, such as plating. At this time, the pattern thickness is preferably about 0.0005 mm to 0.1 mm.

The material of the multi-layer substrate has been described by taking a ceramic substrate as an example this time, but other materials such as color epoxy, paper phenol, and polyimide may be used.

[Embodiment 20] Hereinafter, this embodiment will be described with reference to FIGS.
This will be described using 5.

FIG. 44 is a perspective view showing an embodiment of the mounting structure of the semiconductor device of this embodiment. The semiconductor device 304 is mounted on the multilayer substrate 311 shown in Embodiment 19 by a known method (for example, semiconductor Au bumps). Is connected to the substrate using Ag paste, or a method using an anisotropic conductive film), and the semiconductor element 304 forms the opening 32 of the first layer 301.
It passes through 0 and is face-down bonded to the surface of the second layer 302.

After the face down, a molding agent is filled around the semiconductor element 304 and between the semiconductor element 304 and the surface of the second layer 302 for corrosion prevention and reinforcement. The semiconductor element 304 is formed on the surface of the second layer 302.
The feature is that the input wiring 305 corresponding to the input electrode of is patterned.

[Embodiment 21] Hereinafter, this embodiment will be described with reference to FIGS.
This will be described using 7.

FIG. 46 is a perspective view showing an example of the mounting structure of the semiconductor device of this example, and the opening 32 provided in the first layer 301 of the multilayer substrate 311 shown in Example 19.
After passing through 0, the semiconductor element 304 is fixed with an adhesive or the like so that the active surface is located on the upper surface, and the electrode 325 of the semiconductor element 304 and the wire bonding land 318 of the first layer 301 of the multilayer substrate 311 are connected. It is one example implemented by a wire bonding mounting method. The pitch of the wire bonding land 318 is from 60 μm to 300
The electrodes 32 are arranged with Au wires 312.
5 and the wire bonding land 318 are connected.

FIG. 47 is a sectional view of an example of a semiconductor element mounting method according to the twentieth embodiment.

[Embodiment 22] Hereinafter, this embodiment will be described with reference to FIGS.
This will be described using 9.

FIG. 48 is a perspective view showing an embodiment of the mounting structure of the semiconductor element of the present embodiment, disassembled for each component. The semiconductor element 304 shown in the twentieth embodiment is the first layer of the multilayer substrate 311. The second layer 30 is passed through the opening 320 of 301.
In the embodiment showing the mounting method of the bus wiring of the semiconductor element mounted face down on the second semiconductor element 3,
04, the bus wiring 309 of the mounted multilayer substrate 311
It is performed by the FPC 326 for bus wiring, and it is an FP for bus wiring.
A bus wiring connection land 328 corresponding to the land 307 of the multilayer substrate 311 is formed in C.
And the bus wiring connection land 328 are connected by solder, an anisotropic conductive film, or the like.

FIG. 49 is a front view after the mounting of FIG.

[Embodiment 23] Hereinafter, this embodiment will be described with reference to FIGS.
This will be described using 1.

FIG. 50 is a perspective view showing an embodiment of the mounting structure of the semiconductor device of the present invention by disassembling each component. The semiconductor device 304 shown in the embodiment 20 is the first part of the multilayer substrate 311.
Through the opening 320 in the layer 301 of the second layer 302
In the embodiment showing the mounting method of the bus wiring of the semiconductor device mounted face down in FIG.
The bus wiring 309 of the mounted multilayer substrate 311 of FIG. 4 is performed by a bus wiring PCB substrate having a plurality of openings 329. The bus wiring PCB substrate corresponds to the land 307 of the multilayer substrate 311. The wiring connection land 328 is configured, and the land 307 and the bus wiring connection land 3 are formed.
28 is connected with solder or an anisotropic conductive film or the like.

FIG. 51 is a front view after the mounting of FIG.

[Embodiment 24] This embodiment will be described below with reference to FIG.

FIG. 52 is a perspective view showing an example of the mounting structure of the semiconductor element of the present example. The semiconductor element 304 shown in Example 20 has the opening 320 of the first layer 301 of the multilayer substrate 311. In the embodiment showing the mounting method of the bus wiring of the semiconductor element mounted on the second layer 302 face down, the bus wiring of the multilayer substrate 311 on which the plurality of semiconductor elements 304 are mounted is Using the land 307 provided on the surface of the first layer 301 of the multilayer substrate 311,
It is characterized in that they are connected by Au wires 312 by a wire bonding mounting method.

[Embodiment 25] Hereinafter, this embodiment will be described with reference to FIGS.
4 will be described.

FIG. 53 is a perspective view showing one embodiment of the mounting structure of the semiconductor device of this embodiment, disassembled into parts. The semiconductor device 304 shown in Embodiment 20 is the first layer of the multilayer substrate 311. The semiconductor element 3 is passed through the opening 320 of the semiconductor element 301.
04 is fixed to the second layer 302 of the multilayer substrate 311 with an adhesive or the like such that the active surface of the semiconductor element 30 is positioned on the upper surface.
No. 4 electrode 325 and the wire bonding land 318 of the first layer 301 of the multi-layer substrate 311 are mounted by the wire bonding mounting method. Bus wiring 309 of the multilayer substrate 311 on which the semiconductor element 304 of FIG.
Is performed by the bus wiring FPC 326, and the bus wiring FPC is provided with the bus wiring connection land 328 corresponding to the land 307 of the multilayer substrate 311.
07 and the bus wiring connection land 328 are connected by solder, an anisotropic conductive film, or the like.

FIG. 54 is a front view after the mounting of FIG. 53.

[Twenty-sixth Embodiment] This embodiment will now be described with reference to FIGS.
This will be described using 6.

FIG. 55 is a perspective view showing an embodiment of the mounting structure of the semiconductor element of the present embodiment, disassembled for each component. The semiconductor element 304 shown in the twentieth embodiment is the first layer of the multilayer substrate 311. The semiconductor element 3 is passed through the opening 320 of the semiconductor element 301.
04 is fixed to the second layer 302 of the multilayer substrate 311 with an adhesive or the like such that the active surface of the semiconductor element 30 is positioned on the upper surface.
No. 4 electrode 325 and the wire bonding land 318 of the first layer 301 of the multi-layer substrate 311 are mounted by the wire bonding mounting method. Bus wiring 309 of the multilayer substrate 311 on which the semiconductor element 304 of FIG.
Is performed on a PCB board for bus wiring provided with a plurality of openings 329.
Connection land 3 for bus wiring corresponding to the land 307 of 11
28, and the land 307 and the bus wiring connection land 328 are connected to each other by solder, an anisotropic conductive film, or the like.

FIG. 56 is a front view after the mounting of FIG. 55.

[Embodiment 27] This embodiment will be described below with reference to FIG.

FIG. 57 is a perspective view showing an embodiment of the mounting structure of the semiconductor device of the present embodiment. The semiconductor device 304 shown in the embodiment 20 has the opening 320 of the first layer 301 of the multilayer substrate 311. After passing through, the semiconductor element 304 is fixed to the second layer 302 of the multilayer substrate 311 with an adhesive or the like so that the active surface of the semiconductor element 304 is located on the upper surface, and the electrode 325 of the semiconductor element 304 and the first layer 301 of the multilayer substrate 311. In the embodiment showing the method of mounting the bus wiring of the plurality of multi-layer boards 311 in which the wire bonding lands 318 of FIG. 3 are mounted by the wire bonding mounting method, the bus of the multi-layer board 311 on which the plurality of semiconductor elements 304 are mounted. Using the land 307 provided with the wiring on the surface of the first layer 301 of the multilayer substrate 311, the Au wire 3 is formed by the wire bonding mounting method.
It is characterized by connecting with 12.

[Embodiment 28] This embodiment will be described below with reference to FIG.

FIG. 58 is a sectional view showing an embodiment in which the semiconductor element mounting structure of this embodiment is mounted on a liquid crystal display device which is an electro-optical device, and the semiconductor element 3 shown in the embodiment 22 is shown.
Reference numeral 04 denotes an opening 320 of the first layer 301 of the multilayer substrate 311.
After passing through, the bus wiring 309 of the multilayer substrate 311 on which a plurality of face-down mounted semiconductor elements are mounted on the second layer 302 is mounted on the liquid crystal display device by the FPC 326 for bus wiring. Therefore, the external connection terminal 310 and the panel terminal 315 of the multilayer substrate 311 are connected by the anisotropic conductive film 316. The anisotropic conductive film 316 not only secures electrical connection, but also serves to fix the multilayer substrate 311 to the liquid crystal panel 313 to some extent. When the anisotropic conductive film 316 is a thermosetting type or a blend type of thermoplastic and thermosetting type, a heating / pressing head is pressed against the multilayer substrate 311 for curing connection. When a UV curable type is used for the anisotropic conductive film 316, a pressure head is used as the multilayer substrate 3.
It is pressed against 11, and is irradiated with UV from the panel terminal 315 (glass side) side to be cured.

A mold 330 is filled to protect the exposed portion of the panel terminal 315 from corrosion. In addition, the mold 330 forms the multi-layer substrate 311 on the liquid crystal panel 3.
It also has the role of fixing at 13.

As described above, by using the multilayer substrate 311 of this embodiment, it is possible to cope with a fine pitch of 80 μm or less, which has been difficult in the conventional TCP method.

Further, in the conventional COG method, since the bus wiring is cross-wired on the liquid crystal panel substrate, a large area for the bus wiring of the liquid crystal panel is required, and the metal wiring is used to reduce the wiring resistance value. However, by using the multi-layer substrate 311 of this embodiment, it is possible to save the bus wiring area and reduce the cost as compared with the COG method.

[Embodiment 29] This embodiment will be described below with reference to FIG.

FIG. 59 is a sectional view showing an embodiment in which the semiconductor element mounting structure of the present invention is mounted on the head portion of a thermal printer which is an electronic printing apparatus. The semiconductor element 304 shown in the embodiment 22 is a multilayer substrate. 311 first layer 301
The bus wiring 309 of the multilayer substrate 311 on which a plurality of semiconductor elements face-down mounted on the second layer 302 are mounted through the opening 320 of the FPC 326 for bus wiring.
The multi-layer substrate 311 mounted on the multi-layer substrate 311 is mounted on a thermal printer head of an electronic printing apparatus, and the external connection terminal 310 and the panel terminal 315 of the multi-layer substrate 311 are the anisotropic conductive film 3
The connection is made by 16.

[Embodiment 30] This embodiment will be described below with reference to FIG.

FIG. 60 is a sectional view showing an embodiment in which the mounting structure of the multilayer substrate of the embodiment 23 is mounted on a liquid crystal display device which is an electro-optical device. The feature of the twenty-eighth embodiment is that the bus wirings of the plurality of multilayer substrates 311 are mounted using the bus wiring PCB substrate 327 having the plurality of openings 321.

[Embodiment 31] This embodiment will be described below with reference to FIG.

FIG. 61 is a sectional view showing an embodiment in which the mounting structure of the multilayer substrate of the embodiment 23 is mounted on the head portion of a thermal printer which is an electronic printing device. A feature of the twenty-ninth embodiment is that the bus wirings of the plurality of multilayer boards 311 are mounted by using the bus wiring PCB board 327 having a plurality of openings 321.

[Embodiment 32] This embodiment will be described below with reference to FIG.

FIG. 62 is a perspective view showing an embodiment in which the mounting structure of the multilayer substrate of Embodiment 20 is mounted on a liquid crystal display device which is an electro-optical device. As compared with the twenty-eighth embodiment, the bus wirings of the plurality of multilayer substrates 311 are A by wire bonding.
It is characterized in that they are connected by a u wire 312.

[Embodiment 33] This embodiment will be described below with reference to FIG. 63.

FIG. 63 is a perspective view showing an embodiment in which the mounting structure of the multilayer substrate of the embodiment 20 is mounted on the head portion of a thermal printer which is an electronic printing device. A feature of the twenty-ninth embodiment is that the bus wirings of the plurality of multilayer substrates 311 are connected by Au wires 312 by wire bonding.

[Embodiment 34] This embodiment will be described below with reference to FIG.

FIG. 64 is a sectional view showing an embodiment in which the mounting structure of the multilayer substrate of Embodiment 21 is mounted on a liquid crystal display device which is an electro-optical device. A feature of the twenty-eighth embodiment is that the input / output terminals of the semiconductor element 304 are mounted by wire bonding.

[Embodiment 35] This embodiment will be described below with reference to FIG.

FIG. 65 is a sectional view showing an embodiment in which the mounting structure of the multilayer substrate of Embodiment 21 is mounted on the head portion of a thermal printer which is an electronic printing apparatus. A feature of the twenty-ninth embodiment is that the input / output terminals of the semiconductor element 304 are mounted by wire bonding.

[Embodiment 36] This embodiment will be described below with reference to FIG. 66.

FIG. 66 is a sectional view showing an example in which the mounting structure of the multilayer substrate of Example 21 is mounted on a liquid crystal display device which is an electro-optical device. The embodiment 34 is characterized in that the bus wirings of the plurality of multilayer boards 311 are mounted using the bus wiring PCB board 327 having a plurality of openings 321.

[Embodiment 37] This embodiment will be described below with reference to FIG.

FIG. 67 is a sectional view showing an embodiment in which the mounting structure of the multilayer substrate of the embodiment 21 is mounted on the head portion of a thermal printer which is an electronic printing device. The embodiment 35 is characterized in that the bus wirings of the plurality of multilayer boards 311 are mounted using the bus wiring PCB board 327 having a plurality of openings 321.

[Embodiment 38] This embodiment will be described below with reference to FIG.

FIG. 68 is a perspective view showing an embodiment in which the mounting structure of the multilayer substrate of Embodiment 21 is mounted on a liquid crystal display device which is an electro-optical device. As compared with the twenty-eighth embodiment, the bus wirings of the plurality of multilayer substrates 311 are A by wire bonding.
It is characterized in that they are connected by a u wire 312.

[Embodiment 39] This embodiment will be described below with reference to FIG. 69.

FIG. 69 is a perspective view showing an embodiment in which the mounting structure of the multilayer substrate of Embodiment 21 is mounted on the head portion of a thermal printer which is an electronic printing device. A feature of the twenty-ninth embodiment is that the bus wirings of the plurality of multilayer substrates 311 are connected by Au wires 312 by wire bonding.

[Embodiment 40] This embodiment will be described with reference to FIG.

FIG. 70 shows a liquid crystal display device of the present invention.
Similar to the first embodiment, the multilayer substrate 14 in which the liquid crystal driving semiconductor chip 4 is face-down bonded on the surface of the multilayer substrate
Is connected to the terminal 18 of the liquid crystal display panel using a connecting member 19. The main part of the connecting portion is the same as that in FIG. 4 of the first embodiment. However, in the multi-layer substrate, in order to reduce the connection length between the multi-layer substrates, only the portion necessary for wire bonding is projected.

As described above, by using the multilayer substrate of this embodiment, the distance between the multilayer substrates can be shortened with the minimum required shape without having an unnecessary portion in the multilayer substrate, thereby shortening the wire length of wire bonding. Therefore, the occurrence of connection failure due to wire breakage is reduced, and a low-cost and highly reliable liquid crystal display device is possible.

[Embodiment 41] This embodiment will be described with reference to FIG.

FIG. 71 shows a liquid crystal display device of the present invention.
Similar to the first embodiment, the multilayer substrate 14 in which the liquid crystal driving semiconductor chip 4 is face-down bonded on the surface of the multilayer substrate
Is connected to the terminal 18 of the liquid crystal display panel using a connecting member 19, and the multilayer substrates are connected by wire bonding. The main part of the connecting portion is the same as that in FIG. 4 of the first embodiment. However, the upper layer of the multi-layer substrate is smaller than the other layers, a step is formed at the end of the multi-layer substrate, and the connection between adjacent multi-layer substrates is performed by wire bonding in two stages.

As described above, by using the multilayer substrate of the present embodiment, the wire bonding can be divided into a plurality of stages so that the lands for wire bonding can be gathered and, as a result, the outer shape of the multilayer substrate can be reduced, It is possible to make it compact and low-priced.

[Embodiment 42] This embodiment will be described with reference to FIG.

FIG. 72 shows a liquid crystal display device of the present invention.
Similar to the first embodiment, the multilayer substrate 14 in which the liquid crystal driving semiconductor chip 4 is face-down bonded on the surface of the multilayer substrate
Is connected to the terminal 18 of the liquid crystal display panel using a connecting member 19. The main part of the connecting portion is the same as that in FIG. 4 of the first embodiment. However, in the portion M of FIG. 72, the multilayer substrate is provided with at least one intermediate layer between the upper layer and the lower layer, and the intermediate layer or the lower layer or the intermediate layer and the lower layer has a smaller area than the upper layer. Has become.

As described above, by using the multilayer substrate of this embodiment, the intermediate layer or the lower layer other than the upper layer of the multilayer substrate or both the intermediate layer and the lower layer has a smaller area than the upper layer, and the portion to which the jig and tool is attached is The provision makes it easier to handle during rework work.

[Embodiment 43] This embodiment is shown in FIGS.
4 and FIG. 75.

FIG. 73 shows a liquid crystal display device of the present invention.
It is a perspective view which decomposed | disassembled and showed the multilayer substrate of one Example which carried out the face-down bonding of the semiconductor chip for liquid crystal drive on the surface of a multilayer substrate.

Reference numerals 1, 2, and 3 are layers of the multilayer (three-layer) substrate of this embodiment, 1 is a first layer, 2 is a second layer, and 3 is a third layer. Similarly, the liquid crystal driving semiconductor chip 4
Is face-down bonded to the surface of the multilayer substrate. After the bonding, the periphery of the liquid crystal driving semiconductor chip 4 and the space between the liquid crystal driving semiconductor chip 4 and the surface of the first layer 1 are molded for corrosion prevention and reinforcement. A liquid crystal driving semiconductor chip 4 is formed on the surface of the first layer 1.
The input wiring 5 corresponding to the input pad is patterned. Further, the input wiring 5 is connected to the bus wiring 10 of the second layer 2 through the through hole 6. Further, a land 7 is formed at the tip of the input wiring 5 for wire bonding with another adjacent similar multilayer substrate.

On the surface of the first layer 1, the output wiring 8 corresponding to the output pad of the liquid crystal driving semiconductor chip 4 is patterned. Here, since the panel terminal pitch is larger than the output pad pitch of the liquid crystal driving semiconductor chip 4, the pattern is widened and wired on the first layer 1 so that the respective output pads correspond to the panel terminals. ing. Further, a through hole 9 is formed at the tip of the output wiring 8 and is connected to a connection terminal 13 with the panel on the back surface of the first layer.

The layers 1, 2, and 3 are low-temperature co-fired ceramic substrates made of alumina as in Example 1.

FIG. 74 shows a cross section of a main part of an embodiment in which the multilayer substrate of the embodiment shown in FIG. 73 is connected to a liquid crystal display panel.

FIG. 75 shows a main part of an embodiment in which the multilayer substrate of the embodiment shown in FIG. 73 is connected to a liquid crystal display panel.

As described above, by using the multilayer substrate of this embodiment, it is possible to reduce the thickness of the liquid crystal display device by removing a part of the multilayer substrate from the liquid crystal display panel terminals from the liquid crystal display panel terminals. It is possible.

In addition, mounting the semiconductor chip of this embodiment on a multi-layer substrate and mounting the multi-layer substrate on another display device or electronic printing device can be performed by changing the type of the semiconductor chip to a semiconductor chip for driving a plasma display, or E
By changing to the L driving semiconductor chip, it can be similarly applied to a plasma display or an EL display device. Also, a semiconductor chip for driving a thermal head is similarly mounted on a multi-layer substrate, and the multi-layer substrate is similarly connected to the thermal head, so that the electronic printing apparatus can be applied. [Embodiment 44] Another embodiment of the present invention is shown in FIGS.
7 and FIG. 78. 76 and 77 are perspective views showing a multi-layer substrate of one embodiment in which a liquid crystal driving semiconductor chip is face-down bonded to the surface of the multi-layer substrate in the liquid crystal display device of the present invention. The material and structure of this multi-layer substrate are the same as those of the multi-layer substrate of the first embodiment, but mounting holes 432 are provided. Although the mounting hole 432 has a circular shape in the drawing, it may have a rectangular shape, an elliptical shape, a square shape, an elongated hole shape, or the like.

FIG. 77 shows a liquid crystal display device of the present invention using the multilayer substrates 431a to 431a shown in FIGS. The multi-layer substrates 14.431a to 1431d having the liquid crystal driving semiconductor chip 4 mounted on the surface of the multi-layer substrate are connected to the panel 16.
The panel 16, the back light unit 435 and the exterior decorative case 436, and the exterior decorative case upper part 433 are fixed to the multilayer substrates 431a to 431d through mounting holes 432 by fixing screws 434. As a result, in the liquid crystal display device of the present invention, the exterior decorative case can be used also as the exterior case of a PC (personal computer) or the like, and a frame which is required as a separate part in the conventional liquid crystal display device.
Parts such as a metal frame can be reduced, and parts cost can be reduced. Also,
Assembly man-hours can be simplified and processing man-hours can be reduced.

Here, the multilayer boards 14, 431a to 431a-d and the panel terminal 18 are connected by the adhesive member 19 and are adhesively reinforced by the mold 21 as in the first embodiment, but the strength after being assembled in the housing is high. In order to improve (vibration resistance), the panel terminals 18 and the side surfaces of the multilayer substrates 14, 431 a to d,
Alternatively, the mold 21 may be provided on the back surface. The molding material is epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound of some of them, and is a solvent type, a photo-curing type or a combination type thereof.

Since the positional accuracy between the pattern and the mounting hole of the multi-layered substrate can be set to ± 0.1 mm or less, the positional accuracy between the position of the panel pattern and the mounting hole is ± 0. 2mm or less can be secured. Since this mounting hole is used to assemble to the exterior decorative case 436 which is the housing, position reproducibility with respect to the backlight unit 435 and position reproducibility with the panel display area on the exterior decorative case 433 are ensured. Can be improved. When the mounting screws 434 are used for assembly, rework reassembly is easy. In addition, if a tack-shaped component made of plastic with a hook is used, it can be assembled and fixed simply by pushing it in during assembly, and simple assembly is possible. The backlight unit 435 and the exterior makeup case 436 are double-sided.
A method of fixing with a hook or the like or a method of fixing with a mounting claw or the like may be used.

[Embodiment 45] Another embodiment of the present invention will be described with reference to FIGS. 79, 80 and 81. 79 and 8
As shown by 1, the size of the multilayer substrates 437a to 437a is designed to be larger than the end face of the glass terminal 18, and the mounting notch shape is fixed outside the glass end face. The material and structure of this multi-layered substrate are the same as those of the multi-layered substrate of the first embodiment, but the attachment notch 438 is provided. The shape of the attachment notch 438 is semicircular in the figure. The shape may be all or part of a rectangle, a square, a diamond, an ellipse, an elongated hole, or the like. Here, the position of the mounting notch is arranged at the center of the multilayer boards 437a to 437d, and if the shape is symmetrical with respect to the center line in the long side direction of the multilayer board, four parts can be one type. Standardization of equal parts is possible.

FIG. 80 shows the multilayer substrate 437a shown in FIG.
3 shows a liquid crystal display device according to the present invention using ~ d. Multilayer substrate 1 in which semiconductor chip 4 for driving liquid crystal is mounted on the surface of the multilayer substrate
4.437a-d are connected to panel 16. Through the notch 438 for attachment to the multilayer substrates 437a to 437d,
The panel 16, the backlight unit 435 and the exterior decorative case 436 are integrally fixed, and the exterior decorative case upper part 433 is fixed by a fixing screw 434. As a result, in the liquid crystal display device of the present invention, the exterior decorative case can also be used as the exterior case of a PC (personal computer) or the like, and parts such as a frame and a metal frame which are required as separate parts in the conventional liquid crystal display device. Can be reduced, and the multilayer substrate 437a to
Since it is possible to standardize parts by unifying the shape of the mounting notch 438 of d, it is possible to reduce the cost of parts. Furthermore, by reducing the number of parts, the assembly of the liquid crystal display device can be simplified and the number of processing steps can be reduced.

Here, FIG. 81 shows a cross section of a connecting portion of the multilayer substrates 437a to 437a in the liquid crystal display device of the present invention.
The multi-layer substrates 14, 437a-d and the panel terminal 18 are adhesively reinforced by an adhesive member 19 and a mold 21.
In order to improve the strength (vibration resistance) after being assembled in the housing, the end face of the panel terminal 18 and the multilayer substrate 14, 437a
A mold 21 may be provided on the side surface or the back surface of ~ d.

The molding material is epoxy, acrylic,
Urethane, polyester, etc. may be used alone or as a mixture or compound thereof, and may be solvent type, photocurable type or combination type thereof.

Since the positional accuracy between the pattern of the multilayer board and the mounting notch can be set to ± 0.1 mm or less, the positional accuracy between the panel pattern position and the mounting notch. Can secure ± 0.2 mm or less. Since the mounting notch is used for mounting to the exterior decorative case 436 which is a housing, the position reproducibility with respect to the backlight unit 435 and the exterior decorative case 433 are improved.
The position reproducibility with the panel display area can be secured and improved, and when the mounting screw 434 is used for assembly, rework reassembly is easy. In addition, if a tack-shaped component made of plastic with a hook is used, it can be assembled and fixed simply by pushing it in during assembly, and simple assembly is possible. Here, the backlight unit 435 and the exterior makeup case 436 may be fixed by a double-sided tape or the like, or may be fixed by a mounting nail or the like.

[Embodiment 46] Hereinafter, this embodiment will be described with reference to FIGS. 82, 83, 84, 85, 86, 87, 88 and 8.
This will be described using 9.

FIG. 82 shows a liquid crystal display device of the present invention.
A multilayer substrate 6000 according to an embodiment in which three liquid crystal driving semiconductor chips are face-down bonded to the surface of one multilayer substrate is shown.

FIG. 83 is an exploded perspective view of the multilayer substrate 6000 of FIG. Here, the pad pitch P1 on the output side of the liquid crystal driving semiconductor chips 1100, 1200, 1300 is 80 μm, the pitch P2 of the panel terminals 18 is 50 μm, and this is an example in which P1> P2. This panel terminal pitch P2 = 50 μm
Is a fine connection pitch required in a 6-inch class VGA color liquid crystal display device.

1000, 2000, 3000, 400
0 and 5000 are each layer of the multilayer (5 layer) substrate of this embodiment,
1000 is a first layer, 2000 is a second layer, 3000 is a third layer, 4000 is a fourth layer, 5000 is a fifth layer, and liquid crystal driving semiconductor chips 1100, 1200, 13 are provided.
00 is a known method (for example, a semiconductor Au bump is Ag.
Face down bonding is performed on the surface of the first layer 1000 by a method of connecting to a substrate using a paste, a method of using an anisotropic conductive film, a flip chip method of using a solder bump, or the like. After bonding,
Liquid crystal driving semiconductor chips 1100, 1200, 1300
Around and 1100, 1200, 1300 and 1000
Mold 2 to prevent corrosion and reinforcement between the surface and
0 (not shown). The molding material may be epoxy, acrylic, urethane, polyester, etc. alone or a mixture or compound thereof, and may be a solvent type, a thermosetting type, a photocuring type or a combination type thereof.

FIG. 84 shows the first layer wiring, through holes,
It is a top view showing a through hole and the like.

FIG. 85 shows the second layer wiring, through holes,
It is a top view showing a through hole and the like.

FIG. 86 shows third layer wiring, through holes,
It is a top view showing a through hole and the like.

FIG. 87 shows fourth layer wiring, through holes,
It is a top view showing a land and the like.

FIG. 88 shows the fifth layer wiring, through holes,
It is a top view showing a connection terminal and the like.

On the surface of the first layer 1000, 1100,
Input wiring 1 corresponding to 1200, 1300 input pads
110, 1210, 1310 are patterned. In addition, input wiring 1110, 1210, 1310 (however, 1110-1, 1110-N, 1210-1, 1
210-N, 1310-1, and 1310-N) are connected to the bus wiring 2020 of the second layer 2000 via respective through holes 1120, 1220, and 1320. Further, the bus wiring 2020 of the second layer 2000
Through the through hole 2030 of the second layer 2000 and the through hole 3030 of the third layer 3000, and the fourth layer 4
000 bus wiring 4020. Input wiring 1110-1, 1110-N, 1210-1, 1210
-N, 1310-1, and 1310-N are connected in a cascade manner, and thus are provided with wiring different from other input wiring. That is, the input wiring 111 of the liquid crystal driving semiconductor chip 1100.
0-1 is a through hole 1120- of the first layer 1000.
The wiring 4020 is connected through the through holes 2120 of the first and second layers 2000 and the through holes 3120 of the third layer 3000. Liquid crystal driving semiconductor chip 11
Input wiring 1110-N of the third layer 3000 through the through hole 1120-N of the first layer 1000 and the through hole 2120 of the second layer 2000.
Connected to. Further, the liquid crystal driving semiconductor chip 120
The input wiring 1210-1 of 0 is connected to the wiring 3020 of the third layer 3000 through the through hole 1220-1 of the first layer 1000 and the through hole 2220 of the second layer 2000, and the input wiring 1210-N Through the through hole 1220-N of the first layer 1000 and the through hole 2220 of the second layer 2000, the wiring 302 of the third layer 3000.
Connected to 0. In addition, the liquid crystal driving semiconductor chip 13
The input wiring 1310-1 of 00 is connected to the wiring 3020 through the through hole 1320-1 of the first layer 1000 and the through hole 2320 of the second layer 2000. The input wiring 1310-N of the liquid crystal driving semiconductor chip 1300 is connected to the wiring 3020 of the third layer 3000 through the through hole 1320-N of the first layer 1000 and the through hole 2320 of the second layer 2000. There is. Further, the wiring 3020 is connected to the through hole 312 of the third layer 3000.
0 to the wiring 4020 of the fourth layer 4000. Further, the wiring 4020 has a land 404 for wire bonding with another similar multilayer substrate adjacent thereto.
0 is formed. Corresponding to the land 4040, through holes 1010, 2010 and 3010 are provided in the first layer 1000, the second layer 2000 and the third layer 3000 to facilitate wire bonding.

Also, on the surface of the first layer 1000, output wirings 1130, 1230, 13 corresponding to the output pads of the liquid crystal driving semiconductor chips 1100, 1200, 1300.
30 are patterned to form through holes 1140, 1240, 1340 in the first layer 1000 and the second layer 2000.
Through holes 2140, 2240, 2340 and through holes 3140, 3240, 334 in the third layer 3000.
0, through holes 4140, 424 of the fourth layer 4000
0, 4340 and the wiring 5050 through the through holes 5140, 5240, 5340 of the fifth layer 5000,
It is connected to the connection terminal 5060. Where 1100,
Since the terminal pitch of the panel is smaller than the output pad pitch of 1200 and 1300, the pattern is narrowed on the surface of the first layer 1000 so that the respective output pads correspond to the terminals of the panel. In this embodiment, the through holes 1140, 1240, 1340, 2140, 22.
40, 2340, 3140, 3240, 3340, 41
Although 40, 4240, and 4340 are arranged in one row, a staggered arrangement of a plurality of rows may be used. Further, the output pad pitch and the panel terminal pitch may be matched over a plurality of layers. Note that the first layer 1000, the second layer 2000, the third layer 3000, the fourth layer 4000, and the fifth layer
Each of the layers 5000 is a low temperature co-fired ceramic substrate based on alumina. The thickness of each was 0.25 mm. Input wiring 1110, 1210, 1310,
1110-1, 1210-1, 1310-1, 1110
-N, 1210-N, 1310-N, output wiring 113
0, 1230, 1330, wirings 2020, 3020, 4
Reference numerals 020 and 5050 denote fired products of metal pastes such as Au, Ag, AgPd and Cu. Also, the through hole 112
0, 1220, 1320, 1120-1, 1220-
1, 1320-1, 1120-N, 1220-N, 13
20-N, 1140, 1240, 1340, 2030,
2120, 2220, 2320, 2340, 3030,
3120, 3140, 3240, 3340, 4140,
Similarly, 4240, 4340, 5140, 5240, and 5340 are fired products of metal pastes such as Au, Ag, AgPd, and Cu. Also, the land 4040 and the connection terminal 506
Similarly, 0 is a fired product of a metal paste of Au, Ag, AgPd, Cu or the like. Each layer is patterned by a known printing method, and the layers are stacked and baked to be integrated. The thickness of each patterned and baked metal is usually 0.001 mm to 0.0
About 5 mm, but 0.05 m to reduce the resistance
It may be about m to 0.2 mm.

However, the input wirings 1110, 1210, 1310, 1110-1, 12 on the surface of the first layer 1000 are used.
10-1, 1310-1, 1110-N, 1210-
N, 1310-N, output wiring 1130, 1230, 13
30, and the wiring 5050 on the back surface of the fifth layer 5000,
Depending on the wiring pitch, dimensional accuracy, etc., the connection terminals 5060 may be patterned by photolithography or the like after the entire surface of a metal paste such as Au, Ag, AgPd, Cu is printed. The pattern thickness at this time is 0.001 mm to 0.2
It is about mm. Or instead of printing method, Au, Ag,
After forming a thin film by vapor deposition of Cu or the like, or sputtering, a pattern may be formed by a process such as photolithography and plating. The pattern thickness at this time is about 0.0005 mm to 0.1 mm.

Although the multilayer substrate of this embodiment has a five-layer structure, it goes without saying that another number of layers may be used.
Also, one or more ground layers may be provided in the middle for noise countermeasures, static electricity countermeasures, and the like.

As described above, the pad pitch P1 on the output side of the liquid crystal driving semiconductor chip is 80 μm and the connection pitch P2 of the panel terminals is 50 μm.
In the case of the relationship of 2, if a plurality of liquid crystal driving semiconductor chips are mounted on the liquid crystal display device by the conventional TCP, the adjacent TCPs overlap each other and it is difficult to connect the bus wiring board to the input terminal. However, by using the multilayer substrate of this embodiment, it is possible to mount the device in a compact manner without the adjacent multilayer substrates overlapping each other. Therefore, P will increase more and more in the future
As a display device for small information terminal equipment such as DA (Personal Digital Assistance), large capacity display (VGA,
It is possible to provide a liquid crystal display device that has XGA specifications, etc., and is lightweight, thin, and compact.

Further, bonding three liquid crystal driving semiconductor chips to one multi-layer substrate is equivalent to three bonding one liquid crystal driving semiconductor chip to one multi-layer substrate. Since the wiring can be arranged efficiently and the semiconductor chips can also be arranged efficiently, the required area of the multilayer substrate can be reduced and the cost of parts can be reduced.
In addition, it is possible to reduce the man-hours for individually separating the multi-layer substrate (dicing, breaking, etc.) and the man-hours for setting and resetting the multi-layer substrate for bonding and molding the semiconductor chip. Can be provided.

FIG. 89 is a view showing an embodiment in which the multilayer substrate of the embodiment shown in FIG. 82 is connected to a liquid crystal display panel.

A color liquid crystal display type panel 16 (for example, 6
40 * 3 * 480 dot display), the multilayer substrate 6000 of one embodiment shown in FIG. 82 (three 160-output liquid crystal driving semiconductor chips are mounted) is provided on the X side, four are provided, the same as in the first embodiment. Two multi-layered substrates 14 (having one 240-output liquid crystal driving semiconductor chip mounted) are connected to the panel terminals 18 on the Y side. However, the panel wiring and the wiring of the multilayer substrate are not shown in the figure. The connection terminals 13 and 5060 of the multilayer substrates 14 and 6000 and the panel terminals 18 are connected by the connection member 19 as in the first embodiment. The conductive member 19 secures electrical connection and at the same time fixes the multilayer substrates 14 and 6000 to the panel to some extent.

The connecting member 19 used here is an anisotropic conductive film, and is mainly composed of conductive particles and an adhesive.
The conductive particles are solder particles, Ni, Au, Ag, Cu, P
b, Sn, etc., single or plural mixtures, alloys, composite metal particles by alloying or plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.) with Ni, Au,
These are particles of single or multiple plating such as Cu and Fe, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound. This anisotropic conductive film is used to connect the panel terminals 18 to the connection terminals 13 and 50 of the multilayer substrates 14 and 6000.
60, and when a thermosetting or a blend type adhesive of thermoplastic and thermosetting is used for the anisotropic conductive film, the heating and pressing head is pressed against the multilayer substrates 14 and 6000. It is cured and connected. When a UV curable type adhesive is used for the anisotropic conductive film, a pressure head is pressed against the multilayer substrates 14 and 6000, and UV is applied from the panel terminal 18 (glass side) side to cure. Another connecting member is an anisotropic conductive adhesive, which is mainly composed of conductive particles and an adhesive. The conductive particles are solder particles, Ni, Au, Ag, Cu, Pb, Sn, etc., single or plural mixtures, alloys, or composite metal particles by plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.), Ni, Au. , Cu, Fe, etc., particles of which single or plural plating has been performed, carbon particles and the like. The adhesive is styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., alone or as a mixture or compound. This anisotropic conductive adhesive is in a liquid or paste form, and is arranged at the connection portion of the panel terminals 16 by a known method such as a printing method or a dispensing method using a dispenser. When a thermosetting or a blend type adhesive of thermoplasticity and thermosetting is used as the anisotropic conductive adhesive, it is cured and connected by pressing a heating and pressing head against the multilayer substrates 14 and 6000. When a UV curable type adhesive is used as the anisotropic conductive adhesive, the pressure head is pressed against the multilayer substrates 14 and 6000, and UV irradiation is performed from the panel terminal 18 (glass side) side to cure the adhesive. .

A mold 21 is provided (not shown in the figure) to protect the exposed portion of the panel terminal 18 from corrosion. In addition, the mold 21 is a multilayer substrate 14,
It also has the role of fixing 6000 to the panel. The molding material may be epoxy, acrylic, urethane, polyester, etc., or a mixture or compound of some of them, and may be a solvent type, a thermosetting type, a photocuring type or a combination thereof.

Connection of bus wiring between the adjacent multilayer substrates 14 and between the multilayer substrates 6000 is wire-bonded by the wire 15 via the lands 7 and 4040. Further, the input terminals on one side of each of the multilayer substrate 14 and the multilayer substrate 6000 located at the X-side and Y-side ends of the panel are wire-bonded to the relay substrate 7000 by the wires 15. Further, the relay board 7
A connection member 8000 for inputting a signal, a power source, and the like from the outside is connected to 000. This connecting member 800
Although not shown in FIG. 0, the wiring pattern 0 may have one or more wiring patterns, and may also have electronic components mounted thereon. As the wire 15, a metal such as Au, Al, or Cu or an alloy of those metals (including one containing Be, Si, Mg, or the like) can be used. In addition, a mold 21 is similarly provided to protect the wire bonding portion, the wire portion, etc. from corrosion, and to mechanically reinforce (not shown in the figure). The width to be wire-bonded is within the width of the multi-layer substrate, which makes it compact.

Since one liquid crystal driving semiconductor chip bonded to three multilayer substrates is used here, one liquid crystal driving semiconductor chip bonding to one multilayer substrate is connected. In some cases, the number of connecting points between the multilayer substrates has been reduced by 8 (from 11 to 3). Along with this, the number of members of the wire 15 and the number of wire bonding steps can be reduced.

As described above, by using the multi-layer substrate of this embodiment, the cross wiring of the bus wiring is conventionally performed using another bus substrate in the TAB method, but the cross wiring is performed in the same multi-layer substrate. It has been processed. Therefore,
By making the wiring in the board high density, it is possible to make it more compact than the TAB method, and it is possible to reduce the cost because another bus board is not used.

Further, in the conventional COG method, since the bus wiring is cross-wired on the panel substrate, a large area for the bus wiring is required, and metal wiring is required to reduce the wiring resistance value, and the cost is reduced. While it becomes high,
By using the multilayer substrate of this embodiment, it is possible to save the bus wiring area and reduce the cost as compared with the COG method.

Also, in the case where the pad pitch P1 on the output side of the liquid crystal driving semiconductor chip is 80 μm and the connection pitch P2 of the panel terminals is 50 μm such that P1> P2, the adjacent multilayers It has a large capacity display (VGA, XGA, etc.) as a display device for small information terminal devices such as PDAs (Personal Digital Assistance), which can be mounted compactly without the overlapping of boards and will increase more and more in the future. It is possible to provide a liquid crystal display device that is lightweight, thin, and compact.

[Embodiment 47] FIG. 90 is a view showing an embodiment of the liquid crystal display device according to the present invention and is a view showing a liquid crystal panel constituting the liquid crystal display device.

Further, FIG. 91 is a diagram showing a cross-sectional view taken along the line AB of the liquid crystal display panel 16 shown in FIG.

The liquid crystal display panel is composed of the transparent substrate 5 on the COM side.
02 and a SEG side transparent substrate 501 having a length in the vertical and horizontal directions longer than that of the COM side transparent substrate 502, and glass is used for the transparent substrate. On the SEG side transparent substrate 501, SEG side electrode terminals 503 made of indium oxide, SEG side transparent electrodes 505, COM side electrode terminals 504 formed on the SEG side transparent substrate, and on the COM side transparent substrate 502 are COM. The side transparent electrodes 506 are formed by a sputtering method or a vapor deposition method, respectively. The COM side transparent substrate 502 and the SEG side transparent substrate 501 are formed.
A liquid crystal 509 is sealed between them and by a sealant 508. The SEG side electrode terminal 503 on the SEG side transparent substrate 501 is an extension of the SEG side transparent electrode 505 formed on almost the entire surface of the SEG side transparent substrate 501.
This is a terminal for connecting a liquid crystal driving drive circuit that drives the side. A COM-side electrode terminal 504, which is also formed on the SEG-side transparent substrate 501, is a terminal for connecting a liquid crystal driving integrated circuit that drives the COM side.
The COM-side transparent electrode 506 formed on almost the entire surface of the COM-side transparent substrate 502 is connected to the COM-side transparent electrode 506 by a conductive material 507.

A connection structure between the COM side transparent electrode 506 on the COM side transparent substrate 502 and the COM side electrode terminal 504 on the SEG side transparent substrate 501 will be described with reference to FIG. COM-side transparent electrode 50 on COM-side transparent substrate 502
6 is S in the liquid crystal 509 inside the sealing material 508.
In the COM side electrode terminal 504 on the EG side transparent substrate 501,
It is electrically connected by the conductive material 507. As the conductive material 507, a metal paste such as Au, Ag, AgPd, or Cu, an anisotropic conductive adhesive, a conductive rubber having anisotropic conductivity, or the like can be used. Further, as the anisotropic conductive adhesive, as conductive particles, solder particles, Ni, A
u, Ag, Cu, Pb, Sn, etc., alone or in combination,
Conductive particles obtained by plating alloy metal, composite metal particles by plating, etc., plastic particles (polystyrene, polycarbonate, acrylic, etc.) with single or multiple plating of Ni, Au, Cu, Fe, etc. Anisotropic conductive adhesives that can use conductive particles and the like, and use styrene-butadiene-styrene (SBS) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., or a mixture or compound of two or more thereof as an adhesive. Can be used. Further, as this anisotropic conductive adhesive, a sheet-like one having a thickness of several microns to several tens of microns, a paste-like one or the like can be used.

The method of applying the conductive material 507 is as follows.
It depends on what kind of conductive material is used. As the conductive material 507, Au, Ag, AgPd, Cu
When a conductive material having no anisotropic conductivity such as a metal paste is used, each of the COM-side electrode terminals 504 has a C
Only the portion facing the OM side transparent electrode 506 is coated or printed so as not to short-circuit with the adjacent transparent electrode. On the other hand, when various anisotropic conductive adhesives are used, COM
Since electrical conduction can be obtained only in the direction from the side electrode terminal 504 to the COM side transparent electrode 506, a short-circuit with an adjacent transparent electrode may be formed in a portion of the COM side electrode terminal 504 facing the COM side transparent electrode 506. It is possible to apply continuously without applying. Therefore, it is large and CO
When manufacturing a liquid crystal display panel having a large number of M-side electrode terminals 504, it is more productive to use various anisotropic conductive adhesives as the conductive material 507.

In this embodiment, the COM side transparent electrode 506 on the COM side transparent substrate 502 is connected to the COM side electrode terminal 504 on the SEG side transparent substrate 501 by the conductive material 507.
, And all the electrode terminals are formed on the SEG side transparent substrate 501. On the contrary, the COM side transparent substrate 502
Is formed to be wider and longer than the SEG side transparent substrate 501, and the SEG side transparent electrode 5 on the SEG side transparent substrate 501 is formed.
05 may be connected to the electrode terminals on the COM side transparent substrate 502 by a conductive material, and all the electrode terminals may be provided on the COM side transparent substrate 502.

Also, in this embodiment, the SEG side transparent substrate 50 is used.
1. Glass is used for the COM-side transparent substrate 502,
As the material of these transparent substrates, epoxy, acrylic, polyethylene terephthalate, polyester, polyether sulfone, polycarbonate, cellulose triacetate, polysulfone, polyetheretherketone, polyarylate, etc. may be used alone or in combination thereof. A hard transparent plastic plate, a flexible transparent film substrate, or the like can be used.

With the above configuration, all the liquid crystal drive circuits can be connected without turning over the liquid crystal display panel in the manufacturing process of the liquid crystal display panel, which simplifies the manufacturing process and reduces the manufacturing cost. The liquid crystal display device can be reduced, and thus a cheap and high-quality liquid crystal display device can be provided. In addition, C on the COM-side transparent substrate 502
The OM side transparent electrode 506 is a C on the SEG side transparent substrate 501.
The portion connected to the OM side electrode terminal 504 by the conductive material 507 connects the liquid crystal 509 to the SEG side transparent substrate 501 and C.
Sealing material 508 sealed between the transparent substrate 502 and the OM side
Since the conductive material 507 does not come into direct contact with air or chemicals because it is inside (on the side of the liquid crystal 509), a member for protecting the conductive material 507 and a process are not required.
There are advantages that the manufacturing process is not complicated and the manufacturing cost can be suppressed.

[Embodiment 48] FIG. 92 is a view showing an embodiment of the liquid crystal display device according to the present invention. The COM side transparent electrode 506 on the COM side transparent substrate 502 and the COM side electrode on the SEG side transparent substrate 501. For electrical connection with the terminal 504,
It is the figure which showed the liquid crystal panel which used the electrically conductive material 510 which doubled as the sealing material.

This liquid crystal display panel is similar to that of Example 47 in appearance.
90 is similar to the liquid crystal panel shown in FIG. 90 and includes a COM-side transparent substrate 502 and an SEG-side transparent substrate 501 that is longer than the COM-side transparent substrate 502 in the vertical and horizontal directions. Uses glass. On the SEG side transparent substrate 501, an SEG made of indium oxide is formed.
The side electrode terminal 503, the SEG side transparent electrode 505, the COM side electrode terminal 504 formed on the SEG side transparent substrate, and the COM side transparent electrode 5 on the COM side transparent substrate 502.
06 are formed by the sputtering method or the vapor deposition method, respectively. The SEG side electrode terminal 503 on the SEG side transparent substrate 501 is an extension of the SEG side transparent electrode 505 formed on almost the entire surface of the SEG side transparent substrate 501,
It is a terminal for connecting a liquid crystal driving integrated circuit that drives the SEG side. A COM-side electrode terminal 504, which is also formed on the SEG-side transparent substrate 501, is a terminal for connecting a liquid crystal driving integrated circuit that drives the COM side, and is almost entirely over the COM-side transparent substrate 502. The formed COM-side transparent electrode 506 is electrically connected by the conductive material 510 that also serves as a sealing material. Further, the conductive material 510 also serving as the sealing material has a role of enclosing the liquid crystal 509 between the SEG side transparent substrate 501 and the COM side transparent substrate 502.

A method of forming the conductive material 510 that also serves as the sealing material will be described below. As shown in FIG. 92, a conductive material is applied to almost the center of a portion to which an epoxy resin, which has been conventionally used as a sealing material, is applied, and the COM side electrode terminal 504 overlaps with the COM side transparent electrode 506. 507 is applied or printed. Conductive material 5
As 07, a metal paste such as Au, Ag, AgPd, or Cu, or as conductive particles, solder particles, Ni,
Ni, Co, Pd, Au, Ag, C for Au, Ag, Cu, Pb, Sn, etc., alone or a mixture thereof, composite metal particles by alloying or plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.).
u, Fe, Sn, Pb, etc., or particles obtained by plating some of them, carbon particles, etc., and styrene butadiene styrene (SBS) type, epoxy type, acrylic type, polyester type, urethane type etc. as adhesive Alternatively, an anisotropic conductive adhesive using some mixture or compound thereof can be used. When the metal paste is used as the conductive material, the COM-side electrode terminal 50
In order not to short-circuit with the adjacent transparent electrode, only in the portion of each of the four that faces the COM-side transparent electrode 506,
Apply or print. On the other hand, when various anisotropic conductive adhesives are used, electrical conduction can be obtained only in the direction from the COM side electrode terminal 504 to the COM side transparent electrode 506, so that the COM side of the COM side electrode terminal 504 can be obtained. The portion facing the transparent electrode 506 can be continuously applied without worrying about a short circuit with an adjacent transparent electrode.
After this, the epoxy resin used as the sealing material,
Printing or coating is performed so as to surround the conductive material previously coated or printed. After that, the SEG-side transparent substrate 501 and the COM-side transparent substrate 502, which have been aligned, are overlapped, and heated and pressurized or pressurized UV is irradiated. By doing so, it is possible to form the conductive material 510 which also functions as a sealant having a conductive material in the central portion.

Further, the solder particles, Ni, Au and A are uniformly dispersed in the epoxy resin which has been conventionally used as a sealing material.
Ni, Co, Pd, Au, Ag, Cu, F for g, Cu, Pb, Sn, etc. alone or some of them mixed, composite metal particles by alloying or plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.)
It is also possible to use, as the conductive material 510 also functioning as a sealing material, particles of e, Sn, Pb or the like, or particles obtained by plating some of them, or mixed with conductive particles such as carbon particles. Further, without using an epoxy resin that has been conventionally used as a sealing material, solder particles, Ni, Au, Ag, Cu, Pb, Sn, etc. alone or a mixture thereof may be used as conductive particles, alloys or plating. Ni, Co, Pd, A on composite metal particles and plastic particles (polystyrene, polycarbonate, acrylic, etc.)
u, Ag, Cu, Fe, Sn, Pb, etc., or particles plated with some of them, carbon particles, etc. are used, and styrene butadiene styrene (SB
It is possible to use only an anisotropic conductive adhesive containing S) type, acrylic type, polyester type, urethane type or the like, or a mixture or compound of some of them, and use this as a conductive material that also serves as a sealing material. In this case, as the anisotropic conductive adhesive, a sheet-shaped one having a thickness of several microns or a paste-shaped one can be used.

In this embodiment, the COM-side transparent electrode 506 on the COM-side transparent substrate 502 is connected to the COM-side electrode terminal 504 on the SEG-side transparent substrate 501 using a conductive material, and the SEG-side transparent substrate 501 is connected. All the electrode terminals are formed on the top, but on the contrary, the COM side transparent substrate 502 is SE
The width and the length are formed larger than the G side transparent substrate 501,
The SEG side transparent electrode 505 on the SEG side transparent substrate 501 is connected to the electrode terminal on the COM side transparent substrate 502,
All electrode terminals may be provided on the side transparent substrate 502.

Further, in this embodiment, the SEG side transparent substrate 50 is used.
1. Glass is used for the COM-side transparent substrate 502,
As the material of these transparent substrates, epoxy, acrylic, polyethylene terephthalate, polyester, polyether sulfone, polycarbonate, cellulose triacetate, polysulfone, polyetheretherketone, polyarylate, etc. may be used alone or in combination thereof. A hard transparent plastic plate, a flexible transparent film substrate, or the like can be used.

With the above-mentioned structure, the area not directly related to the display between the seal material and the conductive material can be made smaller than that of the liquid crystal display panel shown in the embodiment 47, and the same screen display range can be obtained. In the liquid crystal display panel, the size of the entire display device can be made more compact. Moreover, in the manufacturing process of the liquid crystal display panel, all the liquid crystal drive circuits can be connected without turning over the liquid crystal display panel, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. It is possible to provide a light-weight and compact liquid crystal display device.
Further, the COM-side transparent electrode 5 on the COM-side transparent substrate 502
06 is the COM side electrode terminal 5 on the SEG side transparent substrate 501
Since 04 is connected by the conductive material 510 which also serves as a sealing material, the conductive material portion does not come into direct contact with air or chemicals, and a member for protecting the conductive material 507 and a process are not required. There are advantages that the manufacturing process is not complicated and the manufacturing cost can be suppressed.

[Embodiment 49] FIG. 93 is a view showing an embodiment of the liquid crystal display device according to the present invention. The transparent electrode on the COM side transparent substrate 502 is connected to the electrode terminal on the SEG side transparent substrate 501. FIG. 3 is a diagram showing an embodiment in which a multi-layer substrate 14 to which a liquid crystal driving semiconductor chip 4 is face-down bonded is mounted on a liquid crystal display panel 16 in which all electrode terminals are provided on a SEG side transparent substrate. Further, FIG. 94 is an enlarged view of the portion B of FIG. 93.

The multi-layer substrate 14 is electrically and mechanically connected to the electrode terminals on the SEG side transparent substrate 501 forming the liquid crystal panel 16 by using an anisotropic conductive adhesive. The anisotropic conductive adhesive used for this connection includes, as conductive particles, solder particles, Ni, Au, Ag, Cu, Pb,
Ni alone on composite metal particles such as Sn alone or a mixture of some of them, alloys or plating, plastic particles (polystyrene, polycarbonate, acrylic, etc.)
Co, Pd, Au, Ag, Cu, Fe, Sn, Pb, etc., or particles plated with some of them, carbon particles, etc. are used, and styrene butadiene styrene (SBS) type, acrylic type, polyester type as an adhesive agent ,
It is possible to use a urethane type or the like alone or a mixture of some of them or a compound thereof.

The electrical connection of the bus wiring between the adjacent multi-layer substrate 14 is made by the wire 15 using the wire bonding method. As the wire 15, a metal such as Au, Al, or Cu, or an alloy of these metals can be used. In addition, the SEG side transparent substrate 5
On 01, a connection wiring 601 for connecting the multilayer substrate 14 on which the liquid crystal driving semiconductor chip 4 driving the SEG side is mounted and the multilayer substrate 14 on which the liquid crystal driving semiconductor chip 4 driving the COM side is mounted is formed. The multi-layer substrate 14 that drives the SEG side and the multi-layer substrate 14 that drives the COM side
Are connected by the connection wiring 601 and the wire 15. The connection wiring 601 may be a transparent electrode on which a metal thin film is formed by plating, a sputtering method, an evaporation method, or the like. The transparent electrode is plated with Ni, and then plated with Au. Alternatively, a material plated with Al or the like can be used. A signal from the external power supply circuit board is connected from the terminal of the built-in common input wiring of the rightmost multilayer board of the series of multilayer boards 14 using the tape electric wire 511 or the like.

Although not shown in the figure because the figure becomes complicated, the portion where the multi-layer substrate 14 is mounted includes the wires 15, the multi-layer substrate 14, the liquid crystal driving semiconductor chip 4, and the SEG side. In order to protect the electrode terminals formed on the transparent substrate 501, the connection wiring 601, and the like, they are covered with an ultraviolet curable resin, a silicone resin, or the like.

[0278] In this way, the multilayer substrate 1 incorporating the bus wiring is provided.
By using No. 4, the bus circuit board which is necessary when using the conventional TCP is not required. Therefore, when using the liquid crystal display panel having the same display area, the area other than the display portion is set to the conventional TCP. It can be made smaller than the liquid crystal display device using.

Further, since all the electrode terminals are provided on the SEG side transparent substrate 501, in the manufacturing process of connecting the multilayer substrate 14 on which the liquid crystal driving semiconductor chip 4 is mounted to the electrode terminals on the SEG side transparent substrate 501, Liquid crystal display panel 16
You don't have to turn it over. For this reason, the manufacturing apparatus can be simplified, and the uncured resin does not run down even when the ultraviolet curable resin or the silicone resin is applied to protect the mounting portion of the multilayer substrate 14. It has advantages that the time can be shortened and the manufacturing cost can be reduced.

[Embodiment 50] Another embodiment of the present invention
This will be described below with reference to FIGS. 95, 96, 97, 98, and 99.

FIGS. 95 and 96 show the SEG side liquid crystal drive circuit and C of the liquid crystal display panel in which the electrode terminals are provided only on the SEG side transparent substrate in the liquid crystal display device according to the present invention.
Installed at the corner where the OM side liquid crystal drive circuit contacts,
3 illustrates a connection board for supplying power and signals to a liquid crystal drive circuit.

The connection board 602 shown in FIG.
This is for connecting a common bus circuit of the side liquid crystal drive circuit and the COM side drive circuit, and a connection wiring 605 formed by Au paste printing is provided on a connection substrate 602 made of a ceramic material.

A connection board with input terminals 607 shown in FIG. 96 is obtained by adding a connection board input terminal 606 for inputting a power supply and a signal from an external power supply circuit to the connection board shown in FIG. , Connection board upper layer board 603 with input terminals and connection board lower layer board 604 with input terminals
It has a two-layer structure. The connection board upper layer substrate 603 with an input terminal and the connection board lower layer substrate 604 with an input terminal are made of ceramics, and the connection board input terminal 606 and the connection wiring 605 are connected with the input terminal on the connection board upper layer board 603 with an input terminal. Substrate lower layer substrate 60
Connection wirings 605 are formed on each of the surfaces 4 by Au paste printing. Connection board input terminal 606 and connection wiring 60 on connection board upper layer board 603 with input terminal
5 and the connection wiring 605 on the connection substrate with input terminal lower layer substrate 604 are connected by a through hole provided on the connection substrate with input terminal upper layer substrate 603, and the connection substrate with input terminal upper layer substrate 603 and the input terminal The power and signals input from the connection board input terminal 606 are connected to the SEG by the connection wiring 605 on the connection board lower layer board 604.
Side and COM side drive circuits, respectively.

Here, the connection board 60 of the wiring board is used.
2, a ceramic substrate is used as the connection substrate upper layer substrate 603 with an input terminal and a connection substrate lower layer substrate 604 with an input terminal, and Au paste is used for the connection wiring 605, but the connection substrate 602, the connection substrate upper layer substrate 603 with an input terminal,
As the material of the connection substrate lower layer substrate 604 with an input terminal, various resin substrates such as a glass epoxy substrate and a phenol resin substrate, glass, a polyimide substrate, and the like can be used, and as the connection wiring 605, Ag,
AgPd, Cu or other metal paste fired product, Cu, Au,
A metal thin film of Al or the like formed on the wiring by an etching method, a metal such as Cu, Au, or Al patterned on the wiring by a vapor deposition method or a sputtering method, Cu,
It is possible to use those in which thin film wiring such as Au or Al is patterned by a plating method, or those in which a metal foil such as Cu is patterned by an etching method.

Examples of using these wiring boards for liquid crystal panels are shown in FIGS. 97, 98 and 99.

FIG. 97 shows a liquid crystal display panel in which electrode terminals are provided only on the SEG side transparent substrate, at a corner portion where the SEG side liquid crystal drive circuit and the COM side liquid crystal drive circuit are in contact with each other, a power source and a signal are supplied to the liquid crystal drive circuit. 2 is a view showing a liquid crystal display device on which a connection board for supplying the liquid crystal is mounted.

FIG. 98 is an enlarged view of portion C in FIG. 97.

FIG. 99 is an enlarged view of portion D in FIG. 97.

The liquid crystal display panel 16 comprises a SEG side transparent substrate 501 and a COM side transparent electrode 502.
The transparent electrode formed on the M side transparent substrate 502 is a COM formed on the SEG side transparent substrate by a conductive material.
It is connected to the side electrode terminal. As a result, the multi-layer substrate 14 on which the liquid crystal driving semiconductor chip 4 is mounted is entirely SEG.
It is mounted on the side transparent substrate 501 and is connected to the electrode terminals on the SEG side transparent substrate by an anisotropic conductive adhesive as in the first embodiment. All the common bus circuits of the adjacent multilayer substrates 14 are electrically connected by the Au wire 15 by the wire bonding method.

At the corner portion where the multilayer substrate 14 on which the liquid crystal driving semiconductor chip 4 on the COM side is mounted and the multilayer substrate 14 on which the liquid crystal driving semiconductor chip 4 on the SEG side is mounted are in contact with each other, the C portion is the multilayer on the SEG side. A connection board 602 for connecting the board 14 and the COM-side multi-layer board 14 is connected, and a SEG-side multi-layer board 14 and a COM-side multi-layer board 14 are connected to a portion D.
In addition, the connection boards with input terminals 607 having the connection terminals with the power supply circuit are mounted on the SEG side transparent board 501 by using anisotropic conductive adhesives. The SEG side transparent substrate 5 is used as the connection substrate 602 and the connection substrate 607 with an input terminal.
The anisotropic conductive adhesive is used in spite of the fact that the terminal for electrical connection with the transparent electrode substrate on 01 is not installed.
Since it is connected to the electrode terminals on the side transparent substrate 501,
This is because it is advantageous to use the same one in the manufacturing process for cost reduction. Of course, other adhesives such as ultraviolet curable resins, thermosetting resins, various resinous adhesives using organic solvents, and various instant adhesives can also be used. The connection board 602 and the connection board with input terminal 607 are connected to the adjacent SEG-side multilayer board 14 and the COM-side multilayer board 14 by the Au wire 15 by a wire bonding method, thereby forming a series of SEG-side multilayer boards. A power supply and an image signal are sent to. Further, the connection with the external power supply circuit is performed by the connection board input terminal 6 installed on the connection board with input terminal 607.
06, which supplies power and signals to the entire liquid crystal display device.

Although the connection substrate 602 having only the connection wiring 605, the connection wiring 605, and the connection substrate with an input terminal 607 having the connection substrate input terminal 606 are used here to configure the liquid crystal display device. , The SEG-side multilayer board 14 and the COM-side multilayer board 14 are connected to each other by using only two connection boards 602 having only the connection wiring 605.
02, and the signal input from the external power supply circuit is
Multilayer substrate 1 on the side opposite to where a series of connection substrates for the SEG-side multilayer substrate are mounted (on the side without COM side multilayer substrate)
Alternatively, the configuration may be such that the input is made from the common bus wiring terminal of No. 4.
On the contrary, a liquid crystal display device is configured by using two connection boards 607 having an input terminal having both the connection wiring 605 and the connection board input terminal 606, and the liquid crystal driving on the SEG side mounted above and below the liquid crystal display panel. The semiconductor chip may have a uniform voltage level. In addition, here, the common bus circuit between adjacent multilayer substrates and the connection between the multilayer substrate and the connection substrate are connected by Au by a wire bonding method.
Wires are used, but Al and Cu are also used for this connection.
Also, it is possible to electrically connect by wires such as a wire bonding method, solder, anisotropic conductive adhesive, etc., using wires made of those alloys, flexible circuit boards, various electric wires including vinyl electric wires, and the like. .

With the above-mentioned structure, the common bus circuit of the SEG-side multilayer board and the COM-side multilayer board can be connected with a wiring having a resistance lower than that of the wiring in which the transparent electrode is metal-plated. The display quality of the liquid crystal display device can be further improved. Moreover, since it is not necessary to perform metal plating on the transparent electrode, the manufacturing cost can be reduced.

[Embodiment 51] FIG. 100 is a view showing an embodiment of the liquid crystal display device according to the present invention. The transparent electrode on the COM side transparent substrate 502 is connected to the electrode terminal on the SEG side transparent substrate 501. , A liquid crystal display panel 16 on which all electrode terminals are provided on the SEG-side transparent substrate and a multi-layer substrate 14 to which the liquid crystal driving semiconductor chip 4 is face-down bonded is mounted as a liquid crystal driving circuit on the SEG side is mounted on the liquid crystal on the COM side. A power supply circuit-integrated COM multi-layer substrate 60 in which the liquid crystal drive semiconductor chip 4 and a power supply circuit are integrated as a drive circuit
9 shows a liquid crystal display device in which No. 8 is mounted.

FIG. 101 shows the power supply circuit integrated CO of FIG.
FIG. 8 is an enlarged view of a mounting portion of an M multi-layer substrate 608.

Further, FIG. 102 is a sectional view of the COM multilayer substrate 608 integrated with a power supply circuit.

The power supply circuit-integrated COM multi-layered substrate 608 is a liquid crystal driving semiconductor chip 4 on the COM side which is face-down bonded onto the power supply-integrated COM multi-layered substrate 608.
Power supply and COM side image signal to the
Multilayer substrate 1 on which a G side liquid crystal driving semiconductor chip 4 is mounted
4 also has a function of supplying a power source and an SEG side image signal.

The structure of the power circuit integrated COM multilayer substrate 608 will be described with reference to FIGS. 101 and 102. The power circuit integrated COM multilayer substrate 608 has a multilayer structure including an upper substrate 610 made of ceramics, an intermediate substrate 611, and a lower substrate 612.
The various electronic components 609 forming the power supply circuit are mounted on the upper substrate 610 by a known method (for example, a method of connecting to the substrate using Ag paste, a method of using an anisotropic conductive adhesive, etc.). Note that FIG. 100 and FIG.
In FIG. 1, the illustration of each wiring pattern is omitted. After mounting, the liquid crystal driving semiconductor chip 4 and various electronic components 60
9 is molded for the purpose of preventing corrosion and reinforcement between the liquid crystal driving semiconductor chip 4 and the surface of the upper substrate 610. However, the illustration of the mold is omitted because the figure becomes complicated. A circuit pattern 613-1 corresponding to an input pad of each liquid crystal driving semiconductor chip 4 is formed on the surface of the upper substrate 610. The circuit pattern 613-1 corresponding to the input pads of the liquid crystal driving semiconductor chip 4 includes the through hole 615-1 and the intermediate substrate 6.
11 circuit pattern 613-2, through hole 615
-3, the circuit pattern 613-3 on the lower layer substrate 612, and the through hole 615-4, the same power supply circuit integrated CO
The M multilayer board 608 is connected to the circuit pattern 613-4 of the power supply circuit including various electronic components 609. Note that here, the through hole 615-1 and the intermediate substrate 611.
Upper circuit pattern 613-2, through hole 615-
3, the circuit pattern 613-3 on the lower layer substrate 612 and the through hole 615-4 are connected to the circuit pattern 613-4 of the power supply circuit. However, in the layout of the circuit pattern, the liquid crystal driving semiconductor chip 4 is used. If there is no problem such as another circuit pattern crossing between the circuit pattern 613-1 corresponding to the input pad and the circuit pattern 613-4 of the power supply circuit, it corresponds to the input pad of the liquid crystal driving semiconductor chip 4. The circuit pattern 613-1 and the circuit pattern 613-4 of the power supply circuit may be directly connected on the upper layer substrate 610. Further, circuit patterns 613-5 corresponding to the output pads of each liquid crystal driving semiconductor chip 4 are formed on the upper layer substrate 610, and a circuit pattern 613 corresponding to the output pads of each liquid crystal driving semiconductor chip 4 is formed. -5 is connected to a panel connection terminal 614 formed on the lower substrate 612 through the through hole 615-2.

Here, here, the upper layer substrate 610, the intermediate substrate 611, which constitute the power circuit integrated COM multilayer substrate 608,
Although a low-temperature co-firing ceramics substrate of alumina base material is used as the lower layer substrate 612, other various resin-based substrates such as glass epoxy substrate and phenol resin-based substrate, flexible substrates such as polyimide and aramid, glass, hard plastic, Etc. can be used.

Further, here, the circuit patterns 613-1,
613-2, 613-3, 613-4, Au paste fired material is used as the connection terminal 614 to the panel.
These circuit patterns 613-1, 613-2, 613
-3, 613-4, Ag as a connection terminal 614,
AgPd, Cu or other metal paste fired product, Cu, Au,
A metal thin film of Al or the like formed on the wiring by an etching method, a metal such as Cu, Au, or Al patterned on the wiring by a vapor deposition method or a sputtering method, Cu,
It is possible to use those in which thin film wiring of Au, Al or the like is formed by plating, or those in which metal foil such as Cu is formed by etching.

[0300] The power supply circuit integrated C configured as described above
The OM multilayer substrate 608 is electrically and mechanically connected to the electrode terminals provided on the SEG-side transparent substrate 501 forming the liquid crystal display panel 16 using an anisotropic conductive adhesive.
Examples of the anisotropic conductive adhesive include solder particles as conductive particles, Ni, Au, Ag, Cu, Pb, Sn and the like alone or a mixture thereof, composite metal particles by alloying or plating, plastic particles (polystyrene). , Polycarbonate, acrylic, etc.) Ni, Co, Pd, A
u, Ag, Cu, Fe, Sn, Pb, etc., or particles plated with some of them, carbon particles, etc. are used, and styrene butadiene styrene (SB
S) -based, epoxy-based, acrylic-based, polyester-based, urethane-based, etc., or a mixture of some of them or a compound thereof may be used.

Further, the COM multi-layer substrate 6 integrated with the power supply circuit
08 is a power source for driving the SEG side, and an image signal SE
With the function of supplying to the G side liquid crystal driving semiconductor chip,
A connection terminal to the SEG side drive circuit formed on the upper layer substrate 610 of the power circuit integrated COM substrate 608 and the adjacent SEG side multilayer substrate 14 are connected by using an Au wire 15 using a wire bonding method, A power source and an image signal are supplied to the multi-layer substrate 14 on the SEG side.

It should be noted that this COM multi-layer substrate 6 with integrated power supply circuit
08 and adjacent SEG-side multilayer substrate 14 can be electrically connected by using a wire made of Al, Cu, or an alloy thereof in addition to the Au wire, and by using a flexible wiring board, soldering, Alternatively, they may be electrically or mechanically connected by an anisotropic conductive adhesive.

With such a structure, it is not necessary to connect a separate power supply circuit to the liquid crystal display device as in the conventional case, and it is not necessary to connect each multilayer substrate to the liquid crystal display panel one by one. Therefore, the manufacturing cost can be significantly reduced by shortening the steps and significantly reducing the time required for the production. Further, since a long wiring for connecting a power source and a signal is not required, intrusion of noise from the outside is reduced, and a good display can be obtained.

[Embodiment 52] FIG. 103 is a view showing an embodiment of a liquid crystal display device according to the present invention. Of two conventionally used transparent substrates sandwiching a liquid crystal, a common electrode (COM) is used. The length of the side transparent substrate 502 is made longer than that of the segment electrode (SEG) side transparent substrate 501, and
The SEG side transparent substrate 5 is wider than the width of the COM side transparent substrate 502.
01 is made wider so that the two COM-side transparent substrates 502 and the SEG-side transparent substrates 501 are overlapped and the liquid crystal is sealed by the sealant 508. Transparent substrate 501
SEG side transparent electrode 505 and COM formed on top
COM side transparent electrode 50 formed on the side transparent substrate 502
6 is extended, and the liquid crystal driving semiconductor chip 4 as the COM side liquid crystal driving circuit and the power source circuit are integrated with the COM side transparent electrode of the liquid crystal panel 16 which is used as a connection terminal with the liquid crystal driving circuit. The liquid crystal display device in which the COM multilayer substrate 608 is mounted is shown from the SEG side transparent substrate 501 side.

FIG. 104 is a view showing the liquid crystal display device shown in FIG. 103 from the COM side transparent substrate 502 side.

The power circuit integrated COM multilayer substrate 608 is electrically and mechanically connected to the transparent electrode terminals provided on the COM side transparent substrate 502 constituting the liquid crystal display panel 16 by using an anisotropic conductive adhesive. To be done.

[0307] Further, the COM multi-layer substrate 6 with the integrated power supply circuit
08 is a power source for driving the SEG side, and an image signal SE
A connection terminal for connecting to the SEG side drive circuit, which has a function of supplying to the G side liquid crystal driving semiconductor chip and is formed on the power circuit integrated COM board 608, is connected to the SEG side bus board 50043 using a tape wire 511. Through the SEG-side bus board 50043, power and image signals are supplied to the SEG-side liquid crystal driving semiconductor chip 4 mounted on each TCP 50042.

With such a structure, even when the conventionally used liquid crystal display panel is used, it is not necessary to connect a separate power supply circuit and the liquid crystal display device as in the conventional case, and liquid crystal driving is performed. Since it is not necessary to connect each substrate with integrated circuits for liquid crystal display panel to each one, it is possible to shorten the process and the time required for the manufacturing, and to significantly reduce the manufacturing cost. You can Further, since a long wiring for connecting a power source and a signal is not required, intrusion of noise from the outside is reduced, and a good display can be obtained.

[Embodiment 53] FIG. 105 is a view showing an embodiment of the liquid crystal display device according to the present invention. The transparent electrode on the COM side transparent substrate 502 shown in the embodiment 47 or the embodiment 48 is SEG. Conventionally used for mounting a liquid crystal driving semiconductor chip on the liquid crystal display panel 16 according to the present invention, which is connected to the electrode terminals on the side transparent substrate 501 and provided with all the electrode terminals on the SEG side transparent substrate 501. The TCP 50042 mounted with the liquid crystal driving semiconductor chip 4 is mounted. Each TCP 50042 is
SEG side bus boards 50043 and C for transmitting an input signal to a liquid crystal driving semiconductor chip mounted on 50042
It is electrically and mechanically connected to the OM side bus board 50052 by soldering.

To manufacture this liquid crystal display device, first, C
On the liquid crystal display panel 16 composed of the OM side transparent substrate 502 and the SEG side transparent substrate 501, TCP50042 in which the liquid crystal driving semiconductor chip 4 is mounted in advance,
Connect using an anisotropic conductive adhesive or the like. Next, the UV-curable resin mold 21 is applied to all the transparent electrode exposed portions of the terminals of the SEG side transparent substrate 501 and cured. After that, the liquid crystal display panel was roughly aligned S
EG-side bus board 50043 and COM-side bus board 50
Put on 052, SEG side bus board 50043 and TC
P50042, COM side bus board 50052 and TCP5
After the alignment of 0042 is performed, soldering is performed, and later, the SEG side bus board 50043 and the COM side bus board 500.
52 is connected by soldering using the tape electric wire 511.

As described above, when the conventional liquid crystal display panel is used, after connecting the TCP on the SEG side, the CO
At the time of connecting the M-side TCP and at the time of applying / curing the ultraviolet curable resin, it was necessary to turn over the liquid crystal display panel at least twice, but by using the liquid crystal display panel of the present invention, It is not necessary to turn over, and the application process of the UV-curable resin can be done only once, so that the manufacturing process can be greatly simplified.

As described above, even when the liquid crystal drive circuit is mounted on the liquid crystal display panel by using the conventional TCP, the process is shortened and simplified by using the liquid crystal display panel having the structure of the present invention. Cost reduction is possible.

[0313]

As described above, by forming the input / output wiring of the semiconductor element, the bus line and the connection terminal on the multilayer substrate, mounting a plurality of semiconductor elements thereon and connecting them to the electrodes of the display element, driving is performed. Since the control circuit board is not required, the number of interconnections of semiconductor elements can be reduced and reliability is improved.

Further, it is possible to provide a liquid crystal display device in which the mounting range of the liquid crystal driving semiconductor chip is small, thin, compact, and inexpensive.

Also, one of the electrodes of the two transparent substrates constituting the liquid crystal display panel is connected to the electrode of the other transparent substrate, and a connection terminal for connecting the liquid crystal drive circuit is formed only on the transparent substrate. Since it has the configuration described above, it is possible to simplify the manufacturing process of the liquid crystal display device and facilitate automation of the manufacturing process, which has the effect of significantly reducing the manufacturing cost of the liquid crystal display device. .

Further, as a means for connecting one electrode of the two transparent substrates constituting the liquid crystal display panel to the electrode of the other transparent substrate, a liquid crystal sandwiched between the two transparent electrodes is sealed. Since the structure uses a conductive material that also serves as a sealant, the liquid crystal display device has a large image display area, a compact device, and an inexpensive liquid crystal display device.

Further, since the substrate for supplying power and signals is installed at the corner of the liquid crystal display panel where the X-side drive circuit and the Y-side drive circuit are in contact, the display quality of the liquid crystal display device is improved. It has the effect that it can be made better than before and the manufacturing cost can be reduced.

Further, since the multi-layer substrate on which the liquid crystal driving integrated circuit and the power supply circuit are mounted is used, the number of steps can be reduced.
Manufacturing costs can be significantly reduced. In addition, since a long wiring for connecting a power source and a signal is not required, invasion of noise from the outside is reduced, and a favorable display can be obtained.

[Brief description of drawings]

FIG. 1 is an exploded view of a multilayer substrate according to an embodiment of the present invention.

FIG. 2 is a diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a diagram showing a cross section of a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 5 is an exploded view of a multilayer substrate according to another embodiment of the present invention.

FIG. 6 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 7 is an exploded view of a multilayer substrate according to another embodiment of the present invention.

FIG. 8 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 9 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 10 is a diagram showing a cross section of a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 11 is an exploded view of a multilayer substrate according to another embodiment of the present invention.

FIG. 12 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 13 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 14 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 15 is an exploded view of a multilayer substrate according to another embodiment of the present invention.

FIG. 16 is a diagram showing a liquid crystal display device according to another embodiment of the present invention.

FIG. 17 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 18 is a view showing a cross section of a main part of a liquid crystal display device of another embodiment of the present invention.

FIG. 19 is an exploded view of a multilayer substrate according to another embodiment of the present invention.

FIG. 20 is a diagram showing a main part of a liquid crystal display device according to another embodiment of the present invention.

FIG. 21 is a diagram showing a cross section of an anisotropic conductive film according to an example of the present invention.

FIG. 22 is a view showing a cross section of an anisotropic conductive film of another example of the present invention.

FIG. 23 is a view showing a cross section of an anisotropic conductive adhesive according to an example of the present invention.

FIG. 24 is a view showing a cross section of a main portion of a connection portion of an anisotropic conductive film or an anisotropic conductive adhesive according to an example of the present invention.

FIG. 25 is a sectional view showing a mounting structure of a semiconductor device and a display device according to an embodiment of the present invention.

FIG. 26 is a plan view showing a semiconductor element mounting structure and a display element connected to each other according to an embodiment of the present invention.

FIG. 27 is a detailed wiring diagram of a connecting portion showing an embodiment of the present invention.

FIG. 28 is a connection block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 29 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 30 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 31 is a diagram showing an example of a semiconductor element mounting structure according to the present invention.

FIG. 32 is a diagram showing an example of an LCD module on which the semiconductor element of the present invention is mounted.

FIG. 33 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 34 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 35 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 36 is a diagram showing an example of an electronic printing apparatus mounted with the semiconductor element of the present invention.

FIG. 37 is a diagram showing an embodiment of an electronic printing apparatus mounted with the semiconductor element of the present invention.

FIG. 38 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 39 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 40 is a plan view of a liquid crystal display device of the present invention.

FIG. 41 is a diagram showing an example of a liquid crystal display device on which the semiconductor element of the present invention is mounted.

FIG. 42 is a diagram showing an example of a semiconductor element mounting structure of the present invention.

FIG. 43 is an exploded view of a multilayer substrate according to an example of the present invention.

FIG. 44 is a diagram showing a semiconductor device mounted on a multilayer substrate according to an example of the present invention.

FIG. 45 is a diagram showing a semiconductor element mounted on a multilayer substrate according to an example of the present invention.

FIG. 46 is a diagram showing a semiconductor element mounted on a multilayer substrate according to an example of the present invention.

FIG. 47 is a diagram showing a semiconductor device mounted on a multilayer substrate according to an example of the present invention.

FIG. 48 is a view showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 49 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 50 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 51 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 52 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 53 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 54 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 55 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 56 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 57 is a diagram showing a plurality of semiconductor devices mounted on a multilayer substrate according to an embodiment of the present invention.

FIG. 58 is a diagram in which a multilayer substrate according to an example of the present invention is mounted on an electro-optical device.

FIG. 59 is a diagram in which the multilayer substrate according to the embodiment of the present invention is mounted on an electronic printing device.

FIG. 60 is a diagram in which a multilayer substrate according to an embodiment of the present invention is mounted on an electro-optical device.

FIG. 61 is a diagram in which the multilayer substrate according to one embodiment of the present invention is mounted on an electronic printing device.

FIG. 62 is a view showing the multilayer substrate according to the embodiment of the present invention mounted on an electro-optical device.

FIG. 63 is a diagram in which a multilayer substrate according to an example of the present invention is mounted on an electronic printing device.

FIG. 64 is a diagram in which the multilayer substrate according to the embodiment of the present invention is mounted on an electro-optical device.

FIG. 65 is a diagram in which the multilayer substrate according to the embodiment of the present invention is mounted on an electronic printing device.

FIG. 66 is a diagram in which the multilayer substrate according to the embodiment of the present invention is mounted on an electro-optical device.

FIG. 67 is a diagram in which the multilayer substrate according to one embodiment of the present invention is mounted on an electronic printing device.

FIG. 68 is a view in which the multilayer substrate according to the embodiment of the present invention is mounted on an electro-optical device.

FIG. 69 is a diagram in which the multilayer substrate according to the embodiment of the present invention is mounted on an electronic printing device.

FIG. 70 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 71 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 72 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 73 is an exploded view of a multilayer substrate according to an example of the present invention.

FIG. 74 is a diagram showing a cross section of a main portion of a liquid crystal display device according to an embodiment of the present invention.

FIG. 75 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 76 is a diagram showing a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 77 is a diagram showing mounting holes of a multilayer substrate according to an example of the present invention.

FIG. 78 is a diagram showing a mounting hole of a multilayer substrate according to an example of the present invention.

FIG. 79 is a perspective view showing a mounting hole of another shape of the multilayer substrate according to the embodiment of the present invention.

FIG. 80 is a diagram showing a liquid crystal display device of an embodiment of the present invention.

FIG. 81 is a cross-sectional view showing an attached state of the multilayer substrate according to an example of the present invention.

FIG. 82 is a diagram showing a multilayer substrate according to an example of the present invention.

FIG. 83 is an exploded view of a multilayer substrate according to an example of the present invention.

FIG. 84 is a diagram showing a first layer of a multilayer substrate according to an example of the present invention.

FIG. 85 is a diagram showing a second layer of the multilayer substrate according to an example of the present invention.

FIG. 86 is a diagram showing a third layer of the multilayer substrate according to the example of the present invention.

FIG. 87 is a diagram showing a fourth layer of the multilayer substrate according to an example of the present invention.

FIG. 88 is a diagram showing a fifth layer of the multilayer substrate according to an example of the present invention.

FIG. 89 is a diagram showing a liquid crystal display device of an embodiment of the present invention.

FIG. 90 is a diagram showing an example of the present invention.

91 is a sectional view taken along the line AB of FIG. 90, showing an embodiment of the present invention.

FIG. 92 is a diagram showing an example of the present invention.

FIG. 93 is a diagram showing an example of the present invention.

FIG. 94 is an enlarged view of a B part in FIG. 93 showing an embodiment of the present invention.

FIG. 95 is a diagram showing an example of the present invention.

FIG. 96 is a diagram showing an example of the present invention.

FIG. 97 is a diagram showing an example of the present invention.

98 is an enlarged view of a C portion in FIG. 97 showing an embodiment of the present invention. FIG.

99 is an enlarged view of a portion D in FIG. 97 showing an embodiment of the present invention. FIG.

FIG. 100 is a diagram showing an example of the present invention.

101 is an enlarged view of the power circuit integrated multilayer substrate portion of FIG. 100 showing an embodiment of the present invention.

FIG. 102 is a view showing an embodiment of the present invention and is a cross-sectional view of a power supply circuit integrated substrate.

FIG. 103 is a diagram showing an example of the present invention.

FIG. 104 is a diagram showing an example of the present invention.

FIG. 105 is a diagram showing an example of the present invention.

FIG. 106 is a diagram showing a conventional liquid crystal display device.

FIG. 107 is a diagram showing a main part of a conventional liquid crystal display device.

FIG. 108 is a diagram showing a cross section of a main part of a conventional liquid crystal display device.

FIG. 109 is a diagram showing a cross section of a main part of another conventional liquid crystal display device.

FIG. 110 is a view showing a cross section of a conventional anisotropic conductive film.

FIG. 111 is a view showing a cross section of a main part of a connection portion of a conventional anisotropic conductive film.

FIG. 112 is a view showing a cross section of a main part of a connection portion of a conventional anisotropic conductive film.

FIG. 113 is a cross-sectional view of a conventional semiconductor element mounting structure and a display element connected thereto.

FIG. 114 is a plan view in which a conventional semiconductor element mounting structure and a display element are connected.

FIG. 115 is a plan view in which a conventional semiconductor element mounting structure and a display element are connected.

FIG. 116 is a view showing a conventional liquid crystal display panel.

FIG. 117 is a diagram showing a conventional liquid crystal display panel.
16 is a cross-sectional view taken along line EF of 16. FIG.

[Explanation of symbols]

1. First layer 2. Second layer 3. Third layer 4. 4 '. Liquid crystal driving semiconductor chip 5. 5 '. Input wiring 6. Through hole 7. Land 8. Output wiring 9. Through hole 10. Bus wiring 11. Through hole 12. Through hole 13. Connection terminal 14. Multilayer substrate 15. Wire 16. Panel 17. Connection board 18. Panel terminal 19. Connection member 20. Mold 21. Mold 22. Land for wire bonding 23. Wire 24. Connection board 25. Through hole 26. Through hole 27. Connection terminal 28. Bus wiring 29. Panel terminal 30. Through hole 31. Anisotropic conductive film 32. Conductive particles 33. Adhesive 34. Separator 35. Anisotropic conductive adhesive d. Particle size of conductive particles D. Particle diameter of conductive particles h. Adhesive thickness H. Thickness of adhesive k. Connection terminal thickness K. Thickness of terminal tip 110. Liquid crystal display element 111-1. ~ 111-12. Semiconductor element 112-1. ~ 112-4. Multilayer substrate 113. Liquid crystal display element electrode terminal 114. Multilayer substrate terminal 115. Anisotropic conductive adhesive P11. ~ P3n. Liquid crystal drive output line 1311. ~ 131n. Color pixel 201. Semiconductor device (LSI) 202. Multilayer substrate 203. Electronic element (liquid crystal display element) 204. Input wiring 205. Output wiring 206. Bump 208. Molding agent 209. ACF 210. Adhesive 211. LSI terminal 213. Electronic printing element (thermal printer head) 221. Internal conductive layer 231. LCD terminal 301. First layer 302. Second layer 303. Third layer 304. Semiconductor element 305. Input wiring 306. Through hole 307. Land 308. Output wiring 309. Bus wiring 310. External connection terminal 311. Multilayer substrate 312. Au wire 313. Liquid crystal panel 314. Connection board 315. Panel terminal 316. Anisotropic conductive film 317. Mold 318. Land for wire bonding 319. TCP 320. Opening 321. Bus board opening 322. Bus board 323. Tip 324. Output terminal through hole 325. Electrode 326. FPC for bus wiring 327. PCB board for bus wiring 328. Connection land for bus wiring 329. Electronic printing element 330. Mold 431. Multilayer substrate 431a. With mounting holes. Multilayer substrate 431b. With mounting holes. Multilayer substrate 431c. With mounting holes. Multilayer substrate 431d. With mounting holes. Multilayer substrate 432. with mounting holes. Mounting hole 433. On the outer decorative case 434. Screw 435. Backlight unit 436. Exterior cosmetic case 437. Multilayer substrate 437a. With mounting notches. Multilayer substrate 437b. With mounting notch Multilayer substrate 437c. With mounting notch. Multilayer substrate 437d. With mounting notch Multilayer substrate 438 having mounting notches. Notch for mounting 501. SEG side transparent substrate 502. COM side transparent substrate 503. SEG side electrode terminal 504. COM side electrode terminal 505. SEG side transparent electrode 506. COM side transparent electrode 507. Conductive material 508. Seal material 509. Liquid crystal 510. Conductive material that also serves as a sealing material 511. Tape electric wire 601. Connection wiring 602. Connection board 603. Connection board with input terminal Upper layer board 604. Connection board with input terminal Lower layer board 605. Connection wiring 606. Connection board input terminal 607. Connection board with input terminal 608. Power supply circuit integrated COM multi-layer substrate 609. Electronic component 610. Upper layer substrate 611. Intermediate substrate 612. Lower layer substrate 613-1. Circuit pattern 613-2. Corresponding to input pad of liquid crystal driving semiconductor chip Circuit pattern on the intermediate substrate 613-3. Circuit pattern on lower substrate 613-4. Circuit pattern of power supply circuit 613-5. Circuit pattern 614. corresponding to the output pad of the liquid crystal driving integrated circuit. Connection terminal 615-1. Through hole 615-2. Through hole 615-3. Through hole 615-4. Through hole 615-5. Through hole 1000. First layer 1010. Through hole 1100. Liquid crystal driving semiconductor chip 1110. Input wiring 1110-1. Input wiring 1110-N. Input wiring 1120. Through hole 1120-1. Through hole 1120-N. Through hole 1130. Output wiring 1130-1. Output wiring 1130-N. Output wiring 1140. Through hole 1140-1. Through hole 1140-N. Through hole 1200. Liquid crystal driving semiconductor chip 1210. Input wiring 1210-1. Input wiring 1210-N. Input wiring 1220. Through hole 1220-1. Through hole 1220-N. Through hole 1230. Output wiring 1230-1. Output wiring 1230-N. Output wiring 1240. Through hole 1240-1. Through hole 1240-N. Through hole 1300. Liquid crystal driving semiconductor chip 1310. Input wiring 1310-1. Input wiring 1310-N. Input wiring 1320. Through hole 1320-1. Through hole 1320-N. Through hole 1330. Output wiring 1330-1. Output wiring 1330-N. Output wiring 1340. Through hole 1340-1. Through hole 1340-N. Through hole 2000. Second layer 2010. Through hole 2020. Wiring 2030. Through hole 2120. Through hole 2140. Through hole 2220. Through hole 2240. Through hole 2320. Through hole 2340. Through hole 3000. Third layer 3010. Through hole 3020. Wiring 3030. Through hole 3120. Through hole 3140. Through hole 3240. Through hole 3340. Through hole 4000. Fourth layer 4020. Wiring 4040. Land 4140. Through hole 4240. Through hole 4340. Through hole 5000. Fifth layer 5050. Wiring 5060. Connection terminal 5140. Through hole 5240. Through hole 5340. Through hole 6000. Multilayer substrate 7000. Relay board 8000. Connection member 50041. Liquid crystal driving semiconductor chip 50042. TCP 50043. Bus board (SEG side) 50044. Input wiring 50045. Output wiring 50046. Tip 50047. Input wiring 50048. Bus wiring 50049. Anisotropic conductive film 50050. Conductive particles 50051. Adhesive 50052. Bus board (COM side) 50151. TCP 50152. Flexible wiring member 50153. TCP output terminal 50154. TCP input terminal 50155. Drive control circuit board

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[Procedure amendment]

[Submission date] May 22, 2002 (2002.5.2)
2)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Title of invention

[Correction method] Change

[Correction content]

Title: Liquid crystal display device and electro-optical device

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

[0019]

According to another aspect of the present invention, there is provided a liquid crystal display device comprising a first liquid crystal driving semiconductor chip, a second liquid crystal driving semiconductor chip, and the first liquid crystal driving semiconductor chip. The chip is mounted, and the power and the first image signal are supplied to the first liquid crystal driving semiconductor chip, and the power and the second image are supplied to the second liquid crystal driving semiconductor chip.
And a multi-layer substrate for supplying the image signal of.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

The liquid crystal display device of the present invention is a liquid crystal display device, wherein a pair of substrates, a first electrode provided on one of the substrates, a second electrode provided on the other substrate, and the other of the other substrates are provided. A first electrode terminal provided on the substrate and connected to the first electrode, and mounted on the other substrate,
A multilayer substrate connected to the first electrode terminal; a first liquid crystal driving semiconductor chip mounted on the multilayer substrate and driving the first electrode; and a second substrate mounted on the other substrate, the second substrate A second liquid crystal driving semiconductor chip for driving the electrodes of the second liquid crystal driving semiconductor chip, and the multi-layer substrate supplies power and a first image signal to the first liquid crystal driving semiconductor chip and also drives a second liquid crystal driving semiconductor chip. A power supply and a second image signal are supplied to the semiconductor chip.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

The electro-optical device according to the present invention is the electro-optical device, wherein the first driving semiconductor chip, the second driving semiconductor chip, and the first driving semiconductor chip are mounted, and the first driving semiconductor chip is mounted. A multi-layer substrate that supplies power and a first image signal to the driving semiconductor chip, and supplies a power and a second image signal to the second driving semiconductor chip.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

The electro-optical device according to the present invention is the electro-optical device, wherein a pair of substrates, a first electrode provided on one of the substrates, a second electrode provided on the other substrate, and the other of the two are provided. A first electrode terminal provided on the substrate and connected to the first electrode, and mounted on the other substrate,
A multi-layer substrate connected to the first electrode terminal, a first driving semiconductor chip mounted on the multi-layer substrate and driving the first electrode, and mounted on the other substrate, and the second substrate. A second driving semiconductor chip for driving the electrodes, and the multi-layer substrate supplies a power source and a first image signal to the first driving semiconductor chip and a power source for the second driving semiconductor chip. And supplying a second image signal.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Delete

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05K 1/14 H05K 1/14 C J 3/46 3/46 N Z (31) Priority claim number Hei 5-158611 (32) Priority date June 29, 1993 (June 29, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-158612 (32) Priority date June 29, 1993 (June 29, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-158613 (32) Priority date June 1993 29th (1993.29.29) (33) Priority claiming country Japan (JP) (31) Priority claiming number Japanese Patent Application No. 5-163645 (32) Priority date July 1, 1993 (1993.7. 1) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-163646 (32) Priority date July 1, 1993 (July 1, 1993) (33) Priority right Assertion Country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-163647 (32) Priority date July 1, 1993 (July 1, 1993) (33) Priority claim country Japan (JP) (31) ) Priority claim number Japanese Patent Application No. 5-163648 (32) Priority date July 1, 1993 (July 1, 1993) (33) Priority claim country Japan (JP) (31) Priority claim number Hei 5-182924 (32) Priority date July 23, 1993 (July 23, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-200865 (32) Priority date August 12, 1993 (August 12, 1993) (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 5-221389 (32) Priority date September 1993 6th (September 9, 1993) (33) Country claiming priority Japan (JP) (72) Inventor Shigetoshi Yamada 3-3-5 Yamato, Suwa City, Nagano Seiko Epson Corporation (72) Inventor Kenichi Maruyama 3-3-5 Yamato, Suwa City, Nagano Prefecture, Seiko Epson Corporation (72) Inventor Eiji Muramatsu Suwa, Nagano Prefecture 3-5 Yamato Seiko Epson Corporation (72) Inventor Souichi Maeda Suwa City, Nagano Prefecture 3-3-5 Yamato Seiko Epson Corporation (72) Inventor Seiichi Sakura 3 Yamato Yamato, Suwa City, Nagano Prefecture Inc. 3-5 Seiko-Epson Co., Ltd. (72) Inventor Kazuaki Furuichi 3-3-5 Yamato, Suwa, Nagano Prefecture Inc. 72 Seiko-Epson Co., Ltd. (72) Haruki Mochizuki 3-3 Yamato, Suwa, Nagano Prefecture No. 5 F-term in Seiko Epson Corporation (reference) 2H092 GA29 GA34 GA38 GA40 GA44 GA45 GA48 GA50 GA51 GA59 GA60 JA05 JA24 JB22 JB24 JB31 JB33 NA27 PA06 5C094 AA05 AA08 AA09 AA13 AA15 AA43 AA44 AA19 DBA53 DAA09 DBA53 DB05 EA02 EA05 EB02 FA01 FA02 GB01 5E344 AA02 BB01 CC03 CD02 CD04 5E346 AA31 AA42 BB02 BB11 BB16 CC04 CC09 CC10 CC17 CC32 CC38 CC39 DD13 DD16 DD17 DD32 DD33 DD34 FF04 EE43 EE04 EE04 KK05 KK09

Claims (44)

[Claims] 1. A liquid crystal display device having a plurality of liquid crystal driving semiconductor chips mounted, wherein the liquid crystal driving semiconductor chips are mounted on the surface of a multilayer substrate, and at least an input wiring pattern to the chip and an output wiring pattern from the chip are formed. At least one intermediate layer is provided between the front surface and the back surface of a certain multilayer substrate and between the front surface and the back surface, and the input wiring or the output wiring or a part of both wirings is provided as a wiring pattern in the intermediate layer. A multi-layer substrate in which each wiring is connected through a through hole is electrically connected to a panel terminal, and a plurality of the multi-layer substrates are electrically connected by a conductive connecting means. Liquid crystal display device. 2. A liquid crystal display device according to claim 1, wherein face down bonding or wire bonding is used as a means for mounting the liquid crystal driving semiconductor chip according to claim 1 on the surface of a multilayer substrate. 3. A liquid crystal display device according to claim 1, wherein an anisotropic conductive film is used for electrical connection between the output terminal and the panel terminal of the multilayer substrate according to claim 1. 4. A liquid crystal display device according to claim 1, wherein an anisotropic conductive adhesive is used for electrical connection between the output terminal and the panel terminal of the multilayer substrate according to claim 1. 5. A wire bonding, a heat seal connection, as a conduction means between the plurality of multilayer substrates according to claim 1.
The liquid crystal display device according to claim 1, wherein a flexible substrate connection is used. 6. A liquid crystal display device according to claim 1, wherein wirings on a panel are used as the conducting means between the plurality of multilayer substrates according to claim 1. 7. A liquid crystal display device according to claim 6, wherein the wiring on the panel according to claim 6 is disposed inside the panel terminal portion and the panel cell. 8. The wiring on the panel according to claim 6 and claim 1.
7. The liquid crystal display device according to claim 6, wherein the connection with the input wiring of the multilayer substrate described above and the connection of the output wiring with the panel terminal according to claim 1 are performed at once. 9. A liquid crystal display device according to claim 8, wherein the connection according to claim 8 is made with an anisotropic conductive film. 10. The liquid crystal display device according to claim 8, wherein the connection according to claim 8 is made with an anisotropic conductive adhesive. 11. A liquid crystal display device according to claim 1, wherein a plurality of liquid crystal driving semiconductor chips are mounted on the multilayer substrate according to claim 1. 12. The liquid crystal display device according to claim 9, wherein as the anisotropic conductive film according to claim 9, an anisotropic conductive film having an adhesive thickness smaller than a conductive particle diameter is used. 13. The liquid crystal display according to claim 10, wherein the anisotropic conductive adhesive according to claim 10 is an anisotropic conductive adhesive having a thickness smaller than that of conductive particles. apparatus. 14. A liquid crystal display device in which a row electrode group and a column electrode group are provided on a display substrate, and a display drive signal is supplied to the electrode group from a semiconductor element to display a color pixel, and a bus line and a connection terminal are formed. A liquid crystal display device characterized in that a semiconductor element is mounted on the multilayer substrate, and an output wiring of an independent semiconductor element for each color electrode is connected to an electrode terminal led out from a display substrate. 15. The liquid crystal display device according to claim 14, wherein the semiconductor element is mounted on the surface of the multilayer substrate. 16. The liquid crystal display device according to claim 14, wherein the semiconductor element is rod-shaped, and a semiconductor element having input / output terminals formed on long sides facing each other in parallel is mounted on a multilayer substrate. 17. A multi-layer substrate having a semiconductor device having at least one side provided with an output terminal and at least a side opposite to a main output terminal side provided with an input terminal, and having at least an output wiring pattern and an input wiring pattern. In a mounting structure in which the semiconductor element is mounted on a predetermined pattern, bumps are formed on terminals of the multilayer substrate on which the semiconductor element is mounted, and the semiconductor element is connected to another electronic element. Mounting structure. 18. A multi-layer substrate, comprising a semiconductor device having at least one side equipped with an output terminal and at least a side facing the main output terminal side provided with an input terminal, and equipped with at least an output wiring pattern and an input wiring pattern. In a mounting structure in which the semiconductor element is mounted on a predetermined pattern, bumps are formed on the terminals of the multilayer substrate on which the semiconductor element is mounted, and the semiconductor element is electrically connected to another electronic element. Method. 19. An electron optical device using the semiconductor element mounting structure according to claim 17. 20. An electronic printing apparatus comprising the semiconductor element mounting structure according to claim 17. 21. A multi-layer substrate having at least one output terminal and at least an output wiring pattern and an input wiring pattern, using a semiconductor element having at least a side opposite to a main output terminal side thereof and an input terminal. In a mounting structure in which the semiconductor element is mounted on a predetermined pattern, a terminal is formed on a side surface portion of the multilayer substrate on which the semiconductor element is mounted, and the terminal is used to make the multilayer substrate plane and the electronic element plane substantially vertical. A mounting structure for a semiconductor device, wherein the multilayer substrate is mounted on the electronic device so as to be positioned. 22. The semiconductor element mounting structure according to claim 21, wherein an anisotropic conductive film is used for connecting the multilayer substrate and the electronic element in the semiconductor element mounting structure according to claim 21. 23. An electron optical device using the semiconductor element mounting structure according to claim 21. 24. An electronic printing apparatus using the semiconductor element mounting structure according to claim 21. 25. A semiconductor element is mounted on a surface of a multi-layer substrate, and has a surface of the multi-layer substrate having an input wiring pattern to the semiconductor element and an output wiring pattern from the semiconductor element, and an output terminal connected to an external terminal. At least one intermediate layer is provided between the back surface and the front surface and the back surface, and the input wiring, the output wiring, or a part of both wirings is provided as a wiring pattern in the intermediate layer, and each wiring is through. A multi-layer substrate comprising a multi-layer substrate connected through a hole, wherein an opening for mounting the multi-layer substrate is provided in at least a first layer of the multi-layer substrate. 26. As means for mounting the semiconductor device according to claim 25 on the surface of a multilayer substrate, face down bonding is performed on the surface of the second layer through an opening provided in the first layer of the multilayer substrate. A method for mounting a semiconductor element, which is characterized by being mounted using. 27. As a means for mounting the semiconductor device according to claim 25 on the surface of a multilayer substrate, the semiconductor device positioned on the surface of the second layer through an opening provided in the first layer of the multilayer substrate. And a multi-layer substrate are mounted by wire bonding, which is a semiconductor element mounting method. 28. A semiconductor device characterized in that bus wiring for an input signal required when a plurality of the multi-layered substrates on which the semiconductor device according to claim 26 is mounted is used, is collectively performed by using an FPC. How to implement. 29. The semiconductor device according to claim 27, wherein bus wiring for input signals, which is required when a plurality of the multi-layered substrates on which the semiconductor device is mounted is used, are collectively formed by using an FPC. How to implement. 30. An FPC board having a plurality of openings is provided for bus wiring of an input signal, which is required when a plurality of the multi-layer boards on which the semiconductor element according to claim 26 is mounted is used. A characteristic semiconductor element mounting method. 31. A bus wiring line for an input signal, which is required when a plurality of the multi-layered boards on which the semiconductor element is mounted according to claim 27 is used, is formed by an FPC board having a plurality of openings. A characteristic semiconductor element mounting method. 32. A method for mounting a semiconductor element, wherein bus wiring for an input signal, which is required when a plurality of the multilayer boards on which the semiconductor element is mounted according to claim 26 is used, is formed by wire bonding. . 33. A method of mounting a semiconductor element, wherein bus wiring for an input signal, which is required when a plurality of the multi-layered boards on which the semiconductor element is mounted according to claim 27 is used, is formed by wire bonding. . 34. A method according to claim 28, 29, 30, 31, 32,
33. An electro-optical device using the method for mounting a semiconductor element according to any one of items 33. 35. A method according to claim 28, 29, 30, 31, 32,
33. An electronic printer using the method for mounting a semiconductor element according to any one of 33. 36. A liquid crystal display device according to claim 1, wherein a convex portion or a concave portion is provided on at least a part of sides forming the multilayer substrate. 37. A liquid crystal display device according to claim 1, wherein an arbitrary layer is smaller than other layers. 38. A liquid crystal display device comprising the multi-layer substrate according to claim 1 having mounting holes. 39. A liquid crystal display device comprising the multilayer substrate according to claim 1 provided with a notch for attachment. 40. In a liquid crystal display device having a plurality of liquid crystal driving semiconductor chips mounted therein, a connection terminal to an external circuit, a wiring pattern for forming a circuit, a connection terminal to a liquid crystal panel, a liquid crystal driving semiconductor chip and a power supply. The surfaces on which the electronic components that make up the circuit are mounted are placed above and below the multilayer substrate, and at least one intermediate layer is provided in addition to the wiring patterns connected to the wiring patterns on the upper and lower surfaces of the multilayer substrate. A liquid crystal display device comprising: a multi-layer substrate having a power supply circuit and a liquid crystal driving semiconductor chip electrically connected to a panel terminal. 41. A liquid crystal display panel comprising a liquid crystal sandwiched between two transparent substrates constituting the liquid crystal display device according to claim 1, wherein an electrode on one transparent substrate is formed on the other transparent substrate. A liquid crystal display device, wherein the liquid crystal display device is connected to the connection terminal pattern and the connection terminal to the liquid crystal drive circuit is formed only on the other transparent substrate. 42. Of two transparent substrates constituting a liquid crystal display device, an electrode on one transparent substrate is connected to the other transparent substrate, and a connection terminal for a liquid crystal drive circuit is provided only on the other transparent substrate. The formed liquid crystal display panel according to claim 41, wherein a seal for enclosing a liquid crystal sandwiched between two transparent substrates is used as a member for connecting an electrode on one transparent substrate to another transparent substrate. A liquid crystal display device using a conductive material that also serves as a material. 43. An X-side drive circuit and a Y-side drive circuit are connected to a corner portion where the X-side drive circuit and the Y-side drive circuit contact each other in the liquid crystal display panel in the liquid crystal display device according to claim 41 or 42. A liquid crystal display device, in which a substrate is installed. 44. A liquid crystal display device according to any one of claims 41 and 42, wherein the multi-layer substrate on which the power supply circuit and the liquid crystal drive circuit according to claim 40 are mounted is used.