JP2003022298A - Device and method for timing verification - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and properly perform the timing verification of data propagation between registers without requiring any manual labor. SOLUTION: This device is provided with: a clock edge time designating part 7a of a data transmission side and a clock edge time designing part 7b of a data reception side for designating the clock edge time of the data transmission side and reception side from clock data, circuit data, and timing verification conditions recorded in recording parts 1, 2 and 5; a timing verifying part 4 for performing timing verification from the circuit data, delay data, and clock edge time; and a verification result outputting part 6 for outputting a timing verification result. This device is further provided with a verification result minimum value detecting part 8 for calculating the time difference between the pre-and-post cycle time of a data reception side clock from the time for one cycle inputted from the clock edge time designating part 7b of the data reception side and the verification result inputted from the timing verification result outputting part 6 and generating at least three verification results to detect the minimum value of the absolute value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design verification technique, and more particularly to a timing verification method, and in particular, timing verification with respect to one or a plurality of cycles of a clock edge on the data receiving side with respect to a design verification target circuit. The present invention relates to a timing verification method in which the minimum absolute value among the results including is the verification result.

[0002]

2. Description of the Related Art A conventional method [block diagram (FIG. 11), flowchart (FIG. 12)] will be described with reference to a circuit diagram (FIG. 3) and a timing chart diagram (FIG. 4). 1
Cycle time (10ns) clock (CK1 / CK
When performing the Hold timing check at the time of data transfer from the data transmission register F1 operating in 2) to the data reception register F2, first, the clock relationship between data transmission and reception is determined. In this case, the same edge time is used. Check. That is, since the data transmission side clock source CK1 and the data reception side clock source CK2, which are the basis for timing check, are verified as the same time 0 ns, F1 operates and the data input pin F2 of F2.
Verification is performed between the time 12.5 ns at which / D is reached and the time 2.0 ns at which F2 operates, and as a result, there is a margin of 9.5 ns. However, when verification is performed by logic simulation or the like, time 1 at which the above F2 / D is reached is reached.
At 2.5 ns, the HOLD timing error occurs between 10.0 ns when F2 operates.

[0003]

As described above, there is a problem that an erroneous result is output unlike the result of the logic simulation. In the past, in order to avoid this problem, there was a problem that the user had to manually find it, and further, it was necessary to obtain and create the timing verification condition.

The present invention verifies the timing of data propagation between registers without the need for manual work.
It tries to be able to do it accurately and appropriately.

[0005]

According to a first aspect of the present invention, there is provided a timing verification device for verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or more predetermined clocks. The clock data recording means for recording the clock data, the circuit data recording means for recording the circuit data, the timing verification condition recording means for recording the timing verification conditions, and the data transmission side from the clock data, the circuit data and the timing verification conditions. Data sending side clock edge time designating means and data receiving side clock edge time designating means for designating clock edge time on the receiving side, and timing verification means for performing timing verification from circuit data, delay data and clock edge time, and timing verification Verification result output means for outputting the result The time difference between one cycle time before and after the data reception side clock is calculated from the time for one cycle input from the data reception side clock edge time designating means and the verification result input from the timing verification result output means, and at least 3 It has a verification result minimum value detecting means for generating one or more verification results and detecting the minimum absolute value.

In the timing verification device according to the second aspect of the invention, the timing of data propagation between two registers operating with two different clocks is verified, and a clock data recording means for recording clock data and a circuit. Circuit data recording means for recording data, timing verification condition recording means for recording timing verification conditions, and data transmission side clock for designating clock edge times of the data transmission side and the reception side from clock data, circuit data and timing verification conditions Edge time designation means and data reception side clock edge time designation means, timing verification means for performing timing verification from circuit data, delay data and clock edge time, verification result output means for outputting a timing verification result, and the data reception side Clock edge time designation The time difference between the time for one cycle input from the stage and the one cycle time before and after the data reception side clock is obtained from the verification result input from the timing verification result output means, and at least three or more verification results are generated. And a verification result minimum value detection means for detecting a minimum absolute value, and a clock edge time difference combination extraction means for extracting all combinations of edge time differences between two clocks.

In the timing verification apparatus according to the third aspect of the invention, the timing of data propagation between two registers, which are synchronous circuits synchronized with one or more predetermined clocks, is verified, and clock data is recorded. Clock data recording means, circuit data recording means for recording circuit data, timing verification condition recording means for recording timing verification conditions, and clock edges on the data transmission side and the reception side based on the clock data, circuit data, and timing verification conditions. Data sending side clock edge time designating means and data receiving side clock edge time designating means for designating time, timing verification means for performing timing verification from circuit data, delay data and clock edge time, and verification result for outputting timing verification result Output means and data reception A time difference between one cycle time input from the clock edge time designating means and one cycle time before and after the clock on the data receiving side is obtained from the verification result input from the timing verification result output means, and at least three or more verifications are performed. And a verification result minimum value detection means for generating a result and detecting the minimum absolute value, and using the above configuration again for about one cycle of the data transmission side clock edge during data propagation obtained by the above configuration. It has a logic propagation detecting means for performing timing verification and detecting whether there is duplicate reception or invalid reception with respect to the clock edge times of the three data receiving sides.

In the timing verification method according to the fourth aspect of the invention, when verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or more predetermined clocks, circuit data, delay data and timing Recording step of reading the verification conditions and clock data in the recording means, and setting step of the data transmission side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means And a data receiving side clock edge time setting step for setting a data receiving side clock edge time from the circuit data, the timing verification condition, and the clock data, and timing from the circuit data, the delay data and the clock edge time. Including a timing verification step of performing verification, and obtaining a time difference between one cycle time before and after the data reception side clock from the time of one cycle set by the data reception side clock edge time setting step and the verification result by the timing verification step. , And a verification result minimum value detection step of generating a plurality of verification results of at least three or more and detecting a minimum absolute value.

In the timing verification method according to the fifth aspect of the invention, circuit data, delay data, timing verification conditions and clock data are read and recorded when verifying the timing of data propagation between two registers operating with two different clocks. Recording step for recording in the recording means, data transmission side clock edge time setting step for setting the data transmission side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means, and the circuit data and timing verification Data reception side clock edge time setting step for setting the data reception side clock edge time from the condition and clock data, and timing detection for performing timing verification from the circuit data, delay data and clock edge time. Step, and the time difference between one cycle time before and after the data reception side clock is obtained from the time for one cycle set by the data reception side clock edge time setting step and the verification result by the timing verification step, and at least three or more And a verification result minimum value detection step of detecting a minimum absolute value, and a clock edge time difference combination extraction step of extracting all combinations of edge time differences between two clocks. .

In the timing verification method according to the sixth aspect of the present invention, circuit data, delay data and timing are verified when verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or more predetermined clocks. Recording step of reading the verification conditions and clock data in the recording means, and setting step of the data transmission side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means And a data receiving side clock edge time setting step for setting a data receiving side clock edge time from the circuit data, the timing verification condition, and the clock data, and timing from the circuit data, the delay data and the clock edge time. From the timing verification step of performing the verification, the time of one cycle set in the data receiving side clock edge time setting step and the verification result of the timing verification step, the time difference between the one cycle time before and after the data receiving side clock is obtained, and at least And a verification result minimum value detection step of generating a plurality of verification results of three or more and detecting the minimum value of the absolute value.
Before and after the cycle, the timing verification is performed again using the above method, and the logic propagation detection step is performed to detect whether there is duplicate reception or invalid reception with respect to the clock edge times of the three data reception sides.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the first embodiment. FIG. 2 is a flowchart showing the flow of processing in the first embodiment. FIG. 3 is a circuit diagram for explaining the processing in the first embodiment. FIG. 4 is a timing chart for explaining the processing in the first embodiment. In the first embodiment,
The invention corresponds to the first invention described in claim 1 and the fourth invention described in claim 4.

In the figure, 1 is a clock data recording unit for recording clock data, 2 is a circuit data recording unit for recording circuit data, 3 is a delay data recording unit for recording delay data of the circuit, Reference numeral 5 is a timing verification condition recording unit that records timing verification conditions, and 7a is data transmission from the clock data recording unit 1, circuit data recording unit 2, and timing verification condition recording unit 5 that specifies the clock edge time of the data transmission side clock. The side clock edge time designation unit 7b designates the clock edge time of the data reception side clock from the clock data recording unit 1, the circuit data recording unit 2, and the timing verification condition recording unit 5, and the data reception side clock edge time designation unit 4 A circuit data recording unit 2 and a delay data recording unit 3, and a data transmission side clock edge time designating unit 7a A timing verification unit for executing timing verification from the data reception side clock edge time designating unit 7b, 6 a verification result output unit for outputting the result of the timing verification unit 4, 8 a verification result output unit 6 and a data reception side clock edge time From the designation unit 7b to 1 of the data reception side clock
Input cycle time information, generate data before and after one or more cycle times of the data reception side clock time used in the timing verification result, detect the minimum absolute value of them, and verify the result It is a verification result minimum value detection unit as a result.

The operation of the timing verification method thus configured will be described with reference to the flowchart of FIG. First, the recording unit 1 stores the circuit data, the delay data, the clock data, and the timing verification conditions.
To 3 (step S1 and step S2).
Next, in the data sending side clock edge time designating section 7a and the data receiving side clock edge time designating section 7b, the clock data recorded in the clock data recording section 1, the data recorded in the circuit data recording section 2, and the timing verification The data recorded in the condition recording unit 5 is input and the respective times are determined (steps S3 and S4). Next, the timing verification unit 4 which has input the delay data, the circuit data and the clock edge information to the timing verification unit 4 performs timing verification (step S5), and outputs the result to the verification result output unit 6. At this time, the verification result outputs the same result as the conventional one. Next, the verification result minimum value detection unit 8
Then, the time for one cycle of the data reception clock is input from the data reception side clock edge time designation unit 7b, and 1
The cycle time edge time is added before and after the verification result input from the verification result output unit 6 to determine the minimum absolute value of the verification result (step S6).

As a result, the verification can be performed in the same time as the result of the logic simulation, and the same result can be obtained. Furthermore, in the past, it was no longer necessary to manually find and create conditions,
The timing verification period can be reduced.

According to the first embodiment of the present invention, the timing of data transmission between two registers, which are synchronous circuits synchronized with one or more predetermined clocks, is verified, and clock data is recorded. A clock data recording unit including the clock data recording unit 1,
Circuit data recording means composed of the circuit data recording section 2 recording the circuit data, timing verification recording means composed of the timing verification condition recording section 5 recording the timing verification conditions, and a clock recorded in the recording means. Transmission side clock edge time setting means comprising a data transmission side clock edge time designation section 7a and a data reception side clock edge time designation section 7b for designating clock edge times of the data transmission side and the reception side from data, circuit data and timing verification conditions. And a data receiving side clock edge time setting means, and timing verification from the circuit data and delay data recorded in the recording means and the clock edge time set by the transmitting side clock edge time setting means and the data receiving side clock edge time setting means. Timing detection The unit 4 and the verification result output unit including the verification result output unit 6 for outputting the timing verification result, and one cycle input from the data reception side clock edge time setting unit including the data reception side clock edge time designating unit 7b. Time and the verification result input from the timing verification result output means including the timing verification result output unit 6, the time difference between one cycle time before and after the clock on the data receiving side is obtained, and at least three or more verification results are generated. In addition, since the verification result minimum value detection means including the verification result minimum value detection unit 8 for detecting the minimum absolute value is provided, the timing verification of the data propagation between the registers can be performed without the need for manual work. It is possible to obtain a timing verification device that can perform accurately and appropriately.

Further, according to the first embodiment of the present invention, when verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or more predetermined clocks, circuit data and delay data And a recording step including step S1 and step S2 for reading the timing verification condition and the clock data in the recording means, and setting the data transmission side clock edge time from the circuit data and the timing verification condition and the clock data recorded in the recording means. Data transmitting side clock edge time setting step comprising step S3, and data receiving side clock edge time comprising step S4 for setting the data receiving side clock edge time from the circuit data, timing verification conditions and clock data Including a constant step and a timing verification step including step S5 for performing timing verification from circuit data, delay data and clock edge time, and the time for one cycle set by the data receiving side clock edge time setting step including step S4. And from the verification result by the timing verification step,
Since there is a verification result minimum value detection step including step S6 of obtaining a time difference from one cycle time before and after the clock on the data receiving side, generating at least three or more verification results, and detecting a minimum absolute value. As a result, it is possible to obtain a timing verification method capable of accurately and appropriately verifying the timing of data propagation between registers without the need for manual work.

Embodiment 2. A second embodiment of the present invention will be described with reference to FIGS. FIG. 5 shows the second embodiment.
3 is a block diagram showing the configuration of FIG. FIG. 6 is a flowchart showing the flow of processing in the second embodiment.
FIG. 7 is a circuit diagram for explaining the processing in the second embodiment. FIG. 8 is a timing chart for explaining the processing in the second embodiment. In the second embodiment, configurations and methods other than the specific configurations and methods described here have the same configurations and methods as those in the first embodiment described above, and have the same operation. It plays. In the drawings, the same or corresponding parts are designated by the same reference numerals. This Embodiment 2
The invention corresponds to the second invention described in claim 2 and the fifth invention described in claim 5.

In the figure, 1 is a clock data recording unit for recording clock data, 2 is a circuit data recording unit for recording circuit data, 3 is a delay data recording unit for recording delay data of the circuit, Reference numeral 5 is a timing verification condition recording unit that records timing verification conditions, and 7a is data transmission from the clock data recording unit 1, circuit data recording unit 2, and timing verification condition recording unit 5 that specifies the clock edge time of the data transmission side clock. The side clock edge time designation unit 7b designates the clock edge time of the data reception side clock from the clock data recording unit 1, the circuit data recording unit 2, and the timing verification condition recording unit 5, and the data reception side clock edge time designation unit 4 A circuit data recording unit 2 and a delay data recording unit 3, and a data transmission side clock edge time designating unit 7a A timing verification unit for executing timing verification from the data reception side clock edge time designating unit 7b, 6 a verification result output unit for outputting the result of the timing verification unit 4, 8 a verification result output unit 6 and a data reception side clock edge time From the designation unit 7b to 1 of the data reception side clock
Input cycle time information, generate data before and after one or more cycle times of the data reception side clock time used in the timing verification result, detect the minimum absolute value of them, and verify the result It is a verification result minimum value detection unit as a result. Reference numeral 9 is a clock edge time difference combination data extraction section for inputting detection completion information in the clock data, circuit data, timing verification conditions and verification result minimum value detection section 8 and extracting all combinations of clock edge time differences between the data transmission side and the reception side. Is.

Description will be made with reference to the flowchart of FIG. First, as in the first embodiment, circuit data, delay data, clock data, and timing verification conditions are read into the respective recording units 1 to 3 (steps S1 and S2). Then, all combinations of clock edge time differences between the data transmission side clock and the data reception side clock having different cycle times are obtained (step S8). Next, a certain combination of clock edge time differences is set (step S9), and the minimum verification result value is obtained by the same processing as in the first embodiment (steps S3 to S7). Next, it is checked whether or not all clock combinations have been performed (step S10), another one clock edge time difference combination is set (step S11), and the verification result minimum value is obtained again. At that time, the minimum verification result is compared with the minimum verification result detected in the previous process. The required timing verification result can be obtained by performing all combinations of clock edge time differences.

The second embodiment according to the present invention relates to a method of verifying the timing of data propagation between two registers operating with two different clocks in the configuration of the first embodiment, in addition to the configuration of the first embodiment. And a clock edge time difference combination extraction unit for extracting all combinations of edge time differences between the two clocks.

According to the second embodiment of the present invention, the timing of data propagation between two registers operating at two different clocks is verified, and the clock data recording unit 1 for recording clock data. A clock data recording unit, a circuit data recording unit 2 which records circuit data, and a timing verification recording unit which includes a timing verification condition recording unit 5 which records timing verification conditions, A data sending side clock edge time designating section 7a and a data receiving side clock edge time designating section 7b for designating clock edge times of the data sending side and the receiving side from the clock data, circuit data and timing verification conditions recorded in the recording means.
A transmitting side clock edge time setting means and a data receiving side clock edge time setting means, and circuit data and delay data recorded in the recording means, and a transmitting side clock edge time setting means and a data receiving side clock edge time setting means. Timing verification unit 4 that performs timing verification from the set clock edge time
And the timing and timing for one cycle input from the verification result output means including the verification result output section 6 for outputting the timing verification result and the data reception side clock edge time setting means including the data reception side clock edge time specifying section 7b. From the verification result input from the timing verification result output means including the verification result output unit 6, the time difference from the one cycle time before and after the clock on the data receiving side is obtained, and at least 3
And a verification result minimum value detecting means comprising a verification result minimum value detecting unit 8 for generating one or more verification results and detecting the minimum absolute value, and to detect all combinations of edge time differences between two clocks. Since the clock edge time difference combination extracting unit including the clock edge time difference combination data extracting unit 9 for extracting is provided, it is not necessary to manually verify the timing of data propagation between two registers operating with two different clocks. In addition, it is possible to obtain a timing verification device that can perform more accurately and appropriately.

Further, according to the second embodiment of the present invention, when verifying the timing of data propagation between two registers operating with two different clocks, circuit data and delay data, timing verification conditions and clock data are provided. A data transmission side clock comprising a recording step consisting of steps S1 and S2 for recording in the reading and recording means, and a step S3 for setting a data transmission side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means. An edge time setting step, and a data receiving side clock edge time setting step comprising a step S4 of setting a data receiving side clock edge time from circuit data and timing verification conditions and clock data recorded in the recording means. , Circuit data recorded in the recording means and the delay data and steps S3 and S4
According to the timing verification step consisting of step S5 for performing timing verification from the clock edge time set by, the time for one cycle set by the data receiving side clock edge time setting step consisting of step S4 and the timing verification step consisting of S5. From the verification result, the time difference from the one cycle time before and after the clock on the data receiving side is obtained, and at least three or more verification results are generated to detect the minimum absolute value. And extracting all combinations of edge time differences between the two clocks,
Since it has a clock edge time difference combination extraction step consisting of 3 to S7 and S8 to S11, the timing verification of data propagation between two registers operating with two different clocks can be performed more accurately and appropriately without the need for manual work. It is possible to obtain a timing verification method that can be performed.

Embodiment 3. The third embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG. 9 is a block diagram showing the configuration of the third embodiment. FIG. 10 is a flowchart showing the flow of processing in the third embodiment. In the third embodiment, the configurations and methods other than the specific configurations and methods described here have the same configurations and methods as those in the first and second embodiments described above. The same operation is achieved. In the figure, for the same or corresponding parts,
The same reference numerals are attached. The third embodiment includes a third invention described in claim 3 and a sixth invention described in claim 6.
It corresponds to the invention of.

In the figure, 1 is a clock data recording unit for recording clock data, 2 is a circuit data recording unit for recording circuit data, 3 is a delay data recording unit for recording delay data of the circuit, Reference numeral 5 is a timing verification condition recording unit that records timing verification conditions, and 7a is data transmission from the clock data recording unit 1, circuit data recording unit 2, and timing verification condition recording unit 5 that specifies the clock edge time of the data transmission side clock. The side clock edge time designation unit 7b designates the clock edge time of the data reception side clock from the clock data recording unit 1, the circuit data recording unit 2, and the timing verification condition recording unit 5, and the data reception side clock edge time designation unit 4 A circuit data recording unit 2 and a delay data recording unit 3, and a data transmission side clock edge time designating unit 7a A timing verification unit for executing timing verification from the data reception side clock edge time designating unit 7b, 6 a verification result output unit for outputting the result of the timing verification unit 4, 8 a verification result output unit 6 and a data reception side clock edge time From the designation unit 7b to 1 of the data reception side clock
Input cycle time information, generate data before and after one or more cycle times of the data reception side clock time used in the timing verification result, detect the minimum absolute value of them, and verify the result It is a verification result minimum value detection unit as a result. Reference numeral 9 is a clock edge time difference combination data extraction section for inputting detection completion information in the clock data, circuit data, timing verification conditions and verification result minimum value detection section 8 and extracting all combinations of clock edge time differences between the data transmission side and the reception side. Is. Reference numeral 10 denotes a logical propagation detecting section, which inputs the cycle time of each clock from the data transmitting side clock edge time designating section 7a and the data receiving side clock edge time designating section 7b, and the verification result minimum value detecting section 8 is inputted.
Input the clock time of the data sending side and the clock time of the data receiving side when the minimum value is detected, and add the next clock edge of the data sending side clock and the next edge of the data receiving side clock to the verification result minimum value information. Then, when the data receiving side receives two outgoing data at one edge (duplicate reception), and when no outgoing data is received (one outgoing data is received at a plurality of edges) ( Invalid reception) is detected.

Description will be made with reference to the flowchart of FIG. First, as in the first embodiment, steps S1 to S1.
The process of S6 is performed. Then, the minimum value of the verification result in step S6 for determining whether the absolute value of the verification result is the minimum value is received, the timing verification of the preceding and following one cycle and the extraction of the minimum value are performed in step S12.
Thus, the overlapped reception and the invalid reception are detected by extracting the edge overlap and the edge skip related to the data reception side clock edge time in step S13.

As described above, by adding the logical propagation detector 10, not only the timing verification but also the data transmission / reception check can be performed, so that the timing verification with higher accuracy can be performed.

Since the embodiment of the present invention is configured as described above, the accuracy of the timing verification is improved, the timing verification conditions created by the user can be reduced, and the data propagation can be further reduced. There is an effect that the logic such as duplicate reception and invalid reception of can be verified.

According to the third embodiment of the present invention, the timing of data propagation between two registers, which are synchronous circuits synchronized with one or more predetermined clocks, is verified, and clock data is recorded. A clock data recording unit including the clock data recording unit 1,
Circuit data recording means composed of the circuit data recording section 2 recording the circuit data, timing verification recording means composed of the timing verification condition recording section 5 recording the timing verification conditions, and a clock recorded in the recording means. Transmission side clock edge time setting means comprising a data transmission side clock edge time designation section 7a and a data reception side clock edge time designation section 7b for designating clock edge times of the data transmission side and the reception side from data, circuit data and timing verification conditions. And a data receiving side clock edge time setting means, and timing verification from the circuit data and delay data recorded in the recording means and the clock edge time set by the transmitting side clock edge time setting means and the data receiving side clock edge time setting means. Timing detection 1 cycle time input from the data receiving side clock edge time setting means including the unit 4 and the verification result output unit 6 outputting the timing verification result, and the data receiving side clock edge time designating unit 7b. And a time difference from the one cycle time before and after the clock on the data receiving side is obtained from the verification result input from the timing verification result output means including the timing verification result output unit 6, and at least three or more verification results are generated. And a verification result minimum value detecting means comprising a verification result minimum value detecting unit 8 for detecting the minimum absolute value, and the configuration is repeated about one cycle before and after the data transmission side clock edge at the time of data propagation obtained by the above configuration. The timing verification is performed by using the Since to have a logical propagation detecting means consisting of a logic propagation detecting unit 10 for detecting whether the reception is not, timing verification data propagation between registers, without the need for manual operations,
It is possible to obtain a timing verification device that can perform exactly and appropriately, and can also verify logic such as duplicate reception and invalid reception of data propagation.

Further, according to the first embodiment of the present invention, when verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or a plurality of predetermined clocks, circuit data and delay data And a recording step including step S1 and step S2 for reading the timing verification condition and the clock data in the recording means, and setting the data transmission side clock edge time from the circuit data and the timing verification condition and the clock data recorded in the recording means. Data transmitting side clock edge time setting step comprising step S3, and data receiving side clock edge time comprising step S4 for setting the data receiving side clock edge time from the circuit data, timing verification conditions and clock data Time and timing for one cycle set by the constant step, the timing verification step including step S5 for performing timing verification from the circuit data, the delay data, and the clock edge time, and the data receiving side clock edge time setting step including step S4. From the verification result of the verification step, the time difference from the one cycle time before and after the clock on the data receiving side is obtained, and at least three or more verification results are generated,
A verification result minimum value detection step consisting of step S6 of detecting the minimum absolute value, and timing verification using the above method again about one cycle before and after the data transmission side clock edge during data propagation obtained by the above method. And a logical propagation detection step consisting of steps S12 and S13 for detecting overlapping reception or invalid reception with respect to the three clock edges on the data reception side. Therefore, the timing of data propagation between registers can be manually verified. It is possible to obtain a timing verification method that can be accurately and appropriately performed without the need for work by, and can also verify logic such as duplicate reception and invalid reception of data propagation.

[0030]

According to the first aspect of the present invention, the timing of data transmission between two registers, which are synchronous circuits synchronized with one or more predetermined clocks, is verified, and clock data is recorded. Clock data recording means, circuit data recording means for recording circuit data, timing verification condition recording means for recording timing verification conditions, clock edge time of data transmission side and reception side from clock data, circuit data and timing verification conditions Data sending side clock edge time specifying means and data receiving side clock edge time specifying means, timing verification means for performing timing verification from circuit data, delay data and clock edge time, and verification result output for outputting timing verification results Means for clocking the data receiving side. From the verification result inputted from the time and the timing verification result output unit for one cycle for inputting di time specifying means, before and after the data receiving clock 1
Since there is a verification result minimum value detecting means for obtaining a time difference from the cycle time, generating a plurality of verification results of at least three or more, and detecting a minimum absolute value, it is possible to verify the timing of data propagation between registers. It is possible to obtain a timing verification device that can be accurately and appropriately performed without the need for manual work.

According to the second aspect of the invention, the timing of data propagation between two registers operating at two different clocks is verified, and clock data recording means for recording clock data and circuit data are recorded. Circuit data recording means, timing verification condition recording means for recording timing verification conditions, and data transmission side clock edge time specification for designating clock edge times of the data transmission side and the reception side from clock data, circuit data and timing verification conditions Means and data reception side clock edge time designating means, timing verification means for performing timing verification from circuit data, delay data and clock edge time, verification result output means for outputting a timing verification result, and data reception side clock edge time 1 input from designated means The time difference between the clock cycle time and the one-cycle time before and after the clock on the data receiving side is obtained from the verification result input from the timing verification result output means, and at least three or more verification results are generated to obtain the absolute value. A verification result minimum value detecting means for detecting the minimum value;
Since the clock edge time difference combination extraction means for extracting all combinations of edge time differences between two clocks is provided, timing verification of data propagation between two registers operating with two different clocks can be performed more efficiently without the need for manual work. It is possible to obtain a timing verification device that can perform accurately and appropriately.

According to the third aspect of the invention, the timing of data propagation between two registers which are synchronous circuits synchronized with one or a plurality of predetermined clocks is verified.
Clock data recording means for recording clock data,
Circuit data recording means for recording circuit data, timing verification condition recording means for recording timing verification conditions,
Data sending side clock edge time designating means and data receiving side clock edge time designating means for designating the clock edge time of the data sending side and the receiving side from the clock data, the circuit data and the timing verification condition, and the circuit data, the delay data and the clock edge Timing verification means for performing timing verification from time, verification result output means for outputting a timing verification result, time for one cycle input from the data receiving side clock edge time designating means and the timing verification result output means. And a verification result minimum value detecting means for detecting a minimum absolute value by obtaining a time difference from one cycle time before and after the clock on the data receiving side from the verification result, generating at least three or more verification results. , The data transmission side clock at the time of data propagation obtained by the above configuration Before and after one cycle of the clock edge, the timing verification is performed again using the above configuration, and it is detected whether there is duplicate reception or invalid reception with respect to the three clock edge times of the data reception side. It is possible to obtain a timing verification apparatus that can accurately and properly perform the timing verification of 1. without the need for manual work and can also verify the logic such as duplicate reception and invalid reception of data propagation.

According to the fourth aspect of the invention, in verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or a plurality of predetermined clocks, circuit data, delay data, timing verification conditions and A recording step of reading the clock data into a recording means, a step of setting a clock edge time of a data transmitting side from the circuit data and timing verification conditions recorded in the recording means, and a clock edge time of a data transmitting side from the clock data; Data receiving side clock edge time setting step for setting the data receiving side clock edge time from the circuit data and timing verification conditions and the clock data, and timing for performing timing verification from the circuit data, delay data and clock edge time And a verification step, which is set by the data receiving clock edge time setting step 1
The time difference between one cycle time before and after the clock on the data receiving side is obtained from the cycle time and the verification result of the timing verification step, and at least three or more verification results are generated to detect the minimum absolute value. Since the verification result minimum value detection step is included, it is possible to obtain a timing verification method that can accurately and appropriately verify the timing of data propagation between registers without the need for manual work.

According to the fifth aspect of the invention, in verifying the timing of data propagation between two registers operating with two different clocks, circuit data and delay data, timing verification conditions and clock data are read and recorded in the recording means. Recording step, a data transmission side clock edge time setting step for setting a data transmission side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means, and the circuit data and timing verification conditions and a clock. Data receiving clock edge time setting step for setting data receiving clock edge time from data, timing verification step for performing timing verification from circuit data, delay data and clock edge time, and data From the verification result by the time and timing verification step of one cycle set by the signal side clock edge time setting step obtains the time difference between before and after the cycle time of the data receiving clock, at least 3
A clock edge time difference combination extraction step of extracting all combinations of edge time differences between two clocks, including a verification result minimum value detection step of generating one or more plurality of verification results, and detecting a minimum absolute value. Therefore, it is possible to obtain a timing verification method capable of more accurately and appropriately verifying the timing of data propagation between two registers that operate with two different clocks, without the need for manual work.

According to the sixth aspect of the invention, in verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or a plurality of predetermined clocks, circuit data, delay data, timing verification conditions and A recording step of reading the clock data into a recording means, a step of setting a clock edge time of a data transmitting side from the circuit data and timing verification conditions recorded in the recording means, and a clock edge time of a data transmitting side from the clock data; Data receiving side clock edge time setting step for setting the data receiving side clock edge time from the circuit data and timing verification conditions and the clock data, and timing for performing timing verification from the circuit data, delay data and clock edge time From the verification step and the time of one cycle set by the data receiving side clock edge time setting step and the verification result of the timing verification step, the time difference between the one cycle time before and after the data receiving side clock is calculated, and at least three or more And a verification result minimum value detection step of generating a plurality of verification results and detecting a minimum absolute value, and before and after one cycle of a data transmission side clock edge during data propagation obtained by the method,
Since the timing verification is performed again using the above method, and the logic propagation detection step of detecting whether there is duplicate reception or invalid reception with respect to the clock edge times of the three data reception sides, the timing verification of the data propagation between the registers is performed. Therefore, it is possible to obtain a timing verification method that can be accurately and appropriately performed without the need for manual work, and that can also verify logic such as duplicate reception and invalid reception of data propagation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in a first embodiment according to the present invention.

FIG. 2 is a flowchart showing a flow of processing in the first embodiment according to the present invention.

FIG. 3 is a circuit diagram for explaining processing in the first embodiment according to the present invention.

FIG. 4 is a timing chart diagram for explaining a process in the first embodiment according to the present invention.

FIG. 5 is a block diagram showing a configuration in a second embodiment according to the present invention.

FIG. 6 is a flowchart showing the flow of processing in the second embodiment according to the present invention.

FIG. 7 is a circuit diagram for explaining processing in the second embodiment according to the present invention.

FIG. 8 is a timing chart for explaining the processing in the second embodiment according to the present invention.

FIG. 9 is a block diagram showing a timing verification device according to a third embodiment of the present invention.

FIG. 10 is a flowchart showing a processing flow of a timing verification method according to the third embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration in a conventional technique.

FIG. 12 is a flowchart showing a flow of processing in the conventional technique.

[Explanation of symbols]

1 clock data recording unit, 2 circuit data recording unit, 3
Delay data recording unit, 4 Timing verification unit, 5 Timing verification condition recording unit, 6 Verification result output unit, 7a Data transmission side clock edge time designation unit, 7b Data reception side clock edge time designation unit, 8 Verification result minimum value detection unit , 9 clock edge time difference combination data extraction unit,
10 Logic propagation detector.

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Claims (6)

[Claims] 1. A clock data recording means for recording clock data, which verifies the timing of data propagation between two registers which are synchronous circuits synchronized with one or more predetermined clocks, and circuit data. Circuit data recording means for recording the timing verification conditions, timing verification condition recording means for recording the timing verification conditions, and data transmission side clock edges for designating clock edge times of the data transmission side and the reception side from the clock data, the circuit data, and the timing verification conditions. The data receiving means comprises a time designating means and a data receiving side clock edge time designating means, a timing verifying means for performing timing verification from circuit data, delay data and clock edge time, and a verification result outputting means for outputting a timing verification result. Input from the side clock edge time specification means From the time required for one cycle and the verification result input from the timing verification result output means,
It is characterized by further comprising a verification result minimum value detecting means for obtaining a time difference from the one cycle time before and after the clock on the data receiving side, generating at least three or more verification results, and detecting the minimum absolute value. Timing verification device. 2. A clock data recording means for recording clock data, and a circuit data recording means for recording circuit data, for verifying timing of data propagation between two registers operating at two different clocks. ,
Timing verification condition recording means for recording the timing verification conditions, data transmission side clock edge time specification means for specifying the clock edge time of the data transmission side and the reception side from the clock data, the circuit data and the timing verification conditions, and the data reception side clock edge Time designation means, timing verification means for performing timing verification from circuit data, delay data and clock edge time, verification result output means for outputting a timing verification result, and one cycle input from the data receiving side clock edge time specification means Minutes, and the verification result input from the timing verification result output means, the time difference between the one cycle time before and after the data reception side clock is obtained, and at least three or more verification results are generated to obtain the minimum absolute value. Verification result to detect value Minimum value detection And a stage, timing verification apparatus characterized by having a clock edge time difference combination extracting means for extracting all combinations of edge time difference between the two clocks. 3. A clock data recording means for recording clock data for verifying a timing of data propagation between two registers which are synchronous circuits synchronized with one or more predetermined clocks, and circuit data. Circuit data recording means for recording the timing verification conditions, timing verification condition recording means for recording the timing verification conditions, and data transmission side clock edges for designating clock edge times of the data transmission side and the reception side from the clock data, the circuit data, and the timing verification conditions. Time designation means and data reception side clock edge time designation means, timing verification means for performing timing verification from circuit data, delay data and clock edge time, verification result output means for outputting timing verification results, and the data reception side clock Input from edge time specification means From the time for one cycle and the verification result input from the timing verification result output means, the time difference between the one cycle time before and after the clock on the data receiving side is obtained, and at least three or more verification results are generated,
And a verification result minimum value detection means for detecting the minimum value of the absolute value, and the timing verification is performed again by using the above-mentioned configuration for about one cycle of the data transmission side clock edge at the time of data propagation obtained by the above-mentioned configuration. 3. The timing verification apparatus according to claim 1, further comprising a logical propagation detection unit that detects whether there is duplicate reception or invalid reception with respect to three data reception side clock edge times. 4. The circuit data, the delay data, the timing verification condition, and the clock data are read and recorded when verifying the timing of data transmission between two registers which are synchronous circuits synchronized with one or a plurality of predetermined clocks. Recording step for recording the data, the circuit data and timing verification conditions recorded in the recording means, and the data transmission side clock edge time setting step for setting the data transmission side clock edge time from the clock data, the circuit data and timing verification conditions And a data reception side clock edge time setting step for setting the data reception side clock edge time from the clock data, and a timing verification step for performing timing verification from the circuit data, the delay data and the clock edge time. Only, the time difference between the one cycle time before and after the data receiving side clock is obtained from the time for one cycle set by the data receiving side clock edge time setting step and the verification result by the timing verification step,
A timing verification method comprising a verification result minimum value detection step of generating a plurality of verification results of at least three or more and detecting a minimum absolute value. 5. A recording step of reading and recording circuit data and delay data, timing verification conditions and clock data in a recording means in verifying the timing of data propagation between two registers operating with two different clocks. Data sending side clock edge time setting step for setting the data sending side clock edge time from the circuit data and timing verification conditions and clock data recorded in the recording means, and the data receiving side clock from the circuit data and timing verification conditions and clock data Data reception side clock edge time setting step for setting edge time, timing verification step for performing timing verification from circuit data, delay data and clock edge time, and data reception side clock edge From the time for one cycle set by the time setting step and the verification result by the timing verification step, a time difference between the one cycle time before and after the clock on the data reception side is obtained, and at least three or more verification results are generated, A verification result minimum value detection step of detecting a minimum absolute value, and a clock edge time difference combination extraction step of extracting all combinations of edge time differences between two clocks. 6. When verifying the timing of data transmission between two registers, which are synchronous circuits synchronized with one or more predetermined clocks, circuit data and delay data, timing verification conditions and clock data are read and recorded. Recording step for recording the data, the circuit data and timing verification conditions recorded in the recording means, and the data transmission side clock edge time setting step for setting the data transmission side clock edge time from the clock data, the circuit data and timing verification conditions And a data reception side clock edge time setting step for setting the data reception side clock edge time from the clock data, a timing verification step for performing timing verification from the circuit data, the delay data and the clock edge time, and a data The time difference between one cycle time before and after the data reception clock is calculated from the time for one cycle set by the data reception side clock edge time setting step and the verification result by the timing verification step, and at least three or more verifications are performed. A verification result minimum value detection step of generating a result and detecting a minimum absolute value,
About one cycle of the clock edge of the data transmission side at the time of data propagation obtained by the above method, timing verification is performed again using the above method, and there is no duplicate reception or invalid reception for the three clock edge times of the data reception side. A timing verification method comprising a logical propagation detection step of detecting a.