JPH09212541A - Timing verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute the timing verification of the circuit to which plural clocks in the relation of non-frequency-multiplication are inputted. SOLUTION: A minimum rising edge section calculation part 5 calculates a time section where the times of changing the clocks mutually in the relation of non-frequency-multiplication from one level to the other level are the closest within the range of being unmatched with each other as a minimum zone 6. A static timing verification part 8 executes the verification of timing between a clock inputted to a data receiving side element and a data signal by supposing that the changing times of a pair of clocks in the relation of non-frequency- multiplication which are respectively inputted to a data transferring side element and the data receiving side element are in the relation of the minimum section. Namely, the timing verification of the circuit to which a clock in the relation of non-frequency-multiplication is executed without improving the high speed operation of static timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing verification device, and more particularly, to an improvement for enabling timing verification of a target circuit to which a plurality of clocks that are not in a frequency-doubled relationship are input.

[0002]

2. Description of the Related Art Conventionally, a static timing verification method has been known as an effective method for verifying the timing of a large scale circuit represented by an LSI (Large Scale Integrated Circuit).
The static timing verification method is a verification method using a path analysis method for a synchronous circuit, and has an advantage that it can be comprehensively processed at high speed without using a verification pattern.

FIG. 25 is a block diagram showing a conventional timing verification device for performing static timing verification. The conventional device 150 is provided with a static timing verification unit 120 as the most main device unit. Then, the static timing verification unit 120 stores data describing the circuit connection information 7, which is information regarding the configuration of the target circuit, that is, the circuit that is the target of the timing verification, and the timing of external input data input to the target circuit. Input timing information 9 is input. Further, when the back annotation verification is performed, the wiring delay information 23 having the information about the wiring capacitance and the wiring resistance is input.

Further, the static timing verification section 120 is constructed so as to be able to verify a target circuit operating with a plurality of clocks. Information regarding the timing of all clocks input to the verification circuit, that is, clock information 12
1 is prepared. Then, the static timing verification unit 120
Then, as the verification operation progresses, the clock information 12
Necessary clock information out of 1 is used appropriately.

The static timing verification unit 120 executes static timing verification of the target circuit based on these pieces of information.

[0006]

However, although the conventional device 150 can verify a circuit that operates with a plurality of clocks, these plurality of clocks need to have a frequency-doubling relationship with each other. was there. That is, as illustrated in the timing chart of FIG. 26, there is a problem that the period between the transfer-side clock T21 and the reception-side clock T22 belonging to each set needs to be a natural multiple. It was

The present invention has been made in order to solve the above-mentioned problems in the conventional device, and is an object to which a plurality of clocks which are not in a frequency-division relationship with each other are input while making the most of the advantage of the static timing verification. It is an object of the present invention to provide a timing verification device capable of performing timing verification on a circuit.

[0008]

According to a first aspect of the present invention, there is provided a timing verification device for verifying the timing of a target circuit including a plurality of elements operating in synchronization with a plurality of clocks, wherein the plurality of clocks are specified. Based on the clock information, with respect to the clocks that are in a non-double frequency relationship among the plurality of clocks, the time intervals at which the levels change from one level to the other level are closest to each other in a range where they do not match each other, that is, the minimum interval. A minimum interval calculating means for calculating, a pair of clocks having a non-double frequency relationship are respectively input, and a pair of the plurality of elements having a relationship of a data transfer side element and a data reception side element, and those And a circuit portion including a data signal path between the two, the circuit connection information defining the target circuit is referred to, and the pair of clocks is used. A timing evaluation unit that executes timing verification between a clock input to the data receiving side element and the data signal on condition that the change time is in the relationship of the minimum interval. To do.

The apparatus of the second invention is a timing verification apparatus for verifying the timing of a target circuit including a plurality of elements operating in synchronization with a plurality of clocks, based on clock information defining the plurality of clocks. Among the plurality of clocks, the time at which one level changes to the other level with respect to the clocks that are in a non-doubled relationship with each other,
Based on the minimum interval calculation means for calculating the closest time interval, that is, the minimum interval, in a range that does not coincide with each other, and the circuit connection information defining the target circuit, one by one is selected from the plurality of elements as a target element in sequence. Among the plurality of elements, the target element search means and the target element selected by the target element search means are data receiving side elements, and the corresponding data transfer side element is based on the circuit connection information. Whether the relation between the pair of clocks respectively input to the data transfer side element and the data reception side element based on the clock information and the path search means that is searched from A clock determination means for performing determination, the data transfer side element,
For the circuit portion including the data receiving side element, and the path of the data signal between them, while referring to the circuit connection information, when the result of the determination is a frequency double, refer to the clock information, When the result of the determination is a non-double frequency, the clock input to the data receiving side element and the data signal are provided on condition that the change times of the pair of clocks have the relationship of the minimum interval. Timing evaluation means for performing timing verification between the two.

A third aspect of the invention is the timing verification apparatus of the second aspect, wherein the timing evaluation means further includes the target element and the target element when the path search means cannot find the element on the data transfer side. The circuit connection information is referred to for a circuit portion including the path of the external input data signal input to the target element, and based on the data input timing information defining the external input data signal and the clock information. And verifying the timing between the clock input to the target element and the external input data signal.

According to a fourth aspect of the invention, in the timing verification apparatus according to any of the first to third aspects of the invention, wiring delay information defining a signal delay time of the wiring of the target circuit,
Clock delay calculation means for individually calculating delay times of a plurality of clock wirings for transmitting a clock to the plurality of elements based on the circuit connection information; and a clock input to the element for each of the plurality of elements. With respect to the clock information, the clock delay adding means for creating the clock information with delay by adding the delay time to the timing defined by the clock information, the minimum interval calculating means is provided with the delay information instead of the clock information. The minimum interval is calculated by referring to the attached clock information.

An apparatus according to a fifth aspect of the present invention is the timing verification apparatus according to the fourth aspect, further comprising back annotation means for extracting the circuit connection information and the wiring delay time from layout information defining a layout of the target circuit. ,
It is further characterized by being provided.

According to a sixth aspect of the invention, in the timing verification apparatus according to any one of the first to third aspects, the minimum section calculating means sets the calculated minimum section to data specified by data transfer cycle information. The transfer cycle is added, and the timing evaluation means refers to the value obtained by adding the data transfer cycle as the minimum section.

A seventh aspect of the invention is the timing verification apparatus according to any one of the first to sixth aspects of the invention, wherein the minimum interval calculating means has a cycle of both non-multiplied clocks. It is characterized in that the minimum section is searched in a period corresponding to the least common multiple.

According to an eighth aspect of the present invention, in the timing verification apparatus according to any one of the first to seventh aspects, the minimum interval calculating means is a clock that is in a non-double frequency relationship among the plurality of clocks. For all combinations of
It is characterized in that the minimum section is calculated.

According to a ninth aspect of the present invention, in a timing verification device for verifying the timing of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks, based on circuit connection information defining the target circuit, The target circuit is divided by a first type block that operates in synchronization with a single clock and a second type block that operates in synchronization with two different clocks, and the first circuit is divided from the circuit connection information by the first type block.
Block dividing means for extracting type 1 block connection information regarding the seed block and type 2 block connection information regarding the type 2 block, and static for performing static timing verification on the type 1 block. Timing verification means, test pattern generation means for generating an input test pattern for performing dynamic timing verification on the second type block, the input test pattern, and the second
Dynamic timing verification is performed on the second type block based on the seed block connection information, and another second type block is connected to the output side of the second type block subjected to the dynamic timing verification. In this case, the type 1 block is connected to the output side of the type 2 block which is the target of the dynamic timing verification, and the dynamic timing verification means which supplies the result of this dynamic timing verification to the test pattern generator. At this time, the data input timing information that defines the timing of the data signal input to the first type block is extracted from the result of the dynamic timing verification, and is supplied to the static timing verification means. Extraction means, and the static timing verification unit defines the first type block connection information and the plurality of clocks. With reference to the clock information, the data input timing information defining the external input data signal input from the outside of the target circuit, and the data input timing information supplied from the data input timing extraction means, Further, by selectively referring to the static timing verification, the test pattern generation means refers to the clock information, and outputs the static timing verification result and the dynamic timing verification result. The input test pattern is generated by further selectively referring to any of the above.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. First Preferred Embodiment> First, a timing verification device according to a first preferred embodiment will be described.

<1-1. Configuration and Operation of Entire Device> FIG. 1 is a block diagram showing the configuration of the timing verification device 101 of this embodiment. In FIG. 1, reference numeral 1 is information regarding the rising timing, cycle, etc. of the clock on the data transfer side used in a block in which data is transferred by clocks having different cycles among the clocks input to the target circuit,
That is, the data transfer side clock information, and 2 is the data reception side clock information used in the same block as the data transfer side clock information 1. These clock information 1 and 2 are given from the outside.

Reference numeral 3 is a synchronization time calculation unit for calculating the time (synchronization time) at which the clock information on the data transfer side and the clock information on the data reception side simultaneously rise, and 4 is numerical information calculated by the synchronization time calculation unit 3. The synchronization time, 5 is a rising edge minimum section calculation unit that calculates the rising edge minimum section based on the data transfer side clock information, the data reception side clock information, and the synchronization time, and 6 is the rising edge minimum section calculation unit 5. It is a rising edge minimum section that is calculated numerical information.

Further, 7 is circuit connection information which is information provided from the outside regarding the configuration of the target circuit, and 9 is data input timing information. Circuit connection information 7 is
It is information corresponding to the circuit diagram of the target circuit, that is, information on the types of elements that form the target circuit and the connection of these elements, and is provided from the outside. The data input timing information 9 is information regarding the time when the external input data input to the target circuit changes, and is described so that the relative relationship with the rising time of the clock becomes clear. This data input timing information 9 is also given from the outside.

Finally, reference numeral 8 is a static timing verification unit for executing static timing verification based on the clock information 1 and 2, the rising edge minimum section 6, the circuit connection information 7, and the data input timing information 9.

FIG. 2 is a circuit diagram showing an example of a target circuit to be verified by the device 101. The target circuit Y1 has three clocks T1 to T3 and 2 having different cycles.
Pieces of external input data Data1 and Data2 are input from the outside through input terminals (shown by white triangles in the figure). Then, the target circuit Y1 is configured to execute a predetermined logical operation based on these signals and output the output signal Out to the outside through an output terminal (shown by a white triangle in the drawing).

Of the clocks T1 to T3, the clock T
1 and T3 have a frequency-doubled relationship with each other, and the clock T2 has a non-frequency-doubled relationship with other clocks T1 and T3. That is, the target circuit Y1 is input with a plurality of clocks including clocks that are in a non-doubled relationship with each other.

Six elements U1 to U included in the target circuit Y1
Reference numeral 6 holds the data signal input to the data input terminal D until the next rising edge of the clock in synchronization with the rising edge of the clock input to the clock terminal T, that is, the transition from the normal level to the active level. Is a flip-flop that continues to output to the output terminal Q. The elements S1 to S3 are arbitrary elements or a combination of elements that delay the propagation of signals. The element S4 is a NAND element.

The operation of the device 101 will be described below by taking the target circuit Y1 as an example. The device 101 operates according to the flowchart of FIG. That is, when the device 101 starts operating, first in step S11, the clock information 1 on the data transfer side is sent to the synchronization time calculation unit 3.
And the clock information 2 on the data receiving side is added. Such clock information 1 and 2 is added manually from the outside or using an external input device.

FIG. 4 illustrates the contents of the clock information 1 and 2 for the target circuit Y1. The clock information 1 and 2 are obtained by distributing the clocks T1 to T3 of the target circuit Y1 to the transfer side and the receiving side. The distribution is preferably performed for all possible combinations, regardless of the circuit configuration of the target circuit Y1. In this case,
As shown in FIG. 4, the clock information 1 and 2 are prepared corresponding to 6 combinations N = 1 to 6.

Next, the processing shifts to step S12, and the synchronization time calculation unit 3 calculates the synchronization time based on the clock information 1 and 2. This calculation is performed for a combination in which the clock on the data transfer side and the clock on the data reception side have a non-double frequency relationship. That is, the set of numerical values executed and calculated for each of the combinations N = 1, 3, 4, 6 shown in FIG. 4 is sent to the rising edge minimum section calculation unit 5 as the synchronization time 4.

The synchronization time Syn1 is the clock information 1 and 2.
Is calculated as the least common multiple of the cycles Cyc1 and Cyc2 of the set of clocks belonging to. That is, the synchronization time Syn
1 is Equation (1): {Syn1 = cycles Cyc1, Cyc
The least common multiple of 2}. For example, the combination N =
For 1, the synchronization time Syn1 is given as the least common multiple of the cycle Cyc1 of the clock T1 and the cycle Cyc2 of the clock T2.

Next, the process proceeds to step S13, and the rising edge minimum section calculating unit 5 calculates the rising edge minimum section based on the clock information 1 and 2 and the synchronization time 4. This calculation also
This is performed for each of the combinations N = 1, 3, 4, 6 in FIG. The calculation procedure will be described below for an example of the combination of clocks T1 and T2 (N = 1).

First, the synchronization time Syn2 next to the synchronization time Syn1 is calculated by the following equation (2): {Syn2 = Syn1 × 2}.
Calculate according to. Subsequently, the clock rising time T1rise_time of the data transfer side is expressed by the mathematical expression (3): {T
1 rise_time = Cyc1 × m}. Similarly,
Data receiving clock rising time T2rise_time
Is defined by Expression (4): {T2rise_time = Cyc2 × n}. Here, the variables m and n are both natural numbers.

Next, the mathematical expression (5): {T1rise_time
<T2rise_time}, Expression (6): {Syn1 ≦ T1ris
e_time <Syn2} and Expression (7): {Syn1
T2rise_time and T1rise_ti within a range that satisfies all three conditions given by <T2rise_time ≦ Syn2}.
The minimum value in the difference of me is the rising edge minimum section T
Calculated as rise. That is, for the rising edge minimum section Trise, the minimum value for all natural numbers m and n satisfying Equations (5) to (7) is calculated by Equation (8): {Trise.
= MIN (T2rise_time-T1rise_time)}.

As a result, as illustrated in the timing chart of FIG. 5, the rising edge minimum section Trise is given as the minimum value of the time interval from the rising time of the clock T1 to the subsequent rising time of the clock T2. In other words, the minimum rising edge section T
The rise is given as the closest time interval between the clocks T1 and T2 in the range where the rising times do not coincide with each other. Therefore, the most severe condition is extracted for the receiving-side element to which the clock T2 is input to operate normally.

<1-2. Configuration and Operation of Static Timing Verification Unit 8> Next, the process proceeds to step S14. At this stage, the static timing verification unit 8 executes the static timing verification. FIG. 6 shows the static timing verification unit 8
FIG. 2 is a block diagram showing an internal configuration of the device. Further, FIG. 7 is a flowchart showing a processing procedure in the static timing verification unit 8. The internal configuration and operation of the static timing verification section 8 will be described below with reference to FIGS. 6 and 7.

When the process of step S14 is started, first, in step S141, a target element to be verified at present in the target circuit Y1 is searched. This process is performed by the target element search unit 81. That is, the target element search unit 81 searches the target circuit Y1 for an element to be verified for the time being, based on the circuit connection information 7.

Next, the process proceeds to step S142, and the path search is executed. That is, the clock input to the target element, the element on the receiving side and the clock thereof are searched. This processing is executed by the path search unit 82 based on the information regarding the target element selected by the target element search unit 81 and the circuit connection information 7.

If the element U2 is selected as the target element, the clock T2 input to the element U2 is first searched for by the path search. Subsequently, by tracing the signal input to the element U2, the elements S1 and U
1. Further, the clock T1 input to the element U1 is searched for. The clock T1 is recognized as the data transfer side clock, and the clock T2 is recognized as the data reception side clock. As a result, in the subsequent processing, only the circuit block X1 including the elements U1 and U2 and the element S1 interposed therebetween is to be handled in the target circuit Y1 of FIG.

Next, the processing shifts to step S143. Here, the clock determination unit 83 makes a first determination regarding the clock. That is, the input data to the selected target element is the external input data Data1,
It is determined whether it is 2. If the determination result is “Yes”, the process proceeds to step S145, and “No”.
If so, the process proceeds to step S144.

In step S144, the clock determination unit 83 continues to make a second determination. That is, it is determined whether or not the relationship between the data transfer side clock and the data reception side clock is a double frequency relationship. This determination is made based on the clock information 1 and 2.
Then, if the determination result is "Yes", the process proceeds to step S136, and if "No", the process proceeds to step S147.

In the example in which the target element is the element U2, since the input data is neither the external input data Data1 nor Data2, the process proceeds from step S143 to step S14.
Go to 4. Then, as shown in FIG.
Since 1 and T2 have a non-doubled relationship with each other,
The process further moves to step S147.

When the target element is, for example, the element U3, the input data is the external input data Data1.
The process proceeds from step S143 to step S145.

If the target element is U6, for example, the clock T1 becomes the data transfer side clock and the clock T3 becomes the data reception side clock. Then, since the input data is neither external input data Data1 nor Data2, the process proceeds from step S143 to step S143.
Move on to 144. Furthermore, as shown in FIG. 4, the clocks T1 and T3 have a frequency-doubling relationship, and therefore the process proceeds from step S144 to step S146.

The processing of steps S145 to S147 is executed by the timing evaluation section 84. Among them, the processes of steps S145 and S146 are performed by the conventional device 1
This is a well-known process that is also performed by the static timing verification unit 120 of 50.

In step S145, for example, the target element U
3, the timing between the clock T1 supplied by either the clock information 1 or 2 and the external input data Data1 supplied by the data input timing information 9 is the normal operation of the element U3 defined by the circuit connection information 7. required for,
It is determined whether or not conditions such as setup time and hold time are satisfied. In addition, external input data Dat
If there is an element in the path of a1, the circuit connection information 7
By referring to, the delay time due to this element is considered.

In step S146, for example, regarding the target device U6, the clocks T1 and T2 supplied by the clock information 1 and 2 are set up for the normal operation of the device U6 defined by the circuit connection information 7. It is determined whether or not the conditions such as the hold time are satisfied.
At this time, the determination is performed based on the circuit connection information 7 in consideration of the signal delay time due to the element S3 interposed between the element U5 and the element U6.

In step S147, the clock information 1,
In addition to 2 and the circuit connection information 7, the rising edge minimum section 6 is further referred to. Then, for example, when the target element is the element U2, as shown in the timing chart of FIG. 8, after the clock T1 rises,
Timing verification is performed under the most severe condition that the clock T2 rises at the time when the rising edge minimum section Trise has passed.

That is, the element U is based on the rising timing of the clock T1 supplied by the data transfer side clock information 1 and the function of the element U1 supplied by the circuit connection information 7.
The time when the output data appears at the output terminal Q of 1 is calculated. Further, based on the function of the element S1 supplied by the circuit connection information 7, the time when the input data arrives at the data input terminal D of the element U2 is calculated in consideration of the signal delay time due to the element S1.

Then, it is determined whether or not the clock T2 rising after the rising edge minimum section Trise from the rising timing of the clock T1 and the input data reaching the element U2 satisfy, for example, the conditions regarding the setup time Setup and the hold time Hold. To be done. For example, when the input data arrives at the element U2, the setup time Setup
If the preceding timing is reached and the timing at which the input data to the element U2 changes next is later than the rising timing of the clock T2 by the hold time Hold or more, it is determined that there is no timing error.

On the contrary, when any one of these conditions is not satisfied, it is determined that there is a timing error. As described above, the rising edge minimum section 6 is used to perform the timing verification for the most severe conditions. Moreover, the verification is performed in consideration of the signal delay time due to the element S1.

In steps S145-S147,
Since the timing evaluation unit 84 compares the timings of the signals to be verified, it is possible to easily obtain not only the presence or absence of the timing error but also a quantitative evaluation of, for example, the size of the margin and the degree of the error.

When any one of steps S145 to S147 is completed, the process proceeds to step S148. In step S148, it is determined whether or not an unverified target element remains in the target circuit Y1. If so, the process returns to step S141,
A new target element is searched. If not, the process of step S14 ends, and the device 10
The entire process of 1 ends (FIG. 3).

In this way, steps S141 to S148
By repeating the above cycle, the timing verification is sequentially performed on all of the elements U1 to U6 that require the timing verification in the target circuit Y1. In the cycle in which the elements U4, U5, and U1 which are not given as examples above are the target elements, the following processing is performed.

In the cycle in which the element U4 is the target element,
As shown in FIG. 4, the clock T1 is treated as a data transfer side clock and the clock T2 is treated as a data reception side clock. Therefore, step S147 is executed. In the cycle in which the element U5 is the target element, the element U3 is
Similarly to the cycle in which the target element is
Is executed and the clock T1 is compared with the external input data Data2.

Further, when the element U1 is the target element, as shown in FIG. 4, a cycle in which the clock T2 is used as the data transfer side clock and the clock T1 is used as the data reception side clock, and the clock T3 is used as the data transfer side clock. ,
Both a cycle in which the clock T1 is used as a data reception side clock and two cycles are executed. The former uses the element U4 as the transfer side element, and the latter uses the element U4.
6 is a transfer side element. In the former case, step S147 is executed, and in the latter case, step S146 is executed.

As described above, since a plurality of clocks having a non-double frequency relationship are input, the conventional device 150
Even for a target circuit that could not be verified by
By using 1, it is possible to perform efficient verification based on the static timing method.

As shown in FIG. 4, step S11
In the above, a preferable example in which the clock information 1 and 2 are prepared for all six combinations N = 1 to 6 has been shown. However, in consideration of the configuration of the target circuit Y1, for example, N = 1 to
Clock information 1 and 2 only for combinations of 3 and 5
It is also possible to prepare.

Further, in the step S11, the example in which the clock information 1 and 2 is directly input to the synchronization time calculation unit 3 from the outside has been described. However, a storage medium is provided in the device 101, and this storage medium is previously stored. The clock information 1 and 2 may be stored. In this case, step S11
Then, the process of reading the clock information 1 and 2 from the storage medium to the synchronization time calculation unit 3 is performed.

Further, the circuit connection information 7, the data input timing information 9 and the like are also temporarily stored in the storage medium, and can be read out from the storage medium as needed in accordance with the operation of the static timing verification section 8. , Device 10
1 may be configured.

<2. Second Preferred Embodiment> FIG. 9 is a block diagram showing a configuration of a timing verification device 102 according to a second preferred embodiment. In the following drawings, the same parts as those of the device 101 shown in FIGS. 1 and 6 are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 9, 20 is layout information of the target circuit, 21 is a back annotation device for extracting circuit connection information and wiring delay information from the layout information 20, and 22 is circuit connection of the target circuit extracted by the back annotation device 21. Information 23 is wiring delay information calculated by the back annotation device 21. The layout information 20 is given from the outside.

Further, reference numeral 24 is a delay time of the clock wiring, that is, a delay time of the clock propagating through the clock wiring (clock delay) is calculated based on the circuit connection information 22 and the wiring delay information 23, and the data transfer side clock and the data are transmitted. A clock delay calculation unit that outputs a clock delay separately for each of the reception side clocks, 25 is a data transfer side clock delay calculated by the clock delay calculation unit 24, and 26 is a clock delay calculation unit 2
4 is a clock delay on the data reception side calculated by 4.

Further, 27 is a clock delay adding section for adding the data transfer side clock delay 25 to the data transfer side clock information 1 and adding the data reception side clock delay 26 to the data reception side clock information 2, and 28 is the data transfer side. Clock information with data transfer side delay, which is obtained by adding the data transfer side clock delay 25 to the clock information 1, and 29, Clock information with data reception side delay, which is obtained by adding the data reception side clock delay 26 to the data reception side clock information 2. Is.

In the following, the target circuit Y1 shown in FIG.
The operation of the device 102 will be described with reference to FIG. The device 102 operates according to the flowchart of FIG. That is, when the device 102 starts operating, first, in step S20, circuit connection information and wiring delay information are extracted. This process is performed by the target circuit Y input from the outside.
It is executed by the back annotation device 21 based on the layout information 20 about 1.

The layout information 20 is created in association with the layout design of the target circuit Y1. Apparatus 1
In 02, the timing verification is performed by adding the layout information 20. That is, the device 102
Then, there is an advantage that it is not necessary to create new data in order to perform the timing verification.

The circuit connection information 22 extracted by the back annotation device 21 corresponds to the circuit connection information 7 supplied to the device 101. That is, the circuit connection information 2
2 has information on various elements forming the target circuit Y1 and their connections. When calculating the wiring delay information 23, the back annotation device 21 first extracts wiring capacitance and wiring resistance from the layout information 20.

Next, the process proceeds to step S21, and the clock delay calculation section 24 calculates the clock delay. That is, in FIG. 2, the delay time of the clock wiring for transmitting the clocks T1 to T3 is calculated. That is, the delay time of the wiring from the input terminal (indicated by a white triangle in FIG. 2) of the target circuit Y1 for receiving each clock T1 to T3 from the outside to the clock terminal T of each element U1 to U6 is calculated. To be done.

The clock delay calculating section 24 further includes
For each combination N = 1 to 6 of the data transfer side clock and the data reception side clock as shown in FIG. 4, the data transfer side clock delay 25 and the data reception side clock delay 2
6 and 6 are created and output. For example, for the combination N = 1 in FIG. 4, as shown in the circuit diagram of FIG.
The wiring delay time Delay1 of the clock T1 is output as the data transfer side clock delay 25, and the wiring delay time Delay2 of the clock T2 is output as the data reception side clock delay 26.

Next, the process proceeds to step S22, and the data transfer side clock information 1 and the data reception side clock information 2 are externally supplied to the clock delay adding section 27.
Is entered. This step S22 may be executed prior to the next step S23.
The front-rear relationship with S22 may be arbitrary.

Next, in step S23, the clock delay addition unit 27 performs the clock delay addition processing. That is, data transfer side clock information 1
To the data transfer side clock delay 25 and output as the data transfer side delay clock information 28, and the data reception side clock information 2 to the data reception side clock delay 26 and output as the data reception side delay clock information 29. To do.

In the following steps S24 to S26, steps S13 to S14 in the device 101 according to the first embodiment are performed.
In, processing is performed by replacing the clock information 1 and 2 with the clock information with delay 28 and 29. Therefore, in the process of step S25, for example, for the combination N = 1 in FIG. 4, Formula (9): {U1rise_tim
e = T1rise_time + Delay1}, the clock rise time U1rise_tim of the data transfer side with delay, which is given by
e is used instead of the data transfer side clock rising time T1rise_time in step S13.

Mathematical expression (10): {U2rise_time =
T2rise_time + Delay2} given clock rising time U2rise_time of the data reception side clock with delay
Is used instead of the data reception side clock rising time T2rise_time in step S13. That is, in equations (5) to (8), the rising time T
The rising edge minimum section Trise is calculated by replacing 1rise_time and T2rise_time with rising times with delay U1rise_time and U2rise_time.

As shown in the timing chart of FIG. 12, rising times with delay U1rise_time, U2r
ise_time is the rising time T1rise_time, T2r of the clocks T1, T2 input to the input terminal of the target circuit Y1.
The delay time Delay1 and Delay of the clock wiring is set to ise_time.
This corresponds to a value obtained by adding 2 to each. That is, the rising times U1rise_time and U2rise_time are the elements U1,
This corresponds to the rising time of the clocks T1 and T2 that reach the clock terminal T of U2.

Further, in step S26, the cycle of steps S141 to S148 is executed as in FIG. That is, steps S145, S146, S147
Then, based on the clock information 1 and 2 and the wiring delay information 23, the timing verification considering the delay of the clock wiring is performed.

Further, the internal configuration of the static timing verification unit 8 which executes step S26 and the relationship with various information are shown in the block diagram of FIG. That is, the internal configuration of the static timing verification unit 8 is the same as that of the static timing verification unit 8 (FIG. 6) of the device 101 according to the first embodiment. The point that the wiring delay information 23 is supplied to the timing evaluation unit 84 is different from the static timing verification unit 8 of the device 101.

For example, in the cycle in which the element U2 is selected as the target element in step S141, step S147
Is performed. At this time, as shown in the timing chart of FIG. 14, the clock T1 input to the clock terminal T of the element U1 is input to the clock terminal T of the element U2 at a time point after the rising edge minimum section Trise has risen. Timing verification is performed under the most severe condition that the clock T2 rises.

That is, the rising timing of the clock T1 supplied by the data transfer side clock information 1, the function of the element U1 supplied by the circuit connection information 22, and the wiring delay information 23.
Based on the above, the time when the output data appears at the output terminal Q of the element U1 is calculated. Further, based on the function of the element S1 supplied by the circuit connection information 22, considering the signal delay time by the element S1 and the wiring delay time Delay3 based on the wiring delay information 23, the data input terminal D of the element U2 is considered. The time when the input data arrives at is calculated.

Then, the clock T2 rising after the rising edge minimum section Trise from the rising timing of the clock T1 and the input data reaching the element U2 are
For example, it is determined whether or not the conditions regarding the setup time Setup and the hold time Hold are satisfied.

As described above, by using the device 102, the timing verification in which the delay time of the clock wiring is also taken into consideration for the target circuit to which a plurality of clocks having a non-double frequency relation is input is It can be executed efficiently based on the timing method.

Instead of directly inputting the clock information 1 and 2, the data input timing information 9, the layout information 20 and the like from the outside, a storage medium is provided, and this information is stored in advance in this storage medium. The device 1 is stored so that each unit of the device can read necessary information from the storage medium as the device operates.
02 may be configured.

<3. Third Preferred Embodiment> In the first and second preferred embodiments, the operation has been described by exemplifying the target circuit having the element that operates at the rising edge of the clock.
However, a circuit having an element that operates at the falling edge or a circuit that has a so-called level sensitive element that operates at the level of a clock can also be the target circuit. In this embodiment,
A characteristic timing verification device in which the number of data transfer cycles can be set from the outside will be described, and an operation example in which a circuit having a level sensitive element is a target circuit will be shown.

FIG. 15 is a circuit diagram showing an example of a target circuit used for explaining the operation of the timing verification device of this embodiment. The target circuit Y2 is the target circuit Y shown in FIG.
1 has a structure in which the elements U1 to U6 as flip-flops that operate at the clock edge are replaced with latches that operate at the clock level.

That is, the element U1 provided in the target circuit Y2
U6 is a falling edge of the clock input to the clock terminal G, that is, a period in which the clock is at a low level (active level) for the data signal input to the data input terminal D at the transition from the normal level to the active level. It is a latch that holds the output for a while and continues to output to the output terminal Q. While the clock is at the high level (normal level), the data signal input to the data input terminal D is output to the output terminal Q as it is.

Clocks T1 to T1 input to the target circuit Y2
T3 is a clock T1 to T3 input to the target circuit Y1.
Is the same as. Therefore, the contents shown in FIG. 4 are valid as they are for the clocks T1 to T3 of the target circuit Y2.

FIG. 16 is a block diagram showing the configuration of the timing verification device 103 of this embodiment. In FIG. 16, 30 is a data transfer cycle input from the outside, 31 is a data transfer side clock information 1, data reception side clock information 2, synchronization time 4, and the number of data through latch stages 30, and the minimum falling edge period Falling edge minimum section calculation unit for calculating
Reference numeral 2 denotes the minimum falling edge section calculated by the minimum falling edge section calculation unit 31.

In the following, the target circuit Y shown in FIG.
The operation of the device 103 will be described with reference to No. 2 as an example. The device 103 operates according to the flowchart of FIG.
That is, when the device 103 starts operating, the processes of steps S31 to S32 are first executed. These processes are the same as the processes of steps S11 to S12 in the apparatus 101.

After that, the process proceeds to step S33, and the falling edge minimum section calculating unit 31 calculates the falling edge minimum section. This calculation is performed by the combination N = 1, 1 in FIG.
This is performed for each of 3, 4, and 6. The calculation procedure will be described below for an example of the combination of clocks T1 and T2 (N = 1).

First, the synchronization time Syn2 next to the synchronization time Syn1 is calculated according to the above-mentioned mathematical expression (2).
Next, the data transfer side clock falling time T1fa
ll_time is represented by Formula (11): {T1fall_time = Cyc1
Xm} is defined. Similarly, the data reception side clock fall time T2fall_time is calculated by the following equation (12): {T2f
All_time = Cyc2 × n} is defined. Here, the variables m and n are both natural numbers.

Then, the equation (13): {T1fall_tim
e + (data transfer cycle) <T2fall_time}, Formula (14): {Syn1 ≦ T1fall_time <Syn2},
And Expression (15): {Syn1 <T2fall_time ≦
The minimum value of the difference between T2fall_time and T1fall_time is calculated as the falling edge minimum section Tfall in a range that satisfies all three conditions given by Syn2}.

That is, the minimum falling edge section Tfa
ll is the minimum value for all natural numbers m and n that satisfy the expressions (13) to (15), and is defined by the expression (16): {Tfall = M
It is obtained by calculating based on IN (T2fall_time-T1fall_time)}. The “data transfer cycle” used in the equation (13) is a value input from the outside as the data transfer cycle 30.

As a result, when "zero" is input as the data transfer cycle, as shown in the timing chart of FIG.
It is given as the minimum value of the time interval from the falling time of the clock T1 to the subsequent falling time of the clock T2. On the other hand, when "1" is input as the data transfer cycle, as shown in the timing chart of FIG. 19, the minimum falling edge period Tfall is from the falling time of the clock T1 to the clock T2 after that.
It is given as a value obtained by adding one cycle of the clock T2 to the minimum value of the time interval until the falling time of.

Then, the process proceeds to step S34. In step S34, as in FIG. 7, step S1
The cycles of 41 to S148 are executed. For example, in the cycle in which the element U2 is selected as the target element in step S141, the process of step S147 is executed. At this time, as shown in the timing chart of FIG. 18 or FIG. 19, the timing verification is performed against the most severe condition that the clock T2 falls at the time when the falling edge minimum section Tfall has passed after the clock T1 fell. Is done.

That is, based on the falling timing of the clock T1 supplied by the data transfer side clock information 1 and the function of the element U1 supplied by the circuit connection information 7, the element U
The time when the output data appears at the output terminal Q of 1 is calculated. Further, based on the function of the element S1 supplied by the circuit connection information 7, the time at which the input data arrives at the data input terminal D of the element U2 is calculated in consideration of the signal delay time Delay of the element S1.

Whether or not the clock T2 falling after the falling edge minimum section Tfall from the falling timing of the clock T1 and the input data reaching the element U2 satisfy the conditions regarding the setup time Setup and the hold time Hold, for example. Is determined. The value of the data transfer cycle 30 is appropriately determined in consideration of the delay time of the signal from the output terminal Q of the element U1 to the data input terminal D of the element U2, as illustrated in FIGS.

As described above, by using the device 103, the timing verification in consideration of the data transfer cycle is performed for the target circuit to which a plurality of clocks having a non-double frequency relationship are input, by the static timing method. It is possible to execute efficiently based on this. Further, as exemplified in this embodiment, the devices 101 to 103 can also be used for a target circuit having a level-sensitive element with respect to a clock.

Instead of directly inputting the clock information 1 and 2, the circuit connection information 7, the data input timing information 9, the data transfer cycle 30, etc. from the outside,
A storage medium is provided, and these pieces of information are stored in the storage medium in advance, and the device 102 is configured so that each unit of the device appropriately reads necessary information from the storage medium as the device operates. You may comprise.

<4. Fourth Preferred Embodiment> FIG. 20 is a block diagram showing a configuration of a timing verification device 104 according to a fourth preferred embodiment. In FIG. 20, reference numeral 41 indicates that the target circuit operates in two clock cycles different from a single-clock operation logic circuit block (hereinafter abbreviated as “first type block”) based on the circuit connection information 7 input from the outside. A logical circuit block dividing unit that divides the logical circuit block (hereinafter abbreviated as “second type block”) into a logical circuit block, and 42 represents connection information regarding the first type block divided by the logical circuit block dividing unit 41 (hereinafter, “second type block”). (Abbreviated as "type 1 block connection information"), and 43 is the logic circuit block dividing unit 4
It is information regarding a type 2 block divided by 1 (hereinafter abbreviated as "type 2 block connection information").

Reference numeral 61 is information about the rising timing, the cycle, etc. of the clock input to the target circuit, that is, clock information. This clock information 61 is given from the outside.

Further, reference numeral 62 is for the type 1 block,
A static timing verification unit 62 executes static timing verification by a conventionally known method while referring to the first type block connection information 42, clock information 61, and data input timing information 9, and 45 is a static timing verification unit 62. As a result of the timing verification, 46 is a test pattern generation unit that generates an input test pattern for performing the dynamic timing verification for the second type block based on the static timing verification result 45 and the clock information 1, and 47 is It is an input test pattern generated by the test pattern generation unit 46.

Further, 48 is a dynamic timing verification unit for performing dynamic timing verification on the second type block based on the input test pattern 47, and 49 is a dynamic timing verification result obtained by the dynamic timing verification unit 48. ,
Reference numeral 50 denotes a data input timing extraction unit that extracts information on the input timing of the data signal to be input to the first type block from the dynamic timing verification result 49, and 5
Reference numeral 1 is a data input timing extracted by the data input timing extraction unit 50.

The dynamic timing verification result 49 is also input to the test pattern generator 46. Then, the test pattern generation unit 46 selectively refers to either the static timing verification result 45 or the dynamic timing verification result 49. The data input timing 51 is also input to the static timing verification unit 62. Then, the static timing verification unit 62 selectively refers to either the data input timing information 9 or the data input timing 51.

FIG. 21 is a circuit diagram showing an example of a target circuit to be verified by the device 104. This target circuit Y3
Includes six clocks T11 whose cycles are not necessarily the same.
To T16 and external input data Data11 are input from the outside through an input terminal (shown by a white triangle in the drawing). Then, the target circuit Y3 executes a predetermined logical operation based on these signals and outputs the output signals Out11, Ou.
It is configured to output t12 to the outside through an output terminal (shown by a white triangle in the figure).

Seven elements U10 to 10 provided in the target circuit Y1.
U16 holds the data signal input to the data input terminal D until the next rising edge of the clock in synchronization with the rising edge of the clock input to the clock terminal T, that is, the transition from the normal level to the active level. Is a flip-flop that continues to output to the output terminal Q. The elements S101 to S105 are arbitrary elements or a combination of elements that delay the propagation of signals. The element S106 is a NAND element.

The operation of the device 104 will be described below by taking the target circuit Y3 as an example. The device 104 operates according to the flowchart of FIG. That is,
When the device 104 starts operating, first, in step S41, the circuit connection information 7 is input from the outside to the logic circuit block division unit 41, and the clock information 61 is input to the static timing verification unit 62 and the test pattern generation unit 46. To be done.

The circuit connection information 7 and the clock information 61 are provided manually from the outside or by using an external input device. Further, instead of directly inputting such information to the logic circuit block dividing unit 41 or the static timing verification unit 62, a storage medium may be provided in the device 104 and stored in this storage medium. And then
The static timing verification unit 62 or the like may read out a necessary portion of information from the storage medium as needed while the processing is proceeding.

Next, in step S42, division into logic circuit blocks is performed by the logic circuit block division unit 41. That is, the target circuit Y3 is divided into a first type block and a second type block. As shown in FIG. 21, the target circuit Y3 is divided into blocks BL1 to BL9. The blocks BL1, BL4, and BL9 are blocks that operate only with the clocks T11, T14, and T16, respectively, and all belong to the type 1 block. Blocks BL2, BL3, BL5-BL8 are all 2
It is a block that operates with individual clocks and belongs to the second type block.

The first type block connection information 42 is obtained by extracting the portions of the blocks BL1, BL4, BL9 belonging to the first type block from the circuit connection information 7. Similarly, the second type block connection information 4 is obtained by extracting the portions related to each of the blocks BL2, BL3, BL5 to BL8 belonging to the second type block.
3 is obtained.

Next, the process proceeds to step S43, and the block BL1 located closest to the input side among the blocks BL1, BL4, BL9 classified as the first type block by the static timing verification unit 62 is performed. Static timing verification is done. Since only one clock T11 is input to the block BL1, the static timing verification of the block BL1, that is, the element U10,
The static timing verification for U11 is performed by a conventionally known method for a target circuit that operates with a single clock.

At this time, the operation of the elements U10 and U11, the characteristics such as the setup time Setup and the hold time Hold, and the delay time DelayA due to the element S101 are ascertained based on the first type block connection information 42. Also,
The timing of the external input data Data11 is grasped based on the data input timing information 9, and the clock information 6
Based on 1, the timing of the clock T11 is grasped. The result of the timing verification is output as the static timing verification result 45.

Next, in step S44, it is determined whether or not a block exists on the output side. Since the block BL2, which is the second type block, exists on the output side of the block BL1, the determination result is “Yes”, and the process proceeds to step S46. In step S46, block B
An input test pattern for performing dynamic timing verification for L2 is created based on the static timing verification result 45 for block BL1. That is,
The test pattern generation unit 46 generates patterns of two input signals to the block BL2, that is, patterns of a data signal input to the data input terminal D and a clock signal input to the clock terminal T of the element U11.

FIG. 23 is a timing chart showing an example of the input test pattern of the block BL2 created by the test pattern generator 46. As shown in FIG. 23, the data signal U input to the data input terminal D of the element U11.
11 / D changes every time the clock signal T11 input to the clock terminal T rises twice, and is delayed by the delay time DelayA.

Then, the process proceeds to step S47,
The dynamic timing verification unit 48 performs dynamic timing verification on the block BL2. The dynamic timing verification is a conventionally well-known method for performing timing verification by using a logic simulation. The dynamic timing verification unit 48, based on the second type block connection information 43, each of the elements U11 and U1 that form the block BL2.
2, the type and connection state of S102 are grasped, and the behavior of each element when the input test pattern 47 is input is simulated.

Then, based on the result of the simulation, it is judged whether or not the conditions such as the setup time Setup and the hold time Hold are satisfied. Therefore, the verification is performed in consideration of the delay time DelayB due to the element S102. The verification result is output as the dynamic timing verification result 49.

Next, in step S48, it is determined whether or not the first type block is connected to the output side. Since the block BL3, which is the second type block, is connected to the output side of the block BL2, the determination result is “No”, and the process returns to step S46. In step S46, an input test pattern for executing the dynamic timing verification for the block BL3 is created based on the dynamic timing verification result 49 for the block BL2.

Thereafter, the processing shifts to step S47,
Based on the newly created input test pattern 47, the dynamic timing verification for the block BL3 is executed by the dynamic timing verification unit 48.

Since the block BL4, which is the first type block, is connected to the output side of the block BL3, it is determined "Yes" at the subsequent step S48. Therefore, the process proceeds to step S49. Step S
In 49, the data input timing of the block BL4, that is, the input timing of the data input to the data input terminal D of the element U14 is extracted from the dynamic timing verification result 49 for the block BL3. This process
The data obtained by the data input timing extraction unit 50 is output as the data input timing 51.

The extraction by the data input timing extraction section 50 is performed as shown in the timing chart of FIG.
For example, four types of timing are extracted that minimize the time difference between the time when the data input to the data input terminal D of the element U12 changes and the time when the clock T12 input to the clock terminal T changes. Carried out by. Setup (rise), setup (fall), hold (r
ise) and hold (fall) are the minimum time differences at these four types of timings.

Of these, the time differences marked with "rise" and "fall" in parentheses are the time differences when the input data rises and when the input data falls, respectively. Moreover, the time differences described as “setup” and “hold” refer to setup time Setup and hold time Hold, respectively.

Then, the process proceeds to step S43, and the static timing verification unit 62 executes the static timing verification for the block BL4. At this time, the data input timing information 9 is not referred to, but the data input timing 51 is referred to instead.

Since the block no longer exists on the output side of the block BL4, in the subsequent step S44,
It is determined to be “No”. As a result, the process is step S4.
Go to 5. In step S45, it is determined whether or not an unverified block exists in the target circuit Y3. Since the blocks including the block BL5 are left unverified, it is determined to be “Yes”, and the process proceeds to step S43.

Through the above processing, the blocks BL1 and B
The timing verification along the sequence of L2, BL3, BL4 is completed. By repeating the same process, timing verification of the series of blocks BL1, BL5, BL6, BL4 and the series of blocks BL1, BL7, BL8, BL9 is performed. When all of these verifications are completed, the determination of “No” is obtained for the first time in step S45, and all the processing is completed.

In the target circuit Y3, only the second type block exists between the first type block and the first type block in any of the series, but for example, the block BL1,
In the series of BL2, BL3, BL4, the device 104 is also used to verify the target circuit in which the first type block (provisionally referred to as block BL10) exists between the second type blocks BL2 and BL3. It is possible to

As described above, the device 104 appropriately uses the static timing method and the dynamic timing method for each circuit block, thereby performing timing verification on the target circuit to which a plurality of clocks having different periods are input. It is possible.

The plurality of clocks input to the target circuit Y3 may be clocks having different periods but also independent of each other and not synchronized. With any of these, the device 104 performs the verification of the target circuit in the same manner.

<5. Modifications> Device 1 of each of the above embodiments
01 to 104 are not limited to the forms illustrated in each of them, and a circuit that operates in synchronization with either the rising or the falling of the clock can be the verification target. That is, the target circuit may generally operate in synchronization with the change time of each clock from the normal level to the active level.

Furthermore, as illustrated in the third embodiment,
A level-sensitive circuit that operates at the clock level can also be the verification target. Although the third embodiment has shown the example in which the low level is the active level, it goes without saying that the active level may be the high level.

[0125]

In the device of the first aspect of the present invention, a pair of clocks having a non-double frequency relationship are respectively input, and at the data receiving side among the elements having the relationship between the data transfer side element and the data receiving side element. Timing verification between the input data signal and the clock signal is performed on the element. Since the verification is performed under the strictest condition that the timing at which the pair of clocks changes is in the relationship of the minimum interval, the verification purpose is achieved. Moreover, this verification method belongs to the static timing method. That is, the timing verification of the target circuit to which the clocks in the non-multiplied relationship are input is performed without impairing the high speed of the static timing.

The apparatus of the second invention is provided with a target element searching means, a path searching means, and a clock judging means, and further, the timing evaluating means, in accordance with the judgment of the clock judging means, divides the frequency of a pair of clocks, A static timing method adapted to the non-doubled relation is selected and executed. Therefore, in the target circuit to which a plurality of clocks are input, whether the relationship between the clocks is doubled or non-doubled, or includes both relationships, the data transfer side element and the data receiving side Timing verification is comprehensively performed by a static timing verification method for all data reception side elements having a relationship of elements.

In the device of the third invention, when the path search means cannot find the data transfer side element, that is, without passing through the data transfer side element which operates in synchronization with the clock, the data signal is transmitted from the outside to the target element. , The timing verification of the target element is performed with reference to the data input timing information. Therefore, in a target circuit to which a plurality of clocks are input, no matter whether the relationship between the clocks is doubled or non-doubled, or both relationships are included, all elements included in the target circuit are On the other hand, the timing verification is comprehensively performed by the static timing verification method.

In the device of the fourth invention, since the delay time of the clock wiring is reflected in the calculation of the minimum section, the clock wiring is input to the target circuit to which a plurality of clocks having a non-double frequency relationship are input. The timing verification that considers the delay time is also executed at high speed based on the static timing method.

Since the apparatus of the fifth invention is provided with the back annotation means, it is possible to use the layout information created in association with the layout design of the target circuit, and to obtain the circuit connection information and the information regarding the wiring delay time. No need to prepare separately. That is, the labor and time required to perform the timing verification are saved.

In the device of the sixth aspect of the present invention, the data transfer cycle which is appropriately set from the outside is added to the minimum section, so that the target circuit to which a plurality of clocks having a non-double frequency relationship are input, Timing verification considering the data transfer cycle is efficiently performed based on the static timing method.

In the device of the seventh aspect of the present invention, since the minimum interval is searched for in the period corresponding to the least common multiple of both cycles with respect to the clocks having the non-multiplication frequency, the efficiency is high and There is no omission in search.

In the apparatus of the eighth aspect of the invention, the minimum interval calculating means sets the minimum interval for all combinations of clocks which are in a non-doubled relationship among a plurality of clocks input to the target circuit. Is calculated, it is not necessary to refer to the circuit connection information and select a combination that requires the calculation of the minimum section. That is, the processing efficiency is improved.

In the device of the ninth invention, the static timing method and the dynamic timing method are properly used according to the type of circuit block, and when the verification of one circuit block is completed, the output of this circuit block is output. Necessary input data is created according to the type of circuit block connected to the side. Therefore, the timing verification is comprehensively performed on the target circuit to which a plurality of clocks having different periods are input. In addition, the dynamic timing verification is performed only for the type 2 blocks that require the dynamic timing verification, and the static timing is executed for the type 1 blocks that can be subjected to the static timing verification. Well verified.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to a first embodiment.

FIG. 2 is a block diagram showing an example of a target circuit.

FIG. 3 is a flowchart showing the operation of the device according to the first embodiment.

FIG. 4 is an explanatory diagram showing an example of clock information.

FIG. 5 is a timing chart illustrating the operation of the device according to the first embodiment.

FIG. 6 is a block diagram of a static timing verification unit according to the first embodiment.

FIG. 7 is a flowchart of a static timing verification unit according to the first embodiment.

FIG. 8 is a timing chart illustrating the operation of the device according to the first embodiment.

FIG. 9 is a block diagram of an apparatus according to a second embodiment.

FIG. 10 is a flowchart showing an operation of the device according to the second embodiment.

FIG. 11 is a block diagram showing a part of a target circuit.

FIG. 12 is a timing chart showing the operation of the device according to the second embodiment.

FIG. 13 is a block diagram of a static timing verification unit according to the first embodiment.

FIG. 14 is a timing chart showing the operation of the device according to the second embodiment.

FIG. 15 is a block diagram showing another example of the target circuit.

FIG. 16 is a block diagram of an apparatus according to a third embodiment.

FIG. 17 is a flowchart showing the operation of the apparatus according to the third embodiment.

FIG. 18 is a timing chart showing the operation of the device according to the third embodiment.

FIG. 19 is a timing chart showing the operation of the device according to the third embodiment.

FIG. 20 is a block diagram of an apparatus according to the fourth embodiment.

FIG. 21 is a block diagram showing still another example of the target circuit.

FIG. 22 is a flowchart showing an operation of the apparatus according to the fourth embodiment.

FIG. 23 is a timing chart showing the operation of the device according to the fourth embodiment.

FIG. 24 is a timing chart showing the operation of the device according to the fourth embodiment.

FIG. 25 is a block diagram of a conventional device.

FIG. 26 is a timing chart showing the operation of the conventional device.

[Explanation of symbols]

1 data transfer side clock information (clock information), 2
Data receiving side clock information (clock information), 5 rising edge minimum section calculation unit (minimum section calculation means), 7
Circuit connection information, 9 Data input timing information, 20
Layout information, 21 back annotation device (back annotation means), 23 wiring delay information,
24 clock delay calculating unit (clock delay calculating unit), 27 clock delay adding unit (clock delay adding unit), 30 data transfer cycle (data transfer cycle information), 41 logic circuit block dividing unit (block dividing unit), 42 first Seed block connection information, 4
3 type 2 block connection information, 46 test pattern generation unit (test pattern generation means), 48 dynamic timing verification unit (dynamic timing verification means), 50 data input timing extraction unit (data input timing extraction means), 62 static Timing verification section (static timing verification means), 81 target element search section (target element search means), 82 path search section (path search means), 83
Clock determination unit (clock determination unit), 84 Timing evaluation unit (timing evaluation unit), Trise rising edge minimum section (minimum section), Tfall falling edge minimum section (minimum section).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor table Yumi Marunouchi 2-3-3 Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd. (72) Inventor Takamitsu Fujiwara 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Ryodenki Co., Ltd. (72) Inventor Hiroyuki Hamano 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Denki Co., Ltd.

Claims (9)

[Claims] 1. A timing verification device for verifying the timing of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks, wherein the clocks among the plurality of clocks are based on clock information defining the plurality of clocks. With respect to the clocks that are in a non-double frequency relationship with each other, the minimum interval calculating means that calculates the closest time interval, that is, the minimum interval, in the range in which the times when one level changes to the other level do not match each other, and the non-double frequency A circuit including a pair of the plurality of elements having a relationship of a data transfer side element and a data receiving side element and a path of a data signal between them while a pair of clocks having the relationship of For the part, the circuit connection information defining the target circuit is referred to, and the change time of the pair of clocks is related to the minimum interval. On condition that, timing verification apparatus characterized by comprising: a timing evaluation means, a to perform validation of the timing between the clock and the data signal input to the data receiver elements. 2. A timing verification device for verifying the timing of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks, wherein the plurality of clocks among the plurality of clocks are defined based on clock information defining the plurality of clocks. A minimum interval calculating means for calculating the closest time interval, that is, the minimum interval, in a range in which the times at which the levels change from one level to the other level do not coincide with each other with respect to the clocks having a non-double frequency relationship with each other; On the basis of the circuit connection information that defines the target element search means for sequentially selecting one as a target element from the plurality of elements, and the target element selected by the target element search means as a data receiving side element. , A data transfer-side element corresponding to this is searched for from the plurality of elements based on the circuit connection information. And a means for determining, based on the clock information, whether the relation between the pair of clocks respectively input to the data transfer side element and the data reception side element is doubled or non-doubled. The circuit connection information is referred to for a circuit portion including a clock determination means, the data transfer side element, the data reception side element, and a data signal path between them, and the determination result is doubled. Is referred to, the clock information is referred to, and when the result of the determination is a non-doubled frequency, the data reception side is controlled by the condition that the change times of the pair of clocks are in the relationship of the minimum interval. Timing evaluation means for executing timing verification between a clock input to the device and the data signal; Apparatus. 3. The timing verification apparatus according to claim 2, wherein the timing evaluation unit further inputs the target element and the target element when the path search unit cannot find the data transfer side element. The target element based on the data input timing information that defines the external input data signal and the clock information while referring to the circuit connection information with respect to the circuit portion including the path of the external input data signal. A timing verification device, characterized in that it verifies the timing between a clock input to the external input data signal and the external input data signal. 4. The timing verifying device according to claim 1, wherein the wiring delay information that defines a signal delay time of the wiring of the target circuit and the circuit connection information are used for the above-mentioned wiring. Clock delay calculating means for individually calculating delay times of a plurality of clock wirings for transmitting a clock to a plurality of elements; and, for each of the plurality of elements, at a timing specified by the clock information with respect to a clock input to the element. Clock delay adding means for creating delay-added clock information by adding a delay time; and the minimum interval calculating means, by referring to the delay-added clock information instead of the clock information, A timing verification device characterized by calculating a minimum interval. 5. The timing verification apparatus according to claim 4, further comprising back annotation means for extracting the circuit connection information and the wiring delay time from layout information that defines a layout of the target circuit. A characteristic timing verification device. 6. The timing verification apparatus according to claim 1, wherein the minimum interval calculation means adds a data transfer cycle specified by data transfer cycle information to the calculated minimum interval. The timing verification means refers to the value obtained by adding the data transfer cycles as the minimum section. 7. The timing verification device according to claim 1, wherein the minimum interval calculation means corresponds to a least common multiple of both cycles with respect to a clock having a non-double frequency relationship. The timing verification apparatus is characterized in that the minimum section is searched for in the period. 8. The timing verification apparatus according to claim 1, wherein the minimum interval calculation means includes all sets of clocks that are in a non-double frequency relationship among the plurality of clocks. A timing verification apparatus, characterized in that the minimum section is calculated for the matching. 9. A timing verification device for verifying the timing of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks, wherein the target circuit is synchronized with a single clock based on circuit connection information defining the target circuit. The target circuit is divided into a first type block that operates in accordance with two different clocks, and a second type block that operates in synchronization with two different clocks, and the first type block connection relating to the first type block from the circuit connection information. Block dividing means for extracting information and second type block connection information relating to the second type block; static timing verifying means for performing static timing verification on the first type block; Test pattern generation means for generating an input test pattern for performing dynamic timing verification on the seed block; The dynamic timing verification for the second type block on the basis of the second type block connection information and the second type block on the output side of the second type block subjected to the dynamic timing verification. When two kinds of blocks are connected, a dynamic timing verification means for supplying a result of the dynamic timing verification to the test pattern generation unit and an output side of the second kind block targeted for the dynamic timing verification. When the type 1 block is connected, data input timing information that defines the timing of the data signal input to the type 1 block is extracted from the result of the dynamic timing verification, and the static timing verification means. Data input timing extracting means for supplying the data to the first type block connection information. Of the data input timing information that specifies the external input data signal input from the outside of the target circuit and the data input timing information that is supplied from the data input timing extraction means. By selectively referring to any one of them, the static timing verification is executed, the test pattern generation means refers to the clock information, and the static timing verification result and the dynamic timing. A timing verification device, wherein the input test pattern is generated by further selectively referring to one of verification results.