JP3715706B2 - Timing verification device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a timing verification device, and more particularly to an improvement for enabling timing verification of a target circuit to which a plurality of clocks that are not in a frequency-division relationship are input.
[0002]
[Prior art]
Conventionally, a static timing verification method is known as an effective method for performing timing verification of a large-scale circuit represented by an LSI (Large Scale Integrated Circuit). The static timing verification method is a verification method based on a path analysis method for a synchronous circuit, and has an advantage that processing can be performed comprehensively and at high speed without using a verification pattern.
[0003]
FIG. 25 is a block diagram showing a conventional timing verification apparatus that performs static timing verification. This conventional device 150 includes a static timing verification unit 120 as the most main device unit. In the static timing verification unit 120, the circuit connection information 7 which is information regarding the configuration of the target circuit, that is, the circuit subjected to timing verification, and data describing the timing of the external input data input to the target circuit Input timing information 9 is input. In addition, when performing back annotation verification, wiring delay information 23 having information on wiring capacitance and wiring resistance is input.
[0004]
Further, the static timing verification unit 120 is configured to be able to verify a target circuit that operates with a plurality of clocks. Information regarding the timing of all clocks input to the verification circuit, that is, clock information 121 is prepared. In the static timing verification unit 120, necessary clock information is appropriately used from the clock information 121 as the verification operation proceeds.
[0005]
The static timing verification unit 120 performs static timing verification of the target circuit based on these pieces of information.
[0006]
[Problems to be solved by the invention]
However, in the conventional device 150, although a circuit that operates with a plurality of clocks can be a target for verification, the plurality of clocks have to be in a double-frequency relationship. That is, as illustrated in the timing chart of FIG. 26, there is a problem in that the period of the transfer side clock T21 and the reception side clock T22 belonging to each set must have a natural number multiple relationship. It was.
[0007]
The present invention has been made in order to solve the above-described problems in the conventional apparatus, and to a target circuit to which a plurality of clocks that are not in a double frequency relationship are input while taking advantage of the static timing verification. However, it is an object of the present invention to provide a timing verification apparatus that can execute timing verification.
[0008]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a timing verification apparatus that performs timing verification of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks. The plurality of clocks are based on clock information that defines the plurality of clocks. A minimum interval calculating means for calculating the closest time interval, that is, the minimum interval in a range in which the time at which the level changes from one level to the other level do not coincide with each other with respect to the clocks that are not doubled in the clock, A pair of clocks in a non-multiplier relationship are respectively input, a pair of the plurality of elements in a relationship between a data transfer side element and a data reception side element, and a data signal path between them, Circuit connection information defining the target circuit is referred to, and the change time of the pair of clocks is related to the minimum section. With the proviso that in, characterized in that it comprises a timing evaluation means for performing a verification of the timing between the clock and the data signal input to the data receiver elements.
[0009]
According to a second aspect of the present invention, there is provided a timing verification apparatus for performing timing verification of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks. The plurality of clocks based on clock information defining the plurality of clocks. A minimum interval calculating means for calculating the closest time interval, that is, the minimum interval in a range in which the time at which the level changes from one level to the other level do not coincide with each other with respect to the clocks that are not doubled in the clock, Based on circuit connection information defining the target circuit, target element search means for sequentially selecting one target element from the plurality of elements, and receiving the target element selected by the target element search means A side element and a data transfer side element corresponding to the side element are searched for from the plurality of elements based on the circuit connection information. Based on the search means and the clock information, a determination is made as to whether the relationship between a pair of clocks input to the data transfer side element and the data reception side element is a double frequency or a non-multiplier, respectively. The circuit determination information is referred to the clock determination means, the data transfer side element, the data reception side element, and the circuit portion including the data signal path therebetween, and the result of the determination is doubled. The clock information is referred to, and when the result of the determination is non-multiplied, the data receiving side is configured on the condition that the change times of the pair of clocks are in the relationship of the minimum interval. Timing evaluation means for performing verification of timing between a clock input to the element and the data signal.
[0010]
The apparatus according to a third aspect is the timing verification apparatus according to the second aspect, wherein the timing evaluation means further determines that the path search means cannot find the data transfer side element, and sends the target element and the target element. The circuit portion including the path of the external input data signal to be input is referred to the circuit connection information, and based on the data input timing information defining the external input data signal and the clock information, The verification of the timing between the clock input to the target element and the external input data signal is executed.
[0011]
A device of a fourth invention is the timing verification device of any one of the first to third inventions, based on wiring delay information defining a signal delay time of the wiring of the target circuit and the circuit connection information. A clock delay calculating means for individually calculating a delay time of a plurality of clock wirings for transmitting a clock to the plurality of elements; and a timing specified by the clock information for a clock input to the element for each of the plurality of elements. Clock delay addition means for creating clock information with delay by adding the delay time, and the minimum interval calculation means, by referring to the clock information with delay instead of the clock information, The minimum interval is calculated.
[0012]
According to a fifth aspect of the invention, in the timing verification apparatus of the fourth aspect, the apparatus further comprises back annotation means for extracting the circuit connection information and the wiring delay time from the layout information that defines the layout of the target circuit. It is characterized by that.
[0013]
According to a sixth aspect of the present invention, in the timing verification device according to any one of the first to third aspects, the minimum interval calculation means adds a data transfer cycle defined in the data transfer cycle information to the calculated minimum interval. In addition, the timing evaluation means refers to the value added with the data transfer cycle as the minimum interval.
[0014]
The apparatus according to a seventh aspect is the timing verification apparatus according to any one of the first to sixth aspects, wherein the minimum interval calculation means sets the least common multiple of both periods to a clock having a non-multiplication relationship. The minimum interval is searched in a corresponding period.
[0015]
According to an eighth aspect of the present invention, in the timing verification apparatus according to any one of the first to seventh aspects, the minimum interval calculation means includes all the clocks having a non-multiplication relationship among the plurality of clocks. The minimum interval is calculated for the combination.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
<1. Embodiment 1>
First, the timing verification apparatus according to the first embodiment will be described.
[0018]
<1-1. Overall configuration and operation>
FIG. 1 is a block diagram showing the configuration of the timing verification apparatus 101 of this embodiment. In FIG. 1, reference numeral 1 denotes information related to the rise time, period, etc. of the clock on the data transfer side used in a block in which data transfer is performed with clocks having different periods among the clocks input to the target circuit, that is, the data transfer side Clock information, 2 is data reception side clock information used in the same block as the data transfer side clock information 1. These clock information 1 and 2 are given from the outside.
[0019]
Further, 3 is a synchronization time calculation unit that calculates the time at which the data transfer side clock information and the data reception side clock information rise simultaneously (synchronization time), 4 is a synchronization time that is numerical information calculated by the synchronization time calculation unit 3, 5 is calculated by the rising edge minimum interval calculation unit for calculating the rising edge minimum interval based on the data transfer side clock information, the data reception side clock information and the synchronization time, and 6 is calculated by the rising edge minimum interval calculation unit 5. This is the minimum rising edge section that is numerical information.
[0020]
Further, 7 is circuit connection information which is information given from the outside regarding the configuration of the target circuit, and 9 is data input timing information. The circuit connection information 7 is information corresponding to the circuit diagram of the target circuit, that is, information relating to the types of elements constituting the target circuit and the connection of those elements, and is given from the outside. The data input timing information 9 is information relating to the time when the external input data input to the target circuit changes, and is described in particular so that the relative relationship with the clock rising time becomes clear. This data input timing information 9 is also given from the outside.
[0021]
Finally, reference numeral 8 denotes a static timing verification unit that performs static timing verification based on the clock information 1, the rising edge minimum section 6, the circuit connection information 7, and the data input timing information 9.
[0022]
FIG. 2 is a circuit diagram illustrating an example of a target circuit to be verified by the apparatus 101. Three clocks T1 to T3 having different periods and two external input data Data1 and Data2 are inputted to the target circuit Y1 from the outside through input terminals (indicated by white triangles in the figure). The target circuit Y1 is configured to execute a predetermined logical operation based on these signals and output the output signal Out to the outside through an output terminal (indicated by a white triangle in the figure).
[0023]
Among the clocks T1 to T3, the clocks T1 and T3 are in a double-frequency relationship, and the clock T2 is in a non-multiplier relationship with the other clocks T1 and T3. That is, a plurality of clocks including clocks having a non-multiplication relationship with each other are input to the target circuit Y1.
[0024]
The six elements U1 to U6 included in the target circuit Y1 are data signals input to the data input terminal D in synchronization with the rising edge of the clock input to the clock terminal T, that is, the transition from the normal level to the active level. Is held until the next rising edge of the clock and continues to be output to the output terminal Q. The elements S1 to S3 are arbitrary elements or combinations of elements that cause a delay in signal propagation. The element S4 is a NAND element.
[0025]
Hereinafter, the operation of the device 101 will be described using the target circuit Y1 as an example. The apparatus 101 operates according to the flowchart of FIG. That is, when the device 101 starts operation, first, in step S11, the data transfer side clock information 1 and the data reception side clock information 2 are given to the synchronization time calculation unit 3. Such clock information 1 and 2 is given manually from the outside or using an external input device.
[0026]
FIG. 4 illustrates the contents of the clock information 1 and 2 for the target circuit Y1. The clock information 1 and 2 is obtained by distributing the clocks T1 to T3 of the target circuit Y1 between the transfer side and the reception side. The distribution is preferably performed for all possible combinations regardless of the circuit configuration of the target circuit Y1. In this case, the clock information 1 and 2 are prepared corresponding to six combinations N = 1 to 6, as shown in FIG.
[0027]
Next, the process proceeds to step S12, and the synchronization time calculation unit 3 calculates the synchronization time based on the clock information 1 and 2. This calculation is performed for a combination in which the data transfer side clock and the data reception side clock have a non-multiplication relationship. That is, the combinations of the numerical values that are executed and calculated for the combinations N = 1, 3, 4, and 6 shown in FIG. 4 are sent to the rising edge minimum interval calculation unit 5 as the synchronization time 4.
[0028]
The synchronization time Syn1 is calculated as the least common multiple of a set of clock cycles Cyc1 and Cyc2 belonging to the clock information 1 and 2. That is, the synchronization time Syn1 is given by Equation (1): {Syn1 = the least common multiple of the cycles Cyc1 and Cyc2}. For example, for the combination N = 1, the synchronization time Syn1 is given as the least common multiple of the cycle Cyc1 of the clock T1 and the cycle Cyc2 of the clock T2.
[0029]
Next, the process proceeds to step S13, and the rising edge minimum section calculation unit 5 calculates the rising edge minimum section based on the clock information 1 and 2 and the synchronization time 4. This calculation is also performed for each of the combinations N = 1, 3, 4, and 6 in FIG. Hereinafter, a calculation procedure will be described for an example of a combination of clocks T1 and T2 (N = 1).
[0030]
First, the next synchronization time Syn2 after the synchronization time Syn1 is calculated according to Equation (2): {Syn2 = Syn1 × 2}. Subsequently, the data transfer side clock rise time T1rise_time is defined by Expression (3): {T1rise_time = Cyc1 × m}. Similarly, the data reception side clock rise time T2rise_time is defined by Expression (4): {T2rise_time = Cyc2 × n}. Here, the variables m and n are both natural numbers.
[0031]
Subsequently, all three conditions given by Formula (5): {T1rise_time <T2rise_time}, Formula (6): {Syn1 ≦ T1rise_time <Syn2}, and Formula (7): {Syn1 <T2rise_time ≦ Syn2} are all satisfied. The minimum value of the difference between T2rise_time and T1rise_time within the range to be satisfied is calculated as the rising edge minimum interval Trise. In other words, the rising edge minimum interval Trise calculates the minimum value for all natural numbers m and n satisfying the equations (5) to (7) based on the equation (8): {Trise = MIN (T2rise_time−T1rise_time)}. Can be obtained.
[0032]
As a result, as illustrated in the timing chart of FIG. 5, the rising edge minimum interval Trise is given as the minimum value of the time interval from the rising time of the clock T1 to the subsequent rising time of the clock T2. In other words, the rising edge minimum interval Trise is given as the closest time interval in the range where the rising times do not coincide with each other between the clocks T1 and T2. Therefore, the strictest conditions are extracted when the receiving-side element to which the clock T2 is input operates normally.
[0033]
<1-2. Configuration and operation of static timing verification unit 8>
Next, the process proceeds to step S14. At this stage, static timing verification is performed by the static timing verification unit 8. FIG. 6 is a block diagram showing an internal configuration of the static timing verification unit 8. FIG. 7 is a flowchart showing a processing procedure in the static timing verification unit 8. The internal configuration and operation of the static timing verification unit 8 will be described below with reference to FIGS. 6 and 7.
[0034]
When the process of step S14 is started, first, in step S141, a target element to be verified in the target circuit Y1 is searched. This process is performed by the target element search unit 81. That is, the target element search unit 81 searches the target circuit Y1 for an element to be verified for the time being based on the circuit connection information 7.
[0035]
Next, the process proceeds to step S142, and a path search is executed. That is, the clock input to the target element, the receiving element, and its clock are searched. This process is executed by the path search unit 82 based on the information related to the target element selected by the target element search unit 81 and the circuit connection information 7.
[0036]
If the element U2 is selected as the target element, the clock T2 input to the element U2 is first searched by the path search. Subsequently, the signal input to the element U2 is traced, and the element S1, the element U1, and the clock T1 input to the element U1 are searched for. The clock T1 is recognized as the data transfer side clock, and the clock T2 is recognized as the data reception side clock. As a result, in the subsequent processing, only the circuit block X1 including the elements U1 and U2 and the element S1 interposed therebetween in the target circuit Y1 of FIG.
[0037]
Next, the process proceeds to step S143. Here, the clock determination unit 83 makes a first determination regarding the clock. That is, it is determined whether or not the input data to the selected target element is the external input data Data1 and Data2. If the determination result is “Yes”, the process proceeds to step S145, and if “No”, the process proceeds to step S144.
[0038]
In step S144, the clock determination unit 83 continues to perform the second determination. That is, it is determined whether or not the relationship between the data transfer side clock and the data reception side clock is a doubled relationship. This determination is made based on the clock information 1 and 2. If the determination result is “Yes”, the process proceeds to step S136, and if “No”, the process proceeds to step S147.
[0039]
In the example in which the target element is the element U2, the input data is neither the external input data Data1 nor Data2, so the process moves from step S143 to step S144. Then, as shown in FIG. 4, the clocks T1 and T2 are in a non-multiplication relationship with each other, so the processing further proceeds to step S147.
[0040]
If the target element is, for example, the element U3, the input data is the external input data Data1, and therefore the process proceeds from step S143 to step S145.
[0041]
Further, when the target element is U6, for example, the clock T1 becomes the data transfer side clock, and the clock T3 becomes the data reception side clock. Since the input data is neither external data Data1 nor Data2, the process proceeds from step S143 to step S144. Furthermore, since the relationship between the clocks T1 and T3 is a double-frequency relationship as shown in FIG. 4, the process proceeds from step S144 to step S146.
[0042]
The processing of steps S145 to S147 is executed by the timing evaluation unit 84. Among these, the processes in steps S145 and S146 are well-known processes that are also performed by the static timing verification unit 120 of the conventional apparatus 150.
[0043]
In step S145, for example, regarding the target element U3, the timing between the clock T1 supplied by one of the clock information 1 and 2 and the external input data Data1 supplied by the data input timing information 9 is defined by the circuit connection information 7. It is determined whether or not conditions such as setup time and hold time necessary for normal operation of the element U3 are satisfied. When an element is present in the path of the external input data Data1, the delay time due to this element is taken into account by referring to the circuit connection information 7.
[0044]
In step S146, for example, regarding the target element U6, the clocks T1 and T2 supplied by the clock information 1 and 2 are set up time, hold time, and the like necessary for normal operation of the element U6 defined by the circuit connection information 7. It is determined whether or not the above condition is satisfied. At this time, the determination is performed based on the circuit connection information 7 in consideration of the signal delay time due to the element S3 interposed between the elements U5 and U6.
[0045]
In step S147, in addition to the clock information 1, 2 and the circuit connection information 7, the rising edge minimum section 6 is further referred to. For example, when the target element is the element U2, as shown in the timing chart of FIG. 8, after the clock T1 rises, the most severe condition that the clock T2 rises at the time when the rising edge minimum interval Trise is passed. Thus, timing verification is performed.
[0046]
That is, the time when the output data appears at the output terminal Q of the element U1 is calculated based on the rising timing of the clock T1 supplied by the data transfer side clock information 1 and the function of the element U1 supplied by the circuit connection information 7. . Further, based on the function of the element S1 supplied by the circuit connection information 7, the time when the input data reaches the data input terminal D of the element U2 is calculated in consideration of the signal delay time by the element S1.
[0047]
Then, it is determined whether or not the clock T2 that rises after the rising edge minimum interval Tries from the rising timing of the clock T1 and the input data that reaches the element U2 satisfy the conditions relating to the setup time Setup and the hold time Hold, for example. For example, the time when the input data arrives at the element U2 precedes the rising time of the clock T2 by the setup time Setup or more, and the time when the input data to the element U2 changes next is the rising time of the clock T2. If it is later than the timing by the hold time Hold or more, it is determined that there is no timing error.
[0048]
Conversely, when any one of these conditions is not satisfied, it is determined that there is a timing error. In this way, the timing verification for the strictest condition is performed using the rising edge minimum section 6. In addition, verification is performed in consideration of the signal delay time due to the element S1.
[0049]
In steps S145 to S147, since the timing evaluation unit 84 compares timings between signals to be verified, not only the presence / absence of a timing error but also, for example, a quantitative analysis such as a margin size and an error level. Can be easily obtained.
[0050]
When any one of steps S145 to S147 is completed, the process proceeds to step S148. In step S148, it is determined whether or not an unverified target element remains in the target circuit Y1. If it remains, the process returns to step S141 to search for a new target element. If not, the process in step S14 is terminated, and the entire process of the apparatus 101 is terminated accordingly (FIG. 3).
[0051]
In this way, by repeating the cycle of steps S141 to S148, timing verification is sequentially performed on all of the elements U1 to U6 that require timing verification in the target circuit Y1. In the cycle in which the elements U4, U5, and U1 that have not been given examples in the above are target elements, processing is performed as follows.
[0052]
In the cycle in which the element U4 is the target element, as shown in FIG. 4, the clock T1 is handled as the data transfer side clock and the clock T2 is handled as the data reception side clock. Therefore, step S147 is executed. In the cycle in which the element U5 is the target element, step S143 is executed in the same manner as in the cycle in which the element U3 is the target element, and the clock T1 and the external input data Data2 are compared.
[0053]
Further, when the element U1 is the target element, as shown in FIG. 4, a cycle in which the clock T2 is used as the data transfer side clock and the clock T1 as the data reception side clock, and the clock T3 is the data transfer side clock and the clock T1. Both of the two cycles are executed, which is a cycle that handles the data as a data receiving side clock. The former uses the element U4 as the transfer side element, and the latter uses the element U6 as the transfer side element. In the former, step S147 is executed, and in the latter, step S146 is executed.
[0054]
As described above, static timing can be obtained by using the device 101 even for a target circuit that cannot be verified by the conventional device 150 because a plurality of clocks having a non-multiplication relationship are input. Efficient verification based on this method becomes possible.
[0055]
As shown in FIG. 4, a preferred example is shown in which clock information 1 and 2 are prepared for all six combinations N = 1 to 6 in step S11, but the configuration of the target circuit Y1 is shown. In consideration, for example, the clock information 1 and 2 can be prepared only for the combinations of N = 1 to 3 and 5.
[0056]
In addition, although an example in which the clock information 1 and 2 are directly input from the outside to the synchronization time calculation unit 3 in step S11 has been shown, a storage medium is provided in the apparatus 101, and the clock information 1 is previously stored in the storage medium. , 2 may be stored. In this case, in step S11, a process of reading the clock information 1 and 2 from the storage medium to the synchronization time calculation unit 3 is performed.
[0057]
Further, the apparatus 101 is also configured to temporarily store the circuit connection information 7 and the data input timing information 9 in the storage medium and read them appropriately from the storage medium in accordance with the operation of the static timing verification unit 8. May be configured.
[0058]
<2. Second Embodiment>
FIG. 9 is a block diagram illustrating a configuration of the timing verification apparatus 102 according to the second embodiment. In the following drawings, the same parts as those of the apparatus 101 shown in FIGS. 1 and 6 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0059]
In FIG. 9, 20 is the layout information of the target circuit, 21 is a back annotation device that extracts circuit connection information and wiring delay information from the layout information 20, 22 is circuit connection information of the target circuit extracted by the back annotation device 21, and , 23 are wiring delay information calculated by the back annotation device 21. The layout information 20 is given from the outside.
[0060]
Further, 24 calculates the delay time of the clock wiring, that is, the delay time of the clock propagating through the clock wiring (clock delay) based on the circuit connection information 22 and the wiring delay information 23, and the data transfer side clock and the data reception side clock. The clock delay calculating unit 25 outputs a clock delay separately, 25 is a data transfer side clock delay calculated by the clock delay calculating unit 24, and 26 is a data receiving side clock delay calculated by the clock delay calculating unit 24. It is.
[0061]
Further, 27 is a clock delay adder that adds the data transfer side clock delay 25 to the data transfer side clock information 1 and adds the data reception side clock delay 26 to the data reception side clock information 2, and 28 is the data transfer side clock information 1. The data transfer side clock delay 25 is added to the data transfer side clock delay 25, and the data reception side delay clock information 29 is the data reception side clock information 2 added to the data reception side clock information 2.
[0062]
Hereinafter, the operation of the device 102 will be described using the target circuit Y1 shown in FIG. 2 as an example. The device 102 operates according to the flowchart of FIG. That is, when the apparatus 102 starts operation, first, in step S20, circuit connection information and wiring delay information are extracted. This processing is executed by the back annotation device 21 based on the layout information 20 related to the target circuit Y1 input from the outside.
[0063]
The layout information 20 is created accompanying the layout design of the target circuit Y1. In the apparatus 102, timing verification is performed by adding the layout information 20. That is, the apparatus 102 has an advantage that it is not necessary to create new data in order to perform timing verification.
[0064]
The circuit connection information 22 extracted by the back annotation device 21 corresponds to the circuit connection information 7 supplied to the device 101. That is, the circuit connection information 22 includes information on various elements constituting the target circuit Y1 and their connection. When calculating the wiring delay information 23, the back annotation device 21 first extracts wiring capacitance and wiring resistance from the layout information 20.
[0065]
Next, the process proceeds to step S21, and the clock delay calculation unit 24 calculates the clock delay. That is, in FIG. 2, the delay time of the clock wiring for transmitting the clocks T1 to T3 is calculated. That is, the delay time of the wiring from the input terminal (indicated by white triangles in FIG. 2) of the target circuit Y1 for receiving the clocks T1 to T3 from the outside to the clock terminals T of the elements U1 to U6 is calculated. Is done.
[0066]
The clock delay calculation unit 24 further includes a data transfer side clock delay 25 and a data reception side clock delay 26 for each combination N = 1 to 6 of the data transfer side clock and the data reception side clock as shown in FIG. Created and output. For example, for the combination N = 1 in FIG. 4, as shown in the circuit diagram of FIG. 11, the delay time Delay1 of the wiring of the clock T1 is output as the data transfer side clock delay 25, and the delay of the wiring of the clock T2 The time Delay 2 is output as the data receiving side clock delay 26.
[0067]
Next, the process proceeds to step S22, and the data transfer side clock information 1 and the data reception side clock information 2 are input to the clock delay adding unit 27 from the outside. This step S22 may be executed prior to the next step S23, and the context with steps S20 to S22 may be arbitrary.
[0068]
Next, in step S23, clock delay addition processing by the clock delay addition unit 27 is performed. That is, the data transfer side clock delay 25 is added to the data transfer side clock information 1 and output as clock information 28 with data transfer side delay, and the data reception side clock delay 26 is added to the data reception side clock information 2 to receive data. Output as clock information 29 with side delay.
[0069]
In the following steps S24 to S26, processing in which the clock information 1 and 2 are replaced with the delayed clock information 28 and 29 in steps S13 to S14 in the apparatus 101 of the first embodiment is performed. Accordingly, in the process of step S25, for example, for the combination N = 1 in FIG. 4, the data transfer side clock rise time U1rise_time with delay given by the equation (9): {U1rise_time = T1rise_time + Delay1} is obtained in step S13. Used instead of the data transfer side clock rise time T1rise_time.
[0070]
Also, the data reception side clock rise time U2rise_time with delay given by Equation (10): {U2rise_time = T2rise_time + Delay2} is used instead of the data reception side clock rise time T2rise_time in step S13. That is, in Equations (5) to (8), the rising edge minimum interval Trise is calculated by replacing the rising times T1rise_time and T2rise_time with the delaying rising times U1rise_time and U2rise_time.
[0071]
As shown in the timing chart of FIG. 12, the rising times U1rise_time and U2rise_time with delay are obtained by adding delay times Delay1 and Delay2 of the clock wiring to the rising times T1rise_time and T2rise_time of the clocks T1 and T2 input to the input terminal of the target circuit Y1, respectively. Each corresponds to the added value. That is, the rise times U1rise_time and U2rise_time correspond to the rise times of the clocks T1 and T2 that reach the clock terminals T of the elements U1 and U2.
[0072]
Moreover, in step S26, the cycle of step S141-S148 is performed similarly to FIG. That is, in steps S145, S146, and S147, timing verification is performed in consideration of the clock wiring delay based on the clock information 1 and 2 and the wiring delay information 23.
[0073]
The relationship between the internal configuration of the static timing verification unit 8 that executes step S26 and various types of information is shown in the block diagram of FIG. That is, the internal configuration of the static timing verification unit 8 is the same as that of the static timing verification unit 8 (FIG. 6) of the apparatus 101 according to the first embodiment. The point that the wiring delay information 23 is supplied to the timing evaluation unit 84 is different from the static timing verification unit 8 of the apparatus 101.
[0074]
For example, in the cycle in which the element U2 is selected as the target element in step S141, the process of step S147 is executed. At this time, as shown in the timing chart of FIG. 14, the clock T1 input to the clock terminal T of the element U1 is input to the clock terminal T of the element U2 when the rising edge minimum interval Trise has passed after rising. Timing verification is performed for the most severe condition that the clock T2 rises.
[0075]
That is, the output data is output to the output terminal Q of the element U1 based on the rising timing of the clock T1 supplied by the data transfer side clock information 1, the function of the element U1 supplied by the circuit connection information 22, and the wiring delay information 23. The time of appearance is calculated. Further, based on the function of the element S1 supplied by the circuit connection information 22, the signal delay time Delay3 based on the signal delay time based on the element S1 and the wiring delay information 23 is taken into account, and then the data input terminal D of the element U2 is used. The time when the input data reaches is calculated.
[0076]
Then, it is determined whether or not the clock T2 that rises after the rising edge minimum interval Tries from the rising timing of the clock T1 and the input data that reaches the element U2 satisfy the conditions relating to the setup time Setup and the hold time Hold, for example.
[0077]
As described above, by using the device 102, the timing verification that considers the delay time of the clock wiring is performed for the target circuit to which a plurality of clocks having a non-multiplication relationship are input. It is possible to execute efficiently based on this.
[0078]
Instead of inputting clock information 1 and 2, data input timing information 9 and layout information 20 directly from the outside, a storage medium is provided, and this information is stored in advance in this storage medium. In addition, the apparatus 102 may be configured such that each part of the apparatus reads out necessary information from the storage medium as the apparatus operates.
[0079]
<3. Embodiment 3>
In the first and second embodiments, the operation has been described by taking the target circuit having an element that operates at the rising edge of the clock as an example. However, a circuit having an element that operates at a falling edge or a circuit having a so-called level sensitive element that operates at a clock level can also be used as a target circuit. In this embodiment, a characteristic timing verification apparatus that allows the number of data transfer cycles to be set from the outside will be described, and an operation example that particularly targets a circuit having a level-sensitive element will be shown.
[0080]
FIG. 15 is a circuit diagram showing an example of a target circuit used for explaining the operation of the timing verification apparatus of this embodiment. This target circuit Y2 has a structure in which, in the target circuit Y1 shown in FIG. 2, the elements U1 to U6 as flip-flops operating at the clock edge are replaced with latches operating at the clock level.
[0081]
That is, the elements U1 to U6 included in the target circuit Y2 receive the data signal input to the data input terminal D at the falling edge of the clock input to the clock terminal G, that is, the transition from the normal level to the active level. Is a latch that holds and outputs to the output terminal Q over a period when the signal is at the low level (active level). During the period when the clock is at a high level (normal level), the data signal input to the data input terminal D is output to the output terminal Q as it is.
[0082]
Assume that the clocks T1 to T3 input to the target circuit Y2 are the same as the clocks T1 to T3 input to the target circuit Y1. Therefore, the contents shown in FIG. 4 are also valid as they are for the clocks T1 to T3 of the target circuit Y2.
[0083]
FIG. 16 is a block diagram showing the configuration of the timing verification apparatus 103 of this embodiment. In FIG. 16, 30 is a data transfer cycle inputted from the outside, 31 is a minimum falling edge interval based on data transfer side clock information 1, data reception side clock information 2, synchronization time 4, and the number of data through latch stages 30 The falling edge minimum interval calculation unit 32 calculates the falling edge minimum interval calculated by the falling edge minimum interval calculation unit 31.
[0084]
Hereinafter, the operation of the device 103 will be described by taking the target circuit Y2 shown in FIG. 15 as an example. The device 103 operates according to the flowchart of FIG. That is, when the apparatus 103 starts operation, first, the processes of steps S31 to S32 are executed. These processes are the same as the processes in steps S11 to S12 in the apparatus 101.
[0085]
Thereafter, the process proceeds to step S33, and the falling edge minimum section calculation unit 31 calculates the falling edge minimum section. This calculation is performed for each of the combinations N = 1, 3, 4, 6 in FIG. 4 as in step S32. Hereinafter, a calculation procedure will be described for an example of a combination of clocks T1 and T2 (N = 1).
[0086]
First, the next synchronization time Syn2 after the synchronization time Syn1 is calculated according to the above-described equation (2). Subsequently, the data transfer side clock falling time T1fall_time is defined by Expression (11): {T1fall_time = Cyc1 × m}. Similarly, the data receiving side clock falling time T2fall_time is defined by Expression (12): {T2fall_time = Cyc2 × n}. Here, the variables m and n are both natural numbers.
[0087]
Subsequently, Formula (13): {T1fall_time + (data transfer cycle) <T2fall_time}, Formula (14): {Syn1 ≦ T1fall_time <Syn2}, and Formula (15): {Syn1 <T2fall_time ≦ Syn2} 3 The minimum value of the difference between T2fall_time and T1fall_time is calculated as the falling edge minimum section Tfall within a range that satisfies all the street conditions.
[0088]
That is, the minimum falling edge interval Tfall is calculated based on Equation (16): {Tfall = MIN (T2fall_time−T1fall_time)} for the minimum values for all natural numbers m and n satisfying Equations (13) to (15). It is obtained by doing. The “data transfer cycle” used in Equation (13) is a value input from the outside as the data transfer cycle 30.
[0089]
As a result, when “zero” is input as the data transfer cycle, as shown in the timing chart of FIG. 18, the minimum falling edge period Tfall starts from the falling time of the clock T1 and the clock T2 thereafter. It is given as the minimum value of the time interval until the fall time. On the other hand, when “1” is input as the data transfer cycle, as shown in the timing chart of FIG. 19, the minimum falling edge interval Tfall starts from the falling time of the clock T1 and the subsequent rising edge of the clock T2. This is given as a value obtained by adding one cycle of the clock T2 to the minimum value of the time interval until the falling time.
[0090]
Next, the process proceeds to step S34. In step S34, the cycle of steps S141 to S148 is executed as in FIG. For example, in the cycle in which the element U2 is selected as the target element in step S141, the process of step S147 is executed. At this time, as shown in the timing chart of FIG. 18 or FIG. 19, the timing verification is performed for the most severe condition that the clock T2 falls after the falling edge minimum section Tfall after the clock T1 falls. Is done.
[0091]
That is, the time when the output data appears at the output terminal Q of the element U1 is calculated based on the falling time of the clock T1 supplied by the data transfer side clock information 1 and the function of the element U1 supplied by the circuit connection information 7. The Further, based on the function of the element S1 supplied by the circuit connection information 7, the time when the input data reaches the data input terminal D of the element U2 is calculated in consideration of the signal delay time Delay by the element S1.
[0092]
Then, it is determined whether or not the clock T2 falling after the falling edge minimum interval Tfall from the falling timing of the clock T1 and the input data reaching the element U2 satisfy, for example, conditions relating to the setup time Setup and hold time Hold. Is done. As illustrated in FIGS. 18 and 19, the value of the data transfer cycle 30 is appropriately determined in consideration of the delay time of the signal from the output terminal Q of the element U1 to the data input terminal D of the element U2.
[0093]
As described above, by using the device 103, timing verification considering a data transfer cycle is performed on a target circuit to which a plurality of clocks having a non-multiplication relationship are input based on a static timing method. It is possible to execute efficiently. As exemplified in this embodiment, the devices 101 to 103 can also be used for a target circuit having a level-sensitive element with respect to a clock.
[0094]
Instead of inputting clock information 1, 2, circuit connection information 7, data input timing information 9, data transfer cycle 30 and the like directly from the outside, a storage medium is provided, and these are stored in advance in the storage medium. The apparatus 102 may be configured such that each part of the apparatus reads out necessary information from the storage medium as the apparatus operates.
[0095]
<4. Embodiment 4>
FIG. 20 is a block diagram illustrating a configuration of the timing verification apparatus 104 according to the fourth embodiment. In FIG. 20, reference numeral 41 denotes an operation based on circuit connection information 7 input from the outside, and the target circuit operates at two clock cycles different from those of a single clock operation logic circuit block (hereinafter referred to as “first type block”). A logic circuit block dividing unit that divides the logic circuit block into two logic circuit blocks (hereinafter abbreviated as “second type block”), and 42 is connection information (hereinafter referred to as “the first type block” divided by the logic circuit block dividing unit 41). Reference numeral 43 is abbreviated as “first type block connection information”, and 43 is information relating to the second type block divided by the logic circuit block dividing unit 41 (hereinafter abbreviated as “second type block connection information”).
[0096]
Reference numeral 61 denotes information related to the rising timing, cycle, etc. of the clock input to the target circuit, that is, clock information. This clock information 61 is given from the outside.
[0097]
Further, reference numeral 62 denotes a static timing verification unit that performs static timing verification by a conventionally known technique with reference to the first type block connection information 42, the clock information 61, and the data input timing information 9 for the first type block. , 45 is a result of timing verification by the static timing verification unit 62, and 46 is an input test pattern for performing dynamic timing verification for the second type block based on the static timing verification result 45 and the clock information 1. A test pattern generation unit 47 and an input test pattern 47 generated by the test pattern generation unit 46.
[0098]
48 is a dynamic timing verification unit that performs dynamic timing verification based on the input test pattern 47 for the second type block, 49 is a dynamic timing verification result obtained by the dynamic timing verification unit 48, and 50 is A data input timing extraction unit that extracts information on the input timing of the data signal to be input to the first type block from the dynamic timing verification result 49, and 51 is a data input timing extracted by the data input timing extraction unit 50 is there.
[0099]
The dynamic timing verification result 49 is also input to the test pattern generation unit 46. Then, the test pattern generation unit 46 selectively refers to either the static timing verification result 45 or the dynamic timing verification result 49. The data input timing 51 is also input to the static timing verification unit 62. Then, the static timing verification unit 62 selectively refers to either the data input timing information 9 or the data input timing 51.
[0100]
FIG. 21 is a circuit diagram illustrating an example of a target circuit to be verified by the device 104. Six clocks T11 to T16 whose external cycles are not necessarily the same and external input data Data11 are inputted to the target circuit Y3 from the outside through input terminals (indicated by white triangles in the figure). The target circuit Y3 is configured to execute a predetermined logical operation based on these signals and output the output signals Out11 and Out12 to the outside through output terminals (indicated by white triangles in the figure). .
[0101]
The seven elements U10 to U16 included in the target circuit Y1 are the data signals input to the data input terminal D in synchronization with the rising edge of the clock input to the clock terminal T, that is, the transition from the normal level to the active level. Is held until the next rising edge of the clock and continues to be output to the output terminal Q. The elements S101 to S105 are arbitrary elements or combinations of elements that cause a delay in signal propagation. The element S106 is a NAND element.
[0102]
Hereinafter, the operation of the device 104 will be described using the target circuit Y3 as an example. The device 104 operates according to the flowchart of FIG. That is, when the device 104 starts operation, first, in step S41, the circuit connection information 7 is input from the outside to the logic circuit block dividing unit 41, and the clock information 61 is sent to the static timing verification unit 62 and the test pattern generation unit 46. Is entered.
[0103]
The circuit connection information 7 and the clock information 61 are given manually from the outside or using an external input device. Further, instead of directly inputting these pieces of information to the logic circuit block division unit 41 or the static timing verification unit 62, a storage medium may be provided in the device 104 and stored in this storage medium. Thus, the static timing verification unit 62 and the like may read out a necessary portion of information from the storage medium as necessary while the process proceeds.
[0104]
Next, in step S42, the logic circuit block dividing unit 41 performs division into logic circuit blocks. That is, the target circuit Y3 is divided into a first type block and a second type block. As shown in FIG. 21, the target circuit Y3 is divided into blocks BL1 to BL9. The blocks BL1, BL4, and BL9 are blocks that operate only with the clocks T11, T14, and T16, respectively, and all belong to the first type block. The blocks BL2, BL3, BL5 to BL8 are all blocks that operate with two clocks and belong to the second type block.
[0105]
By extracting a part relating to each of the blocks BL1, BL4, BL9 belonging to the first type block from the circuit connection information 7, the first type block connection information 42 is obtained. Similarly, the second type block connection information 43 is obtained by extracting the portion relating to each of the blocks BL2, BL3, BL5 to BL8 belonging to the second type block.
[0106]
Next, the process proceeds to step S43, and the static timing verification unit 62 performs static timing for the block BL1 located on the most input side among the blocks BL1, BL4, and BL9 classified as the first type block. Verification is performed. Since only one clock T11 is input to the block BL1, the static timing verification of the block BL1, that is, the static timing verification for the elements U10 and U11, is conventionally known for a target circuit operating with a single clock. It is done by the method.
[0107]
At this time, based on the first type block connection information 42, the operation of the elements U10 and U11, the characteristics such as the setup time Setup and the hold time Hold, and the delay time DelayA by the element S101 are grasped. Further, the timing of the external input data Data 11 is grasped based on the data input timing information 9, and the timing of the clock T 11 is grasped based on the clock information 61. The result of timing verification is output as a static timing verification result 45.
[0108]
Next, in step S44, it is determined whether or not there is a block on the output side. Since the block BL2 that is the second type block exists on the output side of the block BL1, the determination result is “Yes”, and the process proceeds to step S46. In step S46, an input test pattern for executing dynamic timing verification for the block BL2 is created based on the static timing verification result 45 for the block BL1. That is, the test pattern generation unit 46 generates two input signal patterns to the block BL2, that is, a data signal input to the data input terminal D of the element U11 and a clock signal pattern input to the clock terminal T. .
[0109]
FIG. 23 is a timing chart showing an example of an input test pattern of the block BL2 created by the test pattern generation unit 46. As shown in FIG. 23, the data signal U11 / D input to the data input terminal D of the element U11 changes every time the clock signal T11 input to the clock terminal T rises twice, and only the delay time DelayA. There is a delay.
[0110]
Next, the process proceeds to step S47, and the dynamic timing verification unit 48 performs dynamic timing verification on the block BL2. Dynamic timing verification performs timing verification using logic simulation, and is a conventionally well-known method. The dynamic timing verification unit 48 grasps the types and connection states of the elements U11, U12, S102 constituting the block BL2 based on the second type block connection information 43, and when the input test pattern 47 is input. Simulate the behavior of each element.
[0111]
Then, based on the result of the simulation, it is determined whether or not conditions such as a setup time Setup and a hold time Hold are satisfied. Therefore, verification is performed in consideration of the delay time DelayB by the element S102. The verification result is output as a dynamic timing verification result 49.
[0112]
Next, in step S48, it is determined whether or not the first type block is connected to the output side. Since the block BL3 which is the second type block is connected to the output side of the block BL2, the result of the determination is “No”, and the process returns to step S46. In step S46, an input test pattern for executing the dynamic timing verification for the block BL3 is created based on the dynamic timing verification result 49 for the block BL2.
[0113]
Thereafter, the process proceeds to step S47, and the dynamic timing verification for the block BL3 is executed by the dynamic timing verification unit 48 based on the newly created input test pattern 47.
[0114]
Since the block BL4 which is the first type block is connected to the output side of the block BL3, it is determined as “Yes” in the subsequent step S48. Therefore, the process proceeds to step S49. In step S49, the data input timing of the block BL4, that is, the input timing of data input to the data input terminal D of the element U14 is extracted from the dynamic timing verification result 49 for the block BL3. This process is performed by the data input timing extraction unit 50, and the obtained data is output as the data input timing 51.
[0115]
As illustrated in the timing chart of FIG. 24, the extraction by the data input timing extraction unit 50 is, for example, the time when the data input to the data input terminal D of the element U12 changes and the clock T12 input to the clock terminal T. This is accomplished by extracting the four types of timings at which the time difference from the time at which the change occurs is minimized. The setup (rise), setup (fall), hold (rise), and hold (fall) shown in FIG. 24 are the minimum time differences in these four types of timing.
[0116]
Among these, the time differences indicated in parentheses as “rise” and “fall” are time differences when the input data rises and falls, respectively. Also, the time differences marked “setup” and “hold” refer to the setup time Setup and hold time Hold, respectively.
[0117]
Next, the process proceeds to step S43, and the static timing verification unit 62 performs static timing verification on the block BL4. At this time, the data input timing information 9 is not referred to and the data input timing 51 is referred to instead.
[0118]
Since there is no more block on the output side of the block BL4, it is determined as “No” in the subsequent step S44. As a result, the process proceeds to step S45. In step S45, it is determined whether or not an unverified block exists in the target circuit Y3. Since the blocks including the block BL5 are left unverified, the determination is “Yes”, and the process proceeds to step S43.
[0119]
With the above processing, timing verification along the series of blocks BL1, BL2, BL3, BL4 is completed. By repeating the same processing, the timing verification of the series of blocks BL1, BL5, BL6, BL4 and the series of blocks BL1, BL7, BL8, BL9 is performed. When all these verifications are completed, a determination of “No” is obtained for the first time in step S45, and all the processes are completed.
[0120]
In the target circuit Y3, only the second type block exists between the first type block and the first type block in any series. For example, in the series of blocks BL1, BL2, BL3, BL4, It is possible to perform verification using the device 104 even for a target circuit in which a first type block (assumed to be a block BL10) exists between two types of blocks BL2 and BL3.
[0121]
As described above, the device 104 enables timing verification for a target circuit to which a plurality of clocks having the same period are input by appropriately using a static timing method and a dynamic timing method for each circuit block. .
[0122]
The plurality of clocks input to the target circuit Y3 may be clocks not only having different periods but also independent and not synchronized with each other. In any of these cases, the device 104 performs verification of the target circuit in exactly the same manner.
[0123]
<5. Modification>
The devices 101 to 104 of the above-described embodiments are not limited to the forms exemplified in the respective embodiments, and a circuit that operates in synchronization with either rising or falling of the clock can be a verification target. In other words, the target circuit generally only needs to operate in synchronization with the change time from the normal level of each clock to the active level.
[0124]
Furthermore, as exemplified in the third embodiment, a level-sensitive circuit that operates at the clock level can be a verification target. In the third embodiment, an example in which the low level is the active level is shown, but it goes without saying that the active level may be the high level.
[0125]
【The invention's effect】
In the device according to the first aspect of the invention, a pair of clocks having a non-multiplier relationship are respectively input, and the data receiving side element among the elements having the relationship between the data transfer side element and the data receiving side element is input. Timing verification between the data signal and the clock signal is performed. Since the verification is performed under the strictest condition that the timing when the pair of clocks changes is in the minimum interval, the purpose of the verification is achieved. Moreover, this verification method belongs to the static timing method. That is, the timing verification of the target circuit to which the clock having a non-multiplication relationship is input is performed without impairing the high speed of the static timing.
[0126]
In the apparatus of the second invention, a target element search unit, a path search unit, and a clock determination unit are provided, and the timing evaluation unit is configured to multiply or not multiply the pair of clocks according to the determination of the clock determination unit. Select and execute a static timing method adapted to the relationship. For this reason, in the target circuit to which a plurality of clocks are input, the data transfer side element and the data receiving side, regardless of whether the relationship between the clocks is double or non-multiply or includes both Timing verification is comprehensively performed by the static timing verification method for all data receiving side elements having the element relationship.
[0127]
In the apparatus of the third invention, when the path search means cannot find the data transfer side element, that is, without passing through the data transfer side element operating in synchronization with the clock, the data signal is input from the outside to the target element. In this case, the timing verification of the target element is performed with reference to the data input timing information. Therefore, in a target circuit to which a plurality of clocks are input, regardless of whether the relationship between clocks is double or non-multiply, or includes both relationships, all elements included in the target circuit On the other hand, exhaustive timing verification is performed by a static timing verification method.
[0128]
In the device according to the fourth aspect of the invention, since the delay time of the clock wiring is reflected in the calculation of the minimum interval, the delay time of the clock wiring is compared with the target circuit to which a plurality of clocks having a non-multiplication relationship are input. The timing verification considering the above is executed at high speed based on the static timing method.
[0129]
In the apparatus of the fifth invention, since the back annotation means is provided, layout information created in association with the layout design of the target circuit can be used, and circuit connection information and wiring delay time information are separately prepared. There is no need. That is, labor and time necessary for performing timing verification are saved.
[0130]
In the device according to the sixth aspect of the invention, the data transfer cycle appropriately set from the outside is added to the minimum interval, so that the data transfer cycle is applied to the target circuit to which a plurality of clocks having a non-multiplication relationship are input. The timing verification considering the above is efficiently performed based on the static timing method.
[0131]
In the seventh aspect of the invention, since the search for the minimum interval is performed in the period corresponding to the least common multiple of both cycles for the clocks having a non-multiplication relationship, the efficiency is good and the search is omitted. Absent.
[0132]
In the apparatus according to the eighth aspect, the minimum interval calculation means calculates the minimum interval for all combinations of clocks that are not in frequency division with each other among the plurality of clocks input to the target circuit. Therefore, it is not necessary to select the combination that requires the calculation of the minimum interval with reference to the circuit connection information. That is, the processing efficiency is increased.
[Brief description of the drawings]
FIG. 1 is a block diagram of an apparatus according to a first embodiment.
FIG. 2 is a block diagram illustrating an example of a target circuit.
FIG. 3 is a flowchart showing the operation of the apparatus according to the first embodiment.
FIG. 4 is an explanatory diagram showing an example of clock information.
FIG. 5 is a timing chart for explaining the operation of the apparatus according to the first embodiment.
FIG. 6 is a block diagram of a static timing verification unit according to the first embodiment.
FIG. 7 is a flowchart of a static timing verification unit according to the first embodiment.
FIG. 8 is a timing chart for explaining the operation of the apparatus according to the first embodiment.
FIG. 9 is a block diagram of an apparatus according to a second embodiment.
FIG. 10 is a flowchart showing the operation of the apparatus according to the second embodiment.
FIG. 11 is a block diagram showing a part of a target circuit.
FIG. 12 is a timing chart showing the operation of the apparatus according to the second embodiment.
FIG. 13 is a block diagram of a static timing verification unit according to the first embodiment.
FIG. 14 is a timing chart showing the operation of the apparatus according to the second embodiment.
FIG. 15 is a block diagram illustrating another example of a target circuit.
FIG. 16 is a block diagram of an apparatus according to the third embodiment.
FIG. 17 is a flowchart showing the operation of the apparatus according to the third embodiment.
FIG. 18 is a timing chart showing the operation of the apparatus according to the third embodiment.
FIG. 19 is a timing chart showing the operation of the apparatus according to the third embodiment.
FIG. 20 is a block diagram of an apparatus according to the fourth embodiment.
FIG. 21 is a block diagram showing still another example of the target circuit.
FIG. 22 is a flowchart showing the operation of the apparatus according to the fourth embodiment.
FIG. 23 is a timing chart showing the operation of the apparatus according to the fourth embodiment.
FIG. 24 is a timing chart showing the operation of the apparatus according to the fourth embodiment.
FIG. 25 is a block diagram of a conventional apparatus.
FIG. 26 is a timing chart showing the operation of the conventional apparatus.
[Explanation of symbols]
1 data transfer side clock information (clock information), 2 data reception side clock information (clock information), 5 rising edge minimum interval calculation unit (minimum interval calculation means), 7 circuit connection information, 9 data input timing information, 20 layout information , 21 Back annotation device (back annotation means), 23 Wiring delay information, 24 Clock delay calculation section (clock delay calculation means), 27 Clock delay addition section (clock delay addition means), 30 Data transfer cycle (data transfer cycle information) , 41 logic circuit block division unit (block division unit), 42 first type block connection information, 43 second type block connection information, 46 test pattern generation unit (test pattern generation unit), 48 dynamic timing verification unit (dynamic Timing verification means), 50 Data input timing extraction unit (data input timing extraction unit), 62 Static timing verification unit (static timing verification unit), 81 Target element search unit (target element search unit), 82 Path search unit (path search unit), 83 Clock determination unit (clock determination unit), 84 timing evaluation unit (timing evaluation unit), Trise rising edge minimum section (minimum section), Tfall falling edge minimum section (minimum section).

Claims (8)

In a timing verification device that performs timing verification of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks,
Based on the clock information defining the plurality of clocks, the time at which the time from one level to the other level does not coincide with each other with respect to the clocks that are not multiplied by each other among the plurality of clocks is the most in the range. A minimum section calculating means for calculating a close time section, that is, a minimum section;
A pair of clocks in a non-multiplier relationship are respectively input, a pair of the plurality of elements in a relationship between a data transfer side element and a data reception side element, and a data signal path between them, For the circuit portion including the circuit connection information defining the target circuit, and input to the data receiving side element on the condition that the change times of the pair of clocks are in the relationship of the minimum interval Timing evaluation means for performing timing verification between a clock to be performed and the data signal;
A timing verification apparatus comprising: In a timing verification device that performs timing verification of a target circuit including a plurality of elements that operate in synchronization with a plurality of clocks,
Based on the clock information defining the plurality of clocks, the time at which the time from one level to the other level does not coincide with each other with respect to the clocks that are not multiplied by each other among the plurality of clocks is the most in the range. A minimum section calculating means for calculating a close time section, that is, a minimum section;
Based on circuit connection information defining the target circuit, target element search means for sequentially selecting one target element from the plurality of elements,
The target element selected by the target element search means is a data receiving side element, and the data transfer side element corresponding to the target element is searched from the plurality of elements based on the circuit connection information; and ,
Clock determination means for determining whether a relationship between a pair of clocks respectively input to the data transfer side element and the data reception side element is a doubled frequency or a non-multiplied frequency based on the clock information; ,
For the circuit portion including the data transfer side element, the data reception side element, and the path of the data signal between them, the circuit connection information is referred to, and when the result of the determination is a frequency multiplication, With reference to clock information, when the result of the determination is non-multiplication, the change time of the pair of clocks is input to the data receiving side element on condition that the relationship is in the minimum interval. Timing evaluation means for performing timing verification between a clock and the data signal;
A timing verification apparatus comprising: The timing verification device according to claim 2,
The timing evaluation unit further includes a circuit part including the target element and a path of an external input data signal input to the target element when the path search unit cannot find the data transfer side element. The timing between the clock input to the target device and the external input data signal based on the data input timing information defining the external input data signal and the clock information while referring to the circuit connection information The timing verification apparatus characterized by performing verification of this. In the timing verification device according to any one of claims 1 to 3,
Clock delay calculation for individually calculating the delay time of a plurality of clock wirings for transmitting a clock to the plurality of elements based on the wiring delay information defining the signal delay time of the wiring of the target circuit and the circuit connection information Means,
A clock delay adding means for creating clock information with delay by adding the delay time to the timing specified by the clock information for the clock input to the element for each of the plurality of elements;
Further comprising
The timing verification apparatus according to claim 1, wherein the minimum interval calculation means calculates the minimum interval by referring to the clock information with delay instead of the clock information. The timing verification device according to claim 4,
Back annotation means for extracting the circuit connection information and the wiring delay time from layout information defining the layout of the target circuit,
A timing verification device further comprising: In the timing verification device according to any one of claims 1 to 3,
The minimum interval calculation means adds a data transfer cycle defined in data transfer cycle information to the calculated minimum interval,
The timing evaluation device, wherein the timing evaluation means refers to the value added with the data transfer cycle as the minimum interval. In the timing verification device according to any one of claims 1 to 6,
The timing verification apparatus according to claim 1, wherein the minimum interval calculation means searches for the minimum interval in a period corresponding to a least common multiple of both periods with respect to a clock having a non-multiplication relationship. In the timing verification device according to any one of claims 1 to 7,
The timing verification apparatus according to claim 1, wherein the minimum interval calculation means calculates the minimum interval for all combinations of clocks having a non-multiplication relationship among the plurality of clocks.

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