JP2003008007A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can easily contain a nonvolatile memory element for promoting the reductions of the channel leakage and size of the device and the improvement of the drivability of the device, by developing a manufacturing method by which the channel surface concentration profile of a buried channel MOSFET can be optimized. SOLUTION: A semiconductor integrated circuit device which is excellent in performance is constituted by building the buried channel MOSFET optimized in channel surface concentration profile by a manufacturing method using a new gate oxide film forming method and, at the same time, mounting a nonvolatile memory on the circuit device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device having a MOS structure and a method of manufacturing the same.

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage regulator, a switching regulator, a voltage detector, etc. used for power supply voltage management of portable equipment, and a nonvolatile memory etc. for retaining information of portable equipment etc. even when there is no power supply. The present invention relates to a semiconductor device that constitutes a semiconductor integrated circuit and a manufacturing method thereof.

[0003]

2. Description of the Related Art Conventionally, much research and development has been conducted on high driving, low power consumption, low parasitic capacitance, and low voltage of semiconductor elements. Higher drive of MOSFET is
This is done by reducing the width of the gate electrode and reducing the source / drain parasitic resistance. The reduction in the width of the gate electrode means the reduction in the length of the channel region thereunder, that is, the channel length, which reduces the time required for carriers to pass through the channel region. And, as a result, higher driving is brought about. However, this also causes another problem (short channel effect). The most important of these is the problem of leakage current.

In a conventional structure in which a channel region doped with an impurity having an opposite polarity is sandwiched between impurity regions of a source and a drain having a sufficiently high impurity concentration, the source is reduced as the channel region is reduced. The voltage applied to the drain increases the electric field near the boundary between the channel region and the impurity region. As a result, MO
The operation of the SFET becomes extremely unstable.

A conventional MOSFET structure proposed for the purpose of solving such a problem is an LDD (Lightly-Doped-Drain) structure using a spacer. This has a typical structure shown in FIG. 9 (D). In FIG. 9D, a region 203 having a high impurity concentration
The region 213, which is provided shallower than
Called DD. By providing such a region, it is possible to reduce the electric field near the boundary between the channel region and the impurity region and stabilize the operation of the device.
The LDD is usually formed as shown in FIGS. FIG. 9 shows an example of NMOS, but the same is formed even if it is PMOS. First, an oxide film and a conductive film are formed on the P-type semiconductor substrate 1, and these are etched to form a gate insulating film 202 and a gate electrode 204 as shown in FIG. 9A. Then, when the gate electrode 204 is used as a mask, a region 213 having a relatively low impurity concentration (represented by N- in the symbol) is formed in a self-aligned manner, for example, by an ion implantation method or the like. There is also.

Here, using the gate electrode 204 as a mask, in self-alignment (self-alignment), a region 213 having a low impurity concentration is ion-implanted with an opposite conductivity type ion to the lower side of the region 213 having a low impurity concentration. A pocket implantation region 223 having a low impurity concentration is formed.

Next, an insulating film 205 such as NSG or PSG is formed on this. Then, this insulating film 205
Is removed by an anisotropic etching method such as a bias plasma etch, but as a result of the anisotropic etching,
The insulating film 205 is not etched on the side surface of the gate electrode and remains in a shape as shown in FIG. This residue is called spacer 206. Then, using this spacer 206 as a mask, a region 203 having a high impurity concentration (represented by N + in the symbol) is formed in a self-aligning manner. The N + type impurity region is used as the source and drain of the MOSFET.

Besides such an LDD structure, an offset LDD structure using a mask is known. This conventional technique will be described below. In this conventional technique, a complementary MOSFET formed on a single crystal semiconductor substrate
The case where it is used for a device (CMOS) is shown. First, FIG.
As shown in (A), an N-type well 207, a field insulator 208, an N − -type impurity region 211, and an N + are formed on a P-type semiconductor substrate 201 by using a conventional integrated circuit manufacturing method.
Type impurity region 212, P + type impurity region 214, P− type impurity region 215, pocket region (for NMOS) 224
And 225 (for PMOS) and the same as the gate electrode 216 (for NMOS) of N-type polycrystalline silicon doped with phosphorus.
17 (for PMOS) is formed.

The detailed manufacturing method is as follows.
First, BF2 + ions are implanted into a P-type silicon wafer having an impurity concentration of about 1E15 / cm3, so-called LO
The channel stopper 210 and the field insulator 208 are formed by the COS method. Further, phosphorus ions are implanted into this and annealed at 1000 ° C. for 3 to 10 hours,
Diffusion and redistribution of phosphorus ions, impurity concentration 1E16c
An N-type well 207 of about m-3 is formed.

After that, a thickness of 20 to 1 is obtained by a thermal oxidation method.
A gate insulating film (silicon oxide) having a thickness of 00 nm and a polycrystalline silicon film having a thickness of 500 nm and a phosphorus concentration of 1E21 cm −3 are formed by a low pressure CVD method, and this is patterned,
The portions 216 and 217 to be the gate electrodes are formed, and the oxide film 33 is formed on the upper sidewalls of the portions 216 and 217 to be the gate electrodes by thermal oxidation or the like.

Then, an N-type impurity region 21 having an impurity concentration of 1E18 cm -3 is formed by ion implantation using a portion to be a gate electrode and another mask if necessary.
1 and a pocket region 224 having an impurity concentration of about 1E17 cm −3 is formed if necessary, and the impurity concentration of 1E18c is further added.
An m −3 P− type impurity region 214 and, if necessary, a pocket region 225 having an impurity concentration of about 1E17 cm −3 are formed. Thus, FIG. 113A is obtained.

Next, as shown in FIG. 10B, the resist mask 234 is used again to perform ion implantation, and the N + type impurity region 212 and the resist mask 235 are used to form P.
Portion 2 where the + type impurity region 214 is to be the gate electrode
16 and 217 spaced apart. The impurity concentration of each impurity region is about 1E21 cm −3.

Here, N + type impurity regions 212 and P
+ Type impurity region 214 and a portion 2 to be a gate electrode
The distance between 16 and 217 can be set wide, unlike the case of the LDD structure using the spacer described above. Therefore, when the drain applied voltage is 7V, 0.5 to 1.0um
In case of 10V, 0.7-2.0um, 36V
In the case of, it was set to about 2.0 to 5.0 um.

Finally, a phosphorous glass layer 220 is formed as an interlayer insulator as in the case of manufacturing a general integrated circuit. For forming the phosphor glass layer 220, for example, a reduced pressure CV is used.
The method D may be used. As material gas, monosilane S
Using iH4, oxygen O2 and phosphine PH3, 450 ℃
It is obtained by reacting with.

After that, a hole for forming an electrode is opened in the interlayer insulating film to form an aluminum electrode 221. Thus, FIG.
The complementary MOS device as shown in (C) is completed.

[0016]

However, the problems of the conventional LDD structure using the N-type gate electrode and the spacer are that the leakage current increases by reducing the gate length and the channel surface in the buried channel structure. It's a leak issue. Especially in the case of integrated circuits for power supply voltage control,
The tendency is remarkable in the buried channel (here, P-type MOSFET).

Even if the operating speed is improved by shortening the channel, if the leak current is large, the effect of shortening the channel becomes meaningless. In order to reduce the leakage current, a method of suppressing the expansion of the depletion layer between the drain and channel regions by using an impurity implantation technique such as pocket implanter or punch through implanter is often adopted. When the voltage is large (10V or more),
In the case of a buried channel (here, a P-type MOSFET) with a large amount of channel surface leakage, it is expected to reach its limit when the length of the gate electrode is about 2.0 μm or less.

Also, in the case of the offset type LDD structure using the conventional resist mask, the problem is that the leak current is increased by reducing the gate length and the channel surface leak in the buried channel structure. Particularly in the case of the integrated circuit for controlling the power supply voltage, the tendency is remarkable in the buried channel (here, P-type MOSFET).

Even if the operating speed is improved by shortening the channel, if the leak current is large and the resistance of the gate electrode is large, the effect of shortening the channel becomes meaningless. In order to reduce the leakage current, a method of suppressing the expansion of the depletion layer between the drain and channel regions by using an impurity implantation technique such as pocket implanter or punch through implanter is often adopted. When the voltage is high (10 V or more), it is expected that the buried channel (P-type MOSFET in this case) having a large amount of channel surface leakage will reach its limit when the length of the gate electrode is about 1.0 μm or less. .

The buried channel will be briefly described. In the case of a P-type MOSFET, the N-type polysilicon that has been conventionally used as a gate electrode has a very large threshold voltage in the negative direction (about -1 V) due to the difference in work function from that of the N-type well. If the impurity is not implanted for controlling the threshold value, the balance with the N-type MOSFET becomes poor when the inverter circuit or the like is formed (when the CMOS is formed), and the inversion voltage largely deviates from the center of the power supply voltage. The operation margin is significantly reduced. In addition, since the threshold voltage value is large, N-type MOSFET and P-type MOSFET
It becomes difficult to lower the power supply voltage that requires a value larger than the sum of the absolute values of the threshold values of. Therefore, the threshold voltage is generally reduced by implanting impurities for controlling the threshold value.

However, if the impurity implantation for threshold value control in the direction of decreasing the impurity concentration of the channel region is performed, M
The channel of the OSFET is formed in a region slightly buried inside the substrate from the surface of the channel region (buried channel), and a surface depletion region is formed on the outermost surface of the channel region. In this case, after the channel is formed, the driving capability is larger than that of the surface channel with the same channel length, but before the channel is formed, channel leakage of a gate bias (0 V) lower than the threshold voltage of the surface channel with the same channel length is generated. (Subthreshold characteristic) is significantly deteriorated. The driving capability is high because the channel is not formed on the outermost surface (Si-SiO2 interface), and the poor subthreshold characteristics are the channel region outermost surface (Si-SiO2 interface).
This is because a depletion layer is formed between the interface) and the channel.

As described above, in both the LDD structure using the spacer and the offset LDD structure using the mask, the short channel effect is realized to some extent by using the technique of suppressing the short channel effect such as pocket implantation. However, especially in high voltage driving, the buried channel type has a lower subthreshold characteristic than the surface channel type in which a channel is formed on the surface of the channel region, and there is a limit to shortening the channel.

[0023]

In order to solve the above-mentioned problems, the present invention uses the following means.

A first step of forming an N-type well and a sacrificial oxide film near the surface of the semiconductor substrate and ion-implanting an impurity of a conductivity type opposite to that of the N-type well for adjusting the threshold voltage, and removing the oxide film. A second step of forming a gate oxide film, forming a gate oxide film additionally oxidized by thermal oxidation, and then forming an N-type gate electrode was used.

After forming an N-type well and a sacrificial oxide film near the surface of the semiconductor substrate, the sacrificial oxide film is removed to form a gate oxide film, and an impurity of opposite conductivity type to the N-type well for adjusting the threshold voltage is formed. A method of manufacturing an insulated gate semiconductor device having a first step of ion-implanting silicon and a second step of forming an N-type gate electrode after forming a gate oxide film additionally oxidized by thermal oxidation was used. .

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device, an oxide film thickness of about 3 nm to 15 nm is formed on a P-type semiconductor substrate having a resistance of about 20 ohm-cm. The method of manufacturing an insulated gate semiconductor device having the step of

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device, the additional oxidized gate oxide film thickness is 1
A method for manufacturing an insulated gate semiconductor device having a step of increasing the oxide film thickness by increasing the thickness from about 10 nm to about 10 nm was used.

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device described above, the oxidation rate is reduced by using nitrogen gas which is 100 times to 300 times as high as the flow rate of oxygen gas which is an oxidation reaction gas, which is an oxidation reaction suppressing gas. The method of manufacturing an insulated gate semiconductor device having the above-described thermal oxidation step was used.

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device, the method for manufacturing an insulated gate semiconductor device having a thermal oxidation step in which hydrogen gas is added to an oxidation reaction gas to improve the quality of an oxide film is used. I was there.

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device, an insulated gate type having a step of partially etching the surface of the gate oxide film previously formed by cleaning before oxidation and then performing thermal oxidation A method of manufacturing a semiconductor device was used.

Regarding the thermal oxidation in the second step of the method for manufacturing a semiconductor device described above, a pre-oxidation cleaning step is omitted, and an insulated gate semiconductor device having a step of continuously performing thermal oxidation in the same thermal oxidation furnace is manufactured. The method was used.

Regarding the gate oxide film in the second and first steps of the method for manufacturing a semiconductor device described above, the thickness is 5 nm to 40 n
A method of manufacturing an insulated gate semiconductor device having a step of setting an oxide film thickness such that the electric field applied to the gate oxide film is about 4 MV / cm or less in practical use was used.

In a method of manufacturing a semiconductor integrated circuit device having a non-volatile memory element, a non-volatile memory element having a step of using both a tunnel oxide film forming step and an additional oxidation step in the second step of the semiconductor device manufacturing method is incorporated. The method of manufacturing the semiconductor integrated circuit device of the type was used.

In a method of manufacturing a semiconductor integrated circuit device having a non-volatile memory element, a non-volatile memory element having a step of using both a tunnel oxide film forming step and an additional oxidation step in the second step of the method of manufacturing a semiconductor device is incorporated. The method of manufacturing the semiconductor integrated circuit device of the type was used.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION As described above,
According to the present invention, in the semiconductor integrated circuit device in which the P-type MOSFET is used relatively more frequently than the N-type MOSFET, the substrate concentration on the outermost surface of the channel region of the buried channel-type MOSFET (here, P-type MOSFET) is formed to be high. The width of the surface depletion layer in the upper part of the channel region is formed thin to reduce the leak current, facilitate the shortening of the channel, and promote the improvement of its driving capability.

As described above, in the case of the buried channel structure (the structure in which the PMOSFET having the N-type gate electrode is subjected to the surface impurity implantation for the threshold control), when the gate bias above the threshold voltage is applied, The cross sectional structure is as shown in FIG. This is because the energy band shown in FIG. 2 is generated. This is N
This is due to the difference in work function between the mold gate electrode 104 and the Nwell 123.

To turn on / off the MOSFET, the bias applied to the gate electrode changes the conductivity type of the semiconductor substrate in the channel region between the source / drain as an electric field,
It occurs depending on whether the channel is generated or the channel is extinguished, and the gate bias that generates the channel is a value called a threshold value. The region where the gate bias is from the OFF voltage to the threshold voltage is called the sub-threshold region, and the more rapidly it changes from OFF to ON, the more excellent the sub-threshold characteristic, and the quantified index is the sub-threshold characteristic. Swing (S) Logarithm of gate voltage (VG) and drain current (LOG I
D) slope (VG / LOG ID [mV / decade])
Is. That is, the sub-threshold swing (S) becomes smaller as the gate electric field is directly transmitted to the channel generation place.

In the case of the surface channel structure, the potential of the channel generated on the outermost surface of the channel region is determined by the gate insulating film capacitance (capacitance) between the gate electrode and the outermost surface of the semiconductor substrate and the channel and the semiconductor substrate below the channel. It is determined by the depletion layer capacitance (capacitance) between and, and the coupling ratio by these two capacitances. That is, the larger the gate insulating film capacitance (thin film, high dielectric constant) and the smaller the substrate-side depletion layer capacitance (thick width depletion layer, low dielectric constant), the smaller S becomes.

On the other hand, in the case of the buried channel structure, the potential of the channel generated inside the channel region is determined by the gate insulating film capacitance (capacitance) between the gate electrode and the outermost surface of the semiconductor substrate and between the outermost surface of the semiconductor substrate and the channel. The surface depletion layer capacitance (capacitance) and the depletion layer capacitance (capacitance) between the channel and the semiconductor substrate below the channel are determined by the coupling ratio of these three capacitances.
Only when the gate insulating film capacitance is large (thin film, high dielectric constant) and the substrate-side depletion layer capacitance is small (thick width depletion layer, low dielectric constant), there is a limit in reducing S. In other words, if the surface depletion layer width is also made thin and the capacity is increased, it is possible to further reduce S, which in turn reduces the leakage current and the channel length. Then, PMOSFET)
In essence, high drive can be realized.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, a buried channel MOSFET device formed on a single crystal semiconductor substrate (here,
The case where the present invention is used for PMOSFET) is shown. The manufacturing method of this example is shown in FIG. First, an N-type well 1 is formed on a semiconductor substrate 101 by using a conventional integrated circuit manufacturing method.
23, an element isolation oxide film 110 is provided.

The detailed manufacturing method is as follows.
By implanting phosphorus ions near the surface of the semiconductor substrate 101,
Annealing is performed at 00 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute phosphorus ions to form an N-type well 123 having an impurity concentration of about 1E16 cm −3. Subsequently, after patterning with a nitride film or the like, an element isolation oxide film 110 is formed by a so-called LOCOS method.

After forming the sacrificial oxide film 124,
A channel dope implantation region 112 is formed by implanting boron ions or BF2 ions for controlling a threshold voltage into a desired channel region.

After this, as shown in FIG. 4, after removing the sacrificial oxide film 124, a gate oxide film is formed, and then additional oxidation is performed. The detailed manufacturing method is as follows. Gate oxide film to desired thickness (for example, from 5 nm to 4 nm)
After being formed with a film thickness of about 0 nm so that the electric field applied to the gate oxide film is 4 MV / cm or less in actual use), thermal oxidation is subsequently performed. In this way, the gate oxide film 113 additionally oxidized is formed.

This subsequent thermal oxidation step consists of 2
A film thickness of about 3 nm to 15 nm is formed on a P-type semiconductor substrate having a resistance of about 0 ohm-cm, or the total gate oxide film thickness (the gate oxide film thickness provided in advance is It is assumed that the gate oxide film thickness (including the film thickness added by the thermal oxidation) increases from about 1 nm to about 10 nm.

By this thermal oxidation step, the outermost surface portion of the channel dope injection region 112 is oxidized, phosphorus in the oxidized portion is segregated in the outermost surface portion, and boron in the vicinity of the oxidized portion is taken into the oxide film. , The total impurity concentration (N-type impurity concentration) in the outermost surface portion becomes high.

The film thickness of the channel dope injection region 112 oxidized by the subsequent thermal oxidation process is about 45% of the increased gate oxide film thickness. Further, it is desirable that this subsequent thermal oxidation step be performed without taking out from the thermal oxidation furnace after the step of the thermal oxidation portion for forming the gate oxide film in advance is completed. However, the same effect can be obtained even if the gate oxidization process is completed in advance and then taken out from the thermal oxidization furnace, and after the other processes are completed. Furthermore, after the end of the gate oxidation process in advance,
When the thermal oxidation step is carried out once after being taken out from the thermal oxidation furnace and the other steps are completed, the same effect can be obtained by performing the pre-oxidation cleaning. The pre-oxidation cleaning has essentially the same effect whether or not the pre-formed gate oxide film is slightly etched, but the film thickness of the channel dope implantation region 112 oxidized by additional oxidation is the same. However, since it changes depending on the etching amount, it is necessary to select the optimum etching amount.

Furthermore, the channel dope implantation region 11 is oxidized by the thermal oxidation process that is subsequently performed here.
Since the film thickness of 2 is very thin, the subthreshold characteristics may vary greatly if a normal oxidation process is used. Therefore, it is desirable to carry out this oxidation step using oxidation conditions that are extremely diluted with nitrogen gas or the like, or at a low temperature with a low oxidation rate. For example, the flow rate of nitrogen gas during oxidation in the thermal oxidation furnace is 100 times to 300 times that of oxygen.
About double. In this case, wet oxidation using hydrogen gas at the same time is more effective. When low temperature oxidation is used, the quality of the oxide film may be deteriorated.
It is desirable to oxidize at a temperature of ℃ or more. Further, even in the pre-oxidation cleaning, variations in the etching amount may adversely affect the subthreshold characteristics. Therefore, it is desirable to dilute the cleaning liquid concentration to keep the etching rate low.

The description so far has been made on the case where the P-type impurity for controlling the threshold value is implanted through the sacrificial oxidation 124. However, after the sacrificial oxidation 124 is removed, the gate oxidation step is performed, and then the threshold voltage is applied. The effect of the present invention becomes more remarkable when the control P-type impurity implantation is performed and then the above-described thermal oxidation step is performed.

FIG. 105 shows the surface impurity concentration profile in the vertical direction of the channel region thus formed. The impurity concentration of each region is Nwell 123 in a region deeper than the threshold control P-type impurity implantation region, and Nwell123 in a region from the threshold control P-type impurity implantation region to the depth where the channel is formed. The concentration obtained by subtracting the P-type impurity concentration for threshold control from the concentration, the channel outermost surface region is N
The concentration where the type impurities are locally concentrated appears. On the other hand, the surface impurity concentration profile in the vertical direction of the channel region formed by the conventional manufacturing method is shown in FIG. Compared with FIG. 6, a remarkable difference is seen in the impurity concentration of the outermost surface portion.

Thereafter, as shown in FIG. 7, low pressure CVD is performed.
A polysilicon film having a thickness of 100 to 500 nm is formed by a method or the like, an N-type polysilicon film is formed by phosphorus ion implantation or phosphorus predeposition, and a gate electrode 104 is formed by patterning. Then, an oxide film is formed on the upper portion, side wall portion, semiconductor substrate surface portion, etc. of the gate electrode 104 by using a thermal oxidation method, a low pressure CVD method or the like.

Here, a tungsten silicide film having a thickness of about 100 to 200 nm is formed on the N-type polysilicon film by a sputtering method, and a thickness of about 100 to 300 nm is formed on the tungsten silicide film by a low pressure CVD method. The oxide film may be formed. After that, the P− type impurity region 125 having an impurity concentration of about 1E18 cm −3 is formed by using the gate electrode 104 and another mask if necessary.
And a pocket region 126 having an impurity concentration of about 1E17 cm-3
To form.

Here, when the pocket region 126 is formed at about 1/10 of the impurity concentration of the P− type impurity region 125, the trade-off relationship between the leak characteristic and the driving capability due to the reduction of the channel length is the optimum value. Becomes This is because the depletion layer spreads in the channel direction and the P− type impurity region 12
This is because the optimum value is obtained in relation to the resistance value of 5.

Although not shown here, an oxide film spacer may be formed on the side wall of the gate electrode by anisotropic etching after forming an oxide film of about 300 to 600 nm by a CVD method or the like. In this case, an LDD-structured PMPS FET using a spacer is finally obtained.

Although not shown here, a photoresist may be formed on the gate electrode and in a region oversized by 0.2 μm to 2.0 μm from the gate electrode. In this case, the PMPS FET having the offset LDD structure is finally obtained.

Then, again by ion implantation, P +
A type impurity region 127 is formed. Impurity concentration is 1E2
It is about 1 cm-3. In this way, FIG. 103 is obtained.

Finally, an interlayer insulating film such as a phosphorus glass layer is formed as an interlayer insulator as in the case of manufacturing a conventional integrated circuit. For forming the phosphorus glass layer, for example, a reduced pressure CV
The method D may be used. As material gas, monosilane S
Using iH4, oxygen O2 and phosphine PH3, 450 ℃
It is obtained by reacting with.

After that, a hole for forming an electrode is opened in the interlayer insulating film to form an aluminum electrode. Thus, the buried channel MOSFET device is completed.

Although the PMOSFET thus obtained uses N-type polysilicon for the gate electrode,
Compared with the conventional buried channel P-type MOSFET, the sub-threshold characteristic is excellent, and the leakage current and the driving ability are excellent. In particular, when the channel length is reduced, the leak current between the source and drain can be remarkably reduced, which facilitates miniaturization and higher driving.

In the following description, since the above-mentioned additional oxidation step is applied to the manufacturing method of the non-volatile memory type semiconductor device, the manufacturing process of the non-volatile memory element is simplified and the whole semiconductor integrated circuit device having the non-volatile memory element is provided. It is a performance improvement of.

Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, the case where the present invention is applied to an analog / digital signal control MOSFET device and a non-volatile memory MOSFET device formed on the same semiconductor substrate is shown. As shown in FIG. 8, on the semiconductor substrate 101,
Using the conventional integrated circuit manufacturing method, the Pwell 114, the element isolation oxide film 110, the channel stopper 120, the tunnel oxide film 121, the select gate electrode 119, the floating gate electrode 118, the tunnel drain 11 are formed.
6, N + region 115 is provided.

The detailed manufacturing method is as follows.
By implanting boron ions near the surface of the semiconductor substrate 101, 1
Annealed at 000 to 1175 ° C. for 3 to 20 hours to diffuse and redistribute boron ions, and impurity concentration 1E16 cm
A P well 114 of about -3 is formed. Then, implant B + ions into the region patterned by the nitride film,
A channel stopper 120 and an element isolation oxide film 110 are formed by the LOCOS method, and then phosphorus or arsenic ions for tunnel drain formation are implanted into a desired region.

After that, an impurity for controlling the threshold value is implanted into a desired region, and the gate oxide film 122 is formed by a thermal oxidation method.
After forming the film, a selective wet etching is performed by using a photo process, and thereafter, additional oxidation is performed. This additional oxidation process is used as the tunnel oxide film 121 of the nonvolatile memory element.

The detailed manufacturing method is as follows.
The gate oxide film has a desired film thickness (for example, 5 nm to 40 n).
m, the electric field applied to the gate oxide film is 4M in actual use
After the film is formed to have a film thickness of V / cm or less), thermal oxidation is subsequently performed. In this way, the tunnel oxide film 121 is formed by additional oxidation.

This subsequent thermal oxidation step consists of 2
A film thickness of about 3 nm to 15 nm is formed on a P-type semiconductor substrate having a resistance of about 0 ohm-cm, or the total gate oxide film thickness (the gate oxide film thickness provided in advance is It is assumed that the gate oxide film thickness (including the film thickness added by the thermal oxidation) increases from about 1 nm to about 10 nm.

As described above, this thermal oxidation process oxidizes and oxidizes the outermost surface portion of the channel dope injection region of the buried channel type MOSFET (here, the peripheral circuit for controlling and driving the nonvolatile memory element). The phosphorus in the exposed portion is segregated to the outermost surface portion, and boron in the vicinity of the oxidized portion is taken into the oxide film, so that the total impurity concentration (N-type impurity concentration) in the outermost surface portion is increased. Thus, the performance of the buried channel MOSFET (peripheral circuit that controls and drives the nonvolatile memory element) is improved.

That is, in this embodiment, since the additional oxidation step for improving the performance of the buried channel type MOSFET described above and the tunnel oxide film forming step for the nonvolatile memory element are combined, a small number of manufacturing steps are required.
It is possible to realize a high-performance semiconductor integrated circuit device with a built-in nonvolatile memory.

[0069]

The PMOSFET obtained according to the present invention
Is a buried channel structure in which N-type polysilicon is used for the gate electrode, but its subthreshold characteristics are superior to those of the conventional buried-channel P-type MOSFET. Therefore, especially when the channel length is reduced. The leakage current between the source and drain of
We have made it easier to miniaturize and drive higher.

Furthermore, the present invention is an effective method for ultra-low power consumption, which is expected to progress in the future by lowering the threshold voltage.

In the voltage regulator semiconductor integrated circuit device, the area ratio occupied by the P-type MOSFET is extremely large. For this reason, the effect (cost reduction effect) on the area reduction due to the high drive and miniaturization of the P-type MOSFET is remarkable.

Although the present invention has been mainly described with respect to a silicon-based semiconductor device, it is obvious that the present invention can be applied to a semiconductor device using another material such as germanium, silicon carbide or gallium arsenide. Further, in the embodiment, Nwe
The manufacturing process of a PMOSFET having an N-type gate electrode in 11 and introducing a P-type impurity for threshold adjustment has been described. However, a P-well has a P-type gate electrode in the well and an N-type gate electrode for threshold adjustment. The present invention can be applied to the manufacturing process of an NMOSFET in which a type impurity is introduced. Further, an NMOSF called a depletion type which has an N-type gate electrode in a Pwell and introduces an N-type impurity for threshold adjustment.
A PMOSF having a P-type gate electrode in the Nwell and a P-type impurity introduction for threshold adjustment
It can also be applied to the manufacturing process of ET.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a buried channel type transistor of the present invention.

FIG. 2 is a schematic energy band diagram of a buried channel transistor.

FIG. 3 is a schematic cross-sectional view in order of the manufacturing steps of the buried channel transistor of the present invention.

FIG. 4 is a schematic cross-sectional view in order of the manufacturing steps of the buried channel type transistor of the present invention.

FIG. 5 is a surface impurity concentration profile diagram of a conventional buried channel transistor.

FIG. 6 is a surface impurity concentration profile diagram of a buried channel type transistor of the present invention.

FIG. 7 is a schematic cross-sectional view in order of the manufacturing steps of the buried channel transistor of the present invention.

FIG. 8 is a schematic sectional view of a nonvolatile memory cell of the present invention.

FIG. 9 is a schematic cross-sectional view in order of manufacturing steps of a conventional method for manufacturing a semiconductor device.

FIG. 10 is a schematic cross-sectional view in the order of manufacturing steps of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

101 semiconductor substrate 102 drain region 103 source area 104 N-type gate electrode 105 Depletion layer 106 depletion layer 107 surface depletion region 108 channel depletion region 109 channel region 110 element isolation oxide film 111 Gate oxide film 112 channel dope injection region 113 Gate oxide film additionally oxidized 114 Pwell 115 N + area 116 tunnel drain region 117 Control gate area 118 Floating gate electrode 119 Select gate area 120 channel stopper 121 tunnel oxide film 122 gate oxide film 123 Nwell 124 Sacrificial oxide film 125 P-type impurity region 126 pocket areas 127 P + impurity region 201 P type semiconductor substrate 202 gate insulating film 203 High impurity concentration region 204 gate electrode 205 insulating film 206 spacer 207 N type well 208 field insulation 211 N-type impurity region 212 N + type impurity region 213 Region with low impurity concentration 214 P + type impurity region 215 P- type impurity region 216 Gate electrode (for NMOS) 217 Gate electrode (for PMOS) 220 phosphorus glass layer 221 aluminum electrode 223 Pocket implant region 224 pocket area (for NMOS) 225 pocket area (for PMOS) 233 oxide film 234 resist mask 235 resist mask

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/788 H01L 27/08 321D 29/792 F term (reference) 5F048 AA08 AB01 AC03 BA01 BB06 BB08 BB11 BD04 BE03 BG12 BH07 5F083 EP02 EP33 EP42 EP45 EP50 EP64. BH15 BH36 BK13

Claims (11)

[Claims] 1. A first step of forming an N-type well and a sacrificial oxide film near a surface of a semiconductor substrate and ion-implanting an impurity of a conductivity type opposite to that of the N-type well for adjusting a threshold voltage, and the oxide film. And a second step of forming an N-type gate electrode after forming a gate oxide film, forming a gate oxide film additionally oxidized by thermal oxidation, and forming a N-type gate electrode. Device manufacturing method. 2. An N-type well and a sacrificial oxide film are formed in the vicinity of the surface of a semiconductor substrate, the sacrificial oxide film is removed, and a gate oxide film is formed, which is opposite to the N-type well for adjusting the threshold voltage. An insulated gate comprising: a first step of ion-implanting conductivity type impurities; and a second step of forming an N-type gate electrode after forming a gate oxide film additionally oxidized by thermal oxidation. Type semiconductor device manufacturing method. 3. The thermal oxidation of the second step of the method for manufacturing a semiconductor device according to claim 1, wherein a film thickness of 3 nm to 15 nm is formed on a P-type semiconductor substrate having a resistance of about 20 ohm-cm. A method for manufacturing an insulated gate semiconductor device, comprising the step of setting an oxide film thickness to be formed. 4. The thermal oxidation of the second step of the method of manufacturing a semiconductor device according to claim 1, wherein the additional oxidized gate oxide film thickness is from 1 nm to 10 n.
A method for manufacturing an insulated gate semiconductor device, comprising the step of increasing the oxide film thickness by increasing m. 5. The thermal oxidation in the second step of the method for manufacturing a semiconductor device according to claim 1, wherein the flow rate of oxygen gas, which is an oxidation reaction gas, is 100 times to 300 times.
A method of manufacturing an insulated gate semiconductor device, comprising: a thermal oxidation step in which an oxidation rate is reduced by using nitrogen gas which is twice as much as an oxidation reaction suppressing gas. 6. The thermal oxidation of the second step of the method for manufacturing a semiconductor device according to claim 1 or 2, further comprising a thermal oxidation step in which hydrogen gas is added to an oxidation reaction gas to improve an oxide film quality. And method for manufacturing an insulated gate semiconductor device. 7. The thermal oxidation in the second step of the method for manufacturing a semiconductor device according to claim 1, wherein the surface of the gate oxide film previously formed by the pre-oxidation cleaning is partially etched and then the thermal oxidation is performed. A method of manufacturing an insulated gate semiconductor device, comprising: 8. The thermal oxidation of the second step of the method for manufacturing a semiconductor device according to claim 1, further comprising a step of omitting the pre-oxidation cleaning step and continuously performing thermal oxidation in the same thermal oxidation furnace. A method for manufacturing an insulated gate semiconductor device, comprising: 9. The gate oxide film of the second step of the method for manufacturing a semiconductor device according to claim 1 or the first step of the method for manufacturing a semiconductor device according to claim 2, wherein the thickness is from 5 nm to 40 nm.
nm or an oxide film thickness such that the electric field applied to the gate oxide film in actual use is 4 MV / cm or less. 10. A method for manufacturing a semiconductor integrated circuit device having a non-volatile memory element, wherein the step of forming a tunnel oxide film and the additional oxidation step of the second step of the method of manufacturing a semiconductor device according to claim 1 are combined. A method of manufacturing a semiconductor integrated circuit device with a built-in non-volatile memory element, comprising: 11. A method for manufacturing a semiconductor integrated circuit device having a non-volatile memory element, wherein the tunnel oxide film forming step and the additional oxidation step in the second step of the semiconductor device manufacturing method according to claim 2 are combined. A method of manufacturing a semiconductor integrated circuit device with a built-in non-volatile memory element, comprising: