JP2003007883A - Package for storing semiconductor element and semiconductor device - Google Patents

Package for storing semiconductor element and semiconductor device

Info

Publication number
JP2003007883A
JP2003007883A JP2001193746A JP2001193746A JP2003007883A JP 2003007883 A JP2003007883 A JP 2003007883A JP 2001193746 A JP2001193746 A JP 2001193746A JP 2001193746 A JP2001193746 A JP 2001193746A JP 2003007883 A JP2003007883 A JP 2003007883A
Authority
JP
Japan
Prior art keywords
line conductor
circuit board
conductor layer
semiconductor element
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001193746A
Other languages
Japanese (ja)
Other versions
JP3652279B2 (en
Inventor
Toshihiko Kitamura
俊彦 北村
Nobuyuki Tanaka
信幸 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001193746A priority Critical patent/JP3652279B2/en
Publication of JP2003007883A publication Critical patent/JP2003007883A/en
Application granted granted Critical
Publication of JP3652279B2 publication Critical patent/JP3652279B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Non-Reversible Transmitting Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve reliability by preventing a semiconductor element from malfunctioning due to noise entered by reflection of high frequency signal contents for terminal signals into terminal electrodes of the semiconductor element. SOLUTION: A circuit board 6 is mounted on a shelf portion 2b-B inside of the semiconductor package. On the upper face of the circuit board 6, a line conductor 6 for grounding is provided with its one end electrically connected to the semiconductor element 5 and the other end reaching the circumference part of the upper face, and a high resistant part 8 at the middle. On the lower face of the circuit board 6, a grounding conductor layer 6c is formed. On the side face, a notch 16, which penetrates from the upper face to the lower face and reaches the other end of the line conductor 6b at an opening of the upper face is provided. Moreover, a conductive layer 16b is formed on the inside wall of the notch 16 for electrically connecting the other end of the line conductor 6b and the grounding conductor layer 6c.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、高周波信号で作動
する半導体素子を収納するための半導体素子収納用パッ
ケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element that operates with a high frequency signal.

【0002】[0002]

【従来の技術】従来、光通信分野で使用されたり、マイ
クロ波帯,ミリ波帯等の高周波信号を用いる各種半導体
素子を収納する半導体素子収納用パッケージ(以下、半
導体パッケージという)には、半導体素子を電気的に接
地するための導体パターンとしての線路導体が設けられ
ている。このような半導体パッケージを図4に断面図で
示す。同図において、21は基体、22は金属製の枠
体、26は回路基板である。
2. Description of the Related Art Conventionally, semiconductor element storage packages (hereinafter referred to as semiconductor packages) used in the field of optical communication or for storing various semiconductor elements using high frequency signals in the microwave band, millimeter wave band, etc. A line conductor is provided as a conductor pattern for electrically grounding the element. Such a semiconductor package is shown in cross section in FIG. In the figure, 21 is a base, 22 is a metal frame, and 26 is a circuit board.

【0003】基体21は鉄(Fe)−ニッケル(Ni)
−コバルト(Co)合金や銅(Cu)−タングステン
(W)等の金属から成る略四角形状の板状体であり、そ
の上側主面には、IC,LSI,半導体レーザ(L
D),フォトダイオード(PD)等の半導体素子25と
回路基板26−A,26−Bが載置固定される。回路基
板26−A,26−Bの下面には、接地導体層26c−
A,26c−Bが被着されており、銀(Ag)ろう、A
g−銅(Cu)ろう等のろう材や半田によって接地導体
層26cと載置部21aが強固に接着される。
The base 21 is iron (Fe) -nickel (Ni).
-A substantially rectangular plate-like body made of a metal such as cobalt (Co) alloy or copper (Cu) -tungsten (W). The upper main surface thereof has an IC, an LSI, a semiconductor laser (L).
D), the semiconductor element 25 such as a photodiode (PD), and the circuit boards 26-A and 26-B are mounted and fixed. The ground conductor layer 26c- is formed on the lower surfaces of the circuit boards 26-A and 26-B.
A, 26c-B is deposited, silver (Ag) wax, A
The ground conductor layer 26c and the mounting portion 21a are firmly adhered by a brazing material such as g-copper (Cu) brazing or solder.

【0004】なお、半導体素子25は、その電極が回路
基板26に被着されている第1の線路導体26aと第2
の線路導体26bにそれぞれボンディングワイヤ27
a,27bを介して電気的に接続されている。
The semiconductor element 25 includes a first line conductor 26a whose electrodes are attached to a circuit board 26 and a second line conductor 26a.
Bonding wires 27 to the line conductors 26b of
It is electrically connected via a and 27b.

【0005】基体21の上側主面の外周部には載置部2
1aを囲繞するようにして枠体22が立設されており、
枠体22は基体21とともにその内側に半導体素子25
を収容する空所を形成する。枠体22は基体21と同様
にFe−Ni−Co合金やCu−Wの焼結材等から成
り、基体21と一体成形される、または基体21にAg
ろう,Ag−Cuろう等のろう材を介してろう付けされ
る、またはシーム溶接法等の溶接法により接合されるこ
とによって、基体21の上側主面の外周部に立設され
る。
The mounting portion 2 is provided on the outer peripheral portion of the upper main surface of the base 21.
A frame 22 is erected so as to surround 1a,
The frame body 22 is formed with the semiconductor element 25 inside the base body 21.
To form a void for housing The frame 22 is made of a sintered material such as a Fe—Ni—Co alloy or Cu—W like the base 21, and is integrally molded with the base 21, or the base 21 is made of Ag.
It is erected on the outer peripheral portion of the upper main surface of the base body 21 by being brazed through a brazing material such as brazing or Ag-Cu brazing or being joined by a welding method such as a seam welding method.

【0006】枠体22の側面には同軸コネクタ23が嵌
着される貫通孔22aが形成されており、貫通孔22a
内に同軸コネクタ23を嵌め込むとともに半田等の封着
材を貫通孔22a内の隙間に挿入し、しかる後、加熱し
て封着材を溶融させ、溶融した封着材を毛細管現象によ
り同軸コネクタ23と貫通孔22aの内面との隙間に充
填させることによって、同軸コネクタ23が貫通孔22
a内に封着材を介して嵌着接合される。この同軸コネク
タ23は、中心軸部分に信号線路としてFe−Ni−C
o合金等の金属から成る棒状の中心導体23aが固定さ
れている。中心導体23aが半田等から成る導電性接着
材を介して回路基板26−Aの第1の線路導体26aに
電気的に接続される。同軸コネクタ23には、外部電気
回路(図示せず)に接続された同軸ケーブル(図示せ
ず)が装着されることにより、半導体パッケージ内部に
収納された半導体素子25が同軸コネクタ23の中心導
体23aを介して外部電気回路に電気的に接続される。
A through hole 22a into which the coaxial connector 23 is fitted is formed on the side surface of the frame body 22, and the through hole 22a is formed.
The coaxial connector 23 is fitted therein, and a sealing material such as solder is inserted into the gap in the through hole 22a. Thereafter, the sealing material is melted by heating, and the melted sealing material is caused by the capillary phenomenon by the coaxial connector. 23 and the inner surface of the through hole 22 a are filled with the coaxial connector 23 so that the through hole 22 is formed.
It is fitted and joined in a through a sealing material. This coaxial connector 23 has an Fe-Ni-C as a signal line on the central axis portion.
A rod-shaped central conductor 23a made of metal such as o alloy is fixed. The center conductor 23a is electrically connected to the first line conductor 26a of the circuit board 26-A via a conductive adhesive material such as solder. A coaxial cable (not shown) connected to an external electric circuit (not shown) is attached to the coaxial connector 23, so that the semiconductor element 25 housed inside the semiconductor package is inserted into the center conductor 23a of the coaxial connector 23. Is electrically connected to an external electric circuit via.

【0007】第2の線路導体26bは、図5に要部拡大
平面図を示すように、回路基板26−Bの第2の線路導
体26bの延長部の端面に設けられた導体層26dを介
して、接地導体層26c−Bに電気的に接続される。第
2の線路導体26bには高抵抗部28が設けられてい
る。この高抵抗部28は、第2の線路導体26bを流れ
て接地導体層26c−Bに接地される、高周波信号成分
を含む終端用信号を、電気エネルギーから熱エネルギー
に変換し、接地導体層26c−Bからの終端用信号の反
射によるノイズを抑制して電気的に接地するものであ
る。
The second line conductor 26b has a conductor layer 26d provided on the end face of the extension of the second line conductor 26b of the circuit board 26-B, as shown in the enlarged plan view of the main part of FIG. And is electrically connected to the ground conductor layer 26c-B. A high resistance portion 28 is provided on the second line conductor 26b. The high resistance portion 28 converts a termination signal including a high frequency signal component, which flows through the second line conductor 26b and is grounded to the ground conductor layer 26c-B, from electrical energy to thermal energy, and the ground conductor layer 26c. The noise due to the reflection of the termination signal from -B is suppressed and electrically grounded.

【0008】または、導体層26dを設ける代わりに、
図6に要部拡大平面図を示すように、第2の線路導体2
6bの高抵抗部28と、ボンディングワイヤ27bが接
続された側と反対側の回路基板26の側面との間に貫通
孔26eを設け、その貫通孔26e内面に導体層を設け
ることによって、第2の線路導体26bを接地導体層2
6c−Bに電気的に接続する構成が提案されている(特
開平10−51069号公報参照)。
Alternatively, instead of providing the conductor layer 26d,
As shown in the enlarged plan view of the main part in FIG. 6, the second line conductor 2
By providing a through hole 26e between the high resistance portion 28 of 6b and the side surface of the circuit board 26 on the side opposite to the side to which the bonding wire 27b is connected, and by providing a conductor layer on the inner surface of the through hole 26e, The line conductor 26b of the ground conductor layer 2
A configuration for electrically connecting to 6c-B has been proposed (see Japanese Patent Laid-Open No. 10-51069).

【0009】最後に、基体21、枠体22から成る容器
内部に半導体素子25を収容し、枠体22の上面に蓋体
24をろう付け法やシームウエルド法等の溶接法により
接合し、容器内部を気密に封止することによって製品と
しての半導体装置となる。
Finally, the semiconductor element 25 is housed in a container consisting of the base body 21 and the frame body 22, and the lid body 24 is joined to the upper surface of the frame body 22 by a welding method such as a brazing method or a seam weld method. A semiconductor device as a product is obtained by hermetically sealing the inside.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、上記従
来の半導体パッケージにおいては、回路基板26−Bに
設けた第2の線路導体26bを伝わる終端用信号の高周
波化が進むと、第2の線路導体26bに設けられた高抵
抗部28において、終端用信号の電気エネルギーを熱エ
ネルギーに変換することが困難になってきた。そのた
め、第2の線路導体26bを伝送する終端用信号を確実
に接地できなくなり、第2の線路導体26bを伝わる終
端用信号によって接地導体層26c−Bからの反射によ
るノイズが発生し、そのノイズが半導体素子25に入り
込んで半導体素子25に誤動作を発生させるという問題
点を有していた。
However, in the above-mentioned conventional semiconductor package, when the frequency of the terminating signal transmitted through the second line conductor 26b provided on the circuit board 26-B is increased, the second line conductor is increased. It has become difficult to convert the electrical energy of the termination signal into heat energy in the high resistance portion 28 provided in 26b. Therefore, the termination signal transmitted through the second line conductor 26b cannot be reliably grounded, and the termination signal transmitted through the second line conductor 26b causes noise due to reflection from the ground conductor layer 26c-B. However, there is a problem in that the semiconductor element 25 enters the semiconductor element 25 to cause a malfunction in the semiconductor element 25.

【0011】特に、上記問題点は、光通信分野で使用さ
れたりマイクロ波帯,ミリ波帯等の高周波信号を用いる
各種半導体素子を組み込んだ半導体装置の高速情報処理
化が進み、第1の線路導体26aおよび第2の線路導体
26bを介して半導体素子25に入出力される信号がよ
り高周波領域になると、より顕著となっていた。
In particular, the above problem is caused by the progress of high-speed information processing of semiconductor devices used in the field of optical communication and incorporating various semiconductor elements using high-frequency signals in the microwave band, millimeter wave band, etc. It became more prominent when the signal input to and output from the semiconductor element 25 via the conductor 26a and the second line conductor 26b was in a higher frequency region.

【0012】従って、本発明は上記問題点に鑑み完成さ
れたものであり、その目的は、半導体素子の終端用電極
に終端用信号の高周波信号成分の反射によるノイズが入
り込んで半導体素子が誤作動を起こすのを防ぐことによ
り、信頼性の高いものとすることである。
Therefore, the present invention has been completed in view of the above problems, and an object of the present invention is to cause noise due to reflection of a high frequency signal component of a termination signal into a termination electrode of the semiconductor element, thereby causing a malfunction of the semiconductor element. It is to make it reliable by preventing the occurrence of.

【0013】[0013]

【課題を解決するための手段】本発明の半導体パッケー
ジは、上側主面に半導体素子を載置するための載置部を
有する基体と、前記上側主面の外周部に前記載置部を囲
繞するように接合され、内面に回路基板を載置するため
の棚部を有する枠体とを具備した半導体素子収納用パッ
ケージにおいて、前記回路基板は、その上面に一端が前
記半導体素子に電気的に接続され他端が前記上面の縁部
に達しておりかつ途中に高抵抗部を設けた接地用の線路
導体が形成され、下面に接地導体層が形成されており、
側面に上下面を貫通するとともに上面側開口に前記線路
導体の他端が達している切欠き部が形成されており、か
つ該切欠き部の内面に前記線路導体の他端と前記接地導
体層とを電気的に接続する導体層が形成されていること
を特徴とする。
A semiconductor package according to the present invention includes a base body having a mounting portion for mounting a semiconductor element on an upper main surface and an outer peripheral portion of the upper main surface surrounding the mounting portion. In the package for storing a semiconductor element, which has a frame body having a shelf for mounting a circuit board on an inner surface thereof, the circuit board has one end on the upper surface electrically connected to the semiconductor element. A line conductor for grounding is formed, the other end of which is connected to the edge of the upper surface and a high resistance portion is provided on the way, and a grounding conductor layer is formed on the lower surface,
A cutout portion is formed on the side surface so as to penetrate the upper and lower surfaces and the other end of the line conductor reaches the opening on the upper surface side, and the other end of the line conductor and the ground conductor layer are formed on the inner surface of the cutout portion. Is characterized in that a conductor layer for electrically connecting with is formed.

【0014】本発明は、回路基板の側面に上下面を貫通
するとともに上面側開口に線路導体の他端が達している
切欠き部が形成されており、かつ切欠き部の内面に線路
導体の他端と接地導体層とを電気的に接続する導体層が
形成されていることから、線路導体を伝送する終端用信
号のうち高抵抗部において電気エネルギーから熱エネル
ギーに変換しきれないものを、切欠き部の内面に形成さ
れた導体層において枠体に向けて放射させることによ
り、終端用信号を確実に接地することができ、線路導体
の他端における終端用信号の高周波信号成分の反射を減
少させることができる。
According to the present invention, a notch portion is formed on the side surface of the circuit board so as to pass through the upper and lower surfaces, and the other end of the line conductor reaches the opening on the upper surface side, and the inner surface of the notch portion of the line conductor is formed. Since the conductor layer that electrically connects the other end and the ground conductor layer is formed, among the termination signals transmitted through the line conductor, those that cannot be converted from electrical energy to thermal energy in the high resistance portion, By radiating toward the frame in the conductor layer formed on the inner surface of the notch, the termination signal can be reliably grounded, and the reflection of the high-frequency signal component of the termination signal at the other end of the line conductor can be prevented. Can be reduced.

【0015】本発明において、好ましくは、前記切欠き
部は前記線路導体よりも幅広であることを特徴とする。
In the present invention, preferably, the notch portion is wider than the line conductor.

【0016】本発明は、上記の構成により、高抵抗部で
電気的に接地しきれない終端用信号を切欠き部の内面に
形成された導体層において、枠体に向けて終端用信号を
放射し易くなる。即ち、線路導体に設けられた高抵抗部
において電気エネルギーから熱エネルギーに変換しきれ
ない終端用信号を放射させることによって、終端用信号
をより確実に接地させることができる。
With the above structure, the present invention radiates the terminating signal toward the frame body in the conductor layer formed on the inner surface of the cutout portion for the terminating signal that cannot be electrically grounded in the high resistance portion. Easier to do. That is, the termination signal can be more reliably grounded by radiating the termination signal that cannot be completely converted from electrical energy to thermal energy in the high resistance portion provided in the line conductor.

【0017】また本発明において、好ましくは、前記回
路基板の上面に前記線路導体を取り囲むように形成され
るとともに前記線路導体の他端側に接続された同一面接
地導体層が形成されていることを特徴とする。
Further, in the present invention, preferably, a coplanar ground conductor layer is formed on the upper surface of the circuit board so as to surround the line conductor and is connected to the other end of the line conductor. Is characterized by.

【0018】本発明は、上記の構成により、線路導体の
他端において線路導体を伝送する終端用信号を電気的に
接地させるための接地導体層の面積を拡大できるため、
線路導体から接地導体層に向けての終端用信号の伝送を
スムーズに行なうことができ、他端における終端用信号
の高周波信号成分の反射を有効に減少させることができ
る。また、線路導体に略平行にかつ取り囲むように同一
面接地導体層が設けられていることから、線路導体から
同一面接地導体層に終端用信号の高周波信号成分を空間
を介して短絡させることができ、線路導体において終端
用信号を減衰させてより確実に接地することができる。
即ち、線路導体を進行する終端用信号は、線路導体の他
端側に向かって同一面接地導体層に空間を介して短絡さ
れながら進行するため、他端側にいくにつれて大幅に減
衰されることとなる。
According to the present invention, the area of the ground conductor layer for electrically grounding the terminating signal transmitted through the line conductor at the other end of the line conductor can be increased by the above structure.
The termination signal can be smoothly transmitted from the line conductor to the ground conductor layer, and the reflection of the high frequency signal component of the termination signal at the other end can be effectively reduced. Further, since the same-plane ground conductor layer is provided so as to be substantially parallel to and surround the line conductor, it is possible to short-circuit the high-frequency signal component of the termination signal from the line conductor to the same-plane ground conductor layer through a space. Therefore, the signal for termination can be attenuated in the line conductor and grounded more reliably.
That is, the terminating signal that travels along the line conductor travels toward the other end of the line conductor while being short-circuited to the ground conductor layer on the same plane through the space, and therefore is greatly attenuated toward the other end. Becomes

【0019】本発明は、このような構成により、線路導
体を伝わる終端用信号の高周波信号成分によって反射に
よるノイズが発生してそのノイズが半導体素子に入り込
むのを防止し、その結果半導体素子を正常に作動させ得
る。
With this structure, the present invention prevents noise due to reflection from being generated by the high-frequency signal component of the terminating signal transmitted through the line conductor, and prevents the noise from entering the semiconductor element. Can be activated.

【0020】本発明の半導体装置は、上記本発明の半導
体素子収納用パッケージと、前記棚部に載置された前記
回路基板と、前記載置部に載置されるとともに前記回路
基板の前記線路導体の一端に電気的に接続された前記半
導体素子と、前記枠体の上面に接合された蓋体とを具備
したことを特徴とする。
A semiconductor device according to the present invention includes the semiconductor element housing package according to the present invention, the circuit board placed on the shelf, and the line of the circuit board placed on the placing section. It is characterized by comprising the semiconductor element electrically connected to one end of a conductor, and a lid body joined to an upper surface of the frame body.

【0021】本発明は、このような構成により、本発明
の半導体パッケージを用いた信頼性の高い半導体装置を
提供できる。
With the above-described structure, the present invention can provide a highly reliable semiconductor device using the semiconductor package of the present invention.

【0022】[0022]

【発明の実施の形態】本発明の半導体パッケージについ
て以下に詳細に説明する。図1は本発明の半導体パッケ
ージについて実施の形態の一例を示す断面図であり、1
は基体、2は枠体、6は回路基板である。
BEST MODE FOR CARRYING OUT THE INVENTION The semiconductor package of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a semiconductor package of the present invention.
Is a base, 2 is a frame, and 6 is a circuit board.

【0023】本発明の枠体2は、Fe−Ni−Co合金
等の金属やCu−Wの焼結材等から成る枠状体である。
枠体2の内面には、回路基板6−A,6−Bを搭載する
ための棚部2b−A,2b−Bがそれぞれ形成される。
回路基板6−A,6−Bの下面には接地導体層6c−
A,6c−Bが被着されており、Agろう,Ag−Cu
ろう等のろう材や金(Au)−錫(Sn)半田や鉛(P
b)−Sn半田等の半田等によって接地導体層6cと棚
部2bが強固に接着される。
The frame body 2 of the present invention is a frame-shaped body made of a metal such as Fe-Ni-Co alloy or a sintered material of Cu-W.
Shelf portions 2b-A and 2b-B for mounting the circuit boards 6-A and 6-B are formed on the inner surface of the frame body 2, respectively.
A ground conductor layer 6c- is formed on the lower surface of the circuit boards 6-A and 6-B.
A, 6c-B is deposited, Ag wax, Ag-Cu
Brazing material such as wax, gold (Au) -tin (Sn) solder, lead (P)
b) The ground conductor layer 6c and the shelf portion 2b are firmly adhered to each other by solder such as -Sn solder.

【0024】半導体素子5は、その電極が回路基板6の
上面に被着形成されている第1の線路導体6aおよび第
2の線路導体6bにそれぞれボンディングワイヤ7a,
7bを介して電気的に接続されている。
The semiconductor element 5 has bonding electrodes 7a, 6b on the first line conductor 6a and the second line conductor 6b whose electrodes are formed on the upper surface of the circuit board 6, respectively.
It is electrically connected via 7b.

【0025】回路基板6は、例えばAl23セラミック
スから成る場合、以下のようにして作製される。まず、
Al23,酸化珪素(SiO2),酸化カルシウム(C
aO),酸化マグネシウム(MgO)等の原料粉末に適
当な有機バインダや可塑剤,分散剤,溶剤等を添加混合
して泥漿状となす。これを従来周知のドクターブレード
法でシート状となすことによってセラミックグリーンシ
ートを得る。しかる後、このセラミックグリーンシート
に適当な打ち抜き加工を施す、または、Al23,Si
2,CaO,MgO等の原料粉末を金型に充填しプレ
ス成型することによって、所定の形状に成形する。その
セラミックグリーンシートの上面に第1の線路導体6
a、接地用の第2の線路導体6bおよび接地導体層6c
となる金属ペーストを印刷塗布し、還元雰囲気中で約1
600℃の温度で焼成することによって製作される。
When the circuit board 6 is made of Al 2 O 3 ceramics, for example, it is manufactured as follows. First,
Al 2 O 3 , silicon oxide (SiO 2 ), calcium oxide (C
aO), magnesium oxide (MgO), and other raw material powders are added and mixed with an appropriate organic binder, plasticizer, dispersant, solvent, etc. to form a slurry. A ceramic green sheet is obtained by forming this into a sheet by a conventionally known doctor blade method. Then, the ceramic green sheet is punched appropriately, or Al 2 O 3 , Si is used.
A raw material powder such as O 2 , CaO, and MgO is filled in a mold and press-molded to form a predetermined shape. The first line conductor 6 is formed on the upper surface of the ceramic green sheet.
a, the second line conductor 6b for grounding, and the grounding conductor layer 6c
Apply a metal paste by printing and apply it in a reducing atmosphere for approx. 1
It is manufactured by firing at a temperature of 600 ° C.

【0026】第1の線路導体6a、第2の線路導体6b
および接地導体層6cとなる金属ペーストは、W,モリ
ブデン(Mo),マンガン(Mn)等の高融点金属粉末
に適当な有機バインダや溶剤を添加混合してペースト状
となしたものを従来周知のスクリーン印刷法で印刷する
ことにより、セラミックグリーンシートまたはセラミッ
クスの成形体に印刷塗布される。
The first line conductor 6a and the second line conductor 6b
As the metal paste to be the ground conductor layer 6c, a paste having a high melting point metal powder such as W, molybdenum (Mo), manganese (Mn), etc. added and mixed with an appropriate organic binder and a solvent to form a paste is well known. By printing by a screen printing method, it is applied by printing onto a ceramic green sheet or a molded body of ceramics.

【0027】なお、第1の線路導体6a、第2の線路導
体6bおよび接地導体層6cは薄膜形成法によって形成
されていても良く、その場合、第1の線路導体6a、第
2の線路導体6bおよび接地導体層6cは窒化タンタル
(Ta2N),ニクロム(Ni−Cr合金),チタン
(Ti),パラジウム(Pd),白金(Pt)−Au等
から成り、セラミックグリーンシートを焼成した後に形
成される。
The first line conductor 6a, the second line conductor 6b and the ground conductor layer 6c may be formed by a thin film forming method. In that case, the first line conductor 6a and the second line conductor 6a are formed. 6b and the ground conductor layer 6c is tantalum nitride (Ta 2 N), nichrome (Ni-Cr alloy), titanium (Ti), palladium (Pd), made of platinum (Pt) -Au like, after firing the ceramic green sheets It is formed.

【0028】また、枠体2は基体1とともにその内側に
半導体素子5を収容する空所を形成する。この枠体2
は、基体1と同様にFe−Ni−Co合金やCu−Wの
焼結材等から成り、基体1と一体成形される、または基
体1に銀ろう等のろう材を介してろう付けされる、また
はシーム溶接法等の溶接法により接合されることによっ
て基体1の上側主面の外周部に立設される。
Further, the frame body 2 forms a space inside the base body 1 for housing the semiconductor element 5 therein. This frame 2
Is made of a sintered material such as a Fe—Ni—Co alloy or Cu—W similar to the base 1, and is integrally molded with the base 1 or brazed to the base 1 via a brazing material such as silver brazing. Alternatively, they are erected on the outer peripheral portion of the upper main surface of the base 1 by being joined by a welding method such as a seam welding method.

【0029】なお、枠体2は上記のような金属から成る
か、またはセラミックス等の誘電体材料から成りかつそ
の表面にメタライズ層等の導体層が形成されているのが
好ましい。この場合、後述するように、第2の線路導体
6bを伝送する終端用信号のうち高抵抗部8において電
気エネルギーから熱エネルギーに変換しきれないもの
を、切欠き部16の内面に形成された導体層16bで枠
体2に向けて放射させることにより、枠体2で終端用信
号を確実に接地させることができる。
It is preferable that the frame 2 is made of the above metal or a dielectric material such as ceramics and has a conductor layer such as a metallized layer formed on the surface thereof. In this case, as will be described later, of the terminating signals transmitted through the second line conductor 6b, those that cannot be converted from electrical energy to thermal energy in the high resistance portion 8 are formed on the inner surface of the cutout portion 16. By radiating the conductor layer 16b toward the frame 2, the terminating signal can be reliably grounded in the frame 2.

【0030】枠体2の側面には同軸コネクタ3が嵌着さ
れる貫通孔2aが形成されており、貫通孔2a内には同
軸コネクタ3を嵌め込むとともにAu−Sn半田やPb
−Sn半田等の封着材を貫通孔2aとの隙間に挿入し、
しかる後、加熱して封着材を溶融させ、溶融した封着材
は毛細管現象により同軸コネクタ3と貫通孔2aの内面
との隙間に充填されることによって、同軸コネクタ3が
貫通孔2a内に半田等の封着材を介して嵌着接合され
る。
A through hole 2a into which the coaxial connector 3 is fitted is formed on the side surface of the frame body 2. The coaxial connector 3 is fitted into the through hole 2a and Au-Sn solder or Pb is used.
-Insert a sealing material such as Sn solder into the gap between the through hole 2a,
Thereafter, the sealing material is melted by heating, and the molten sealing material is filled in the gap between the coaxial connector 3 and the inner surface of the through hole 2a by a capillary phenomenon, so that the coaxial connector 3 is inserted into the through hole 2a. It is fitted and joined via a sealing material such as solder.

【0031】同軸コネクタ3は、半導体パッケージの内
部に収容する半導体素子5を外部電気回路に接続された
同軸ケーブルに電気的に接続させるものであり、Fe−
Ni−Co合金等の金属から成る円筒形等の筒状の外周
導体に、ガラス等の絶縁体が充填され中心軸にFe−N
i−Co合金等の金属から成る中心導体3aが固定され
て成る。中心導体3aが半田等から成る導電性接着材を
介して回路基板6−Aの第1の線路導体6aに電気的に
接続される。この同軸コネクタ3に、外部より同軸ケー
ブルが装着されることによって、内部に収納された半導
体素子5が同軸コネクタ3の中心導体3aを介して外部
電気回路に電気的に接続される。そして、半導体素子5
の電極と回路基板6の上面に形成された第1の線路導体
6aとがボンディングワイヤ7aにより電気的に接続さ
れ、第1の線路導体6aと中心導体3aとが半田等の導
電性接着材を介して電気的に接続される。
The coaxial connector 3 is for electrically connecting the semiconductor element 5 housed inside the semiconductor package to a coaxial cable connected to an external electric circuit.
A cylindrical outer peripheral conductor made of a metal such as a Ni-Co alloy is filled with an insulator such as glass, and a central axis is made of Fe-N.
A center conductor 3a made of a metal such as an i-Co alloy is fixed. The center conductor 3a is electrically connected to the first line conductor 6a of the circuit board 6-A via a conductive adhesive material such as solder. When the coaxial cable is attached to the coaxial connector 3 from the outside, the semiconductor element 5 housed inside is electrically connected to the external electric circuit via the center conductor 3a of the coaxial connector 3. And the semiconductor element 5
Electrode and the first line conductor 6a formed on the upper surface of the circuit board 6 are electrically connected by a bonding wire 7a, and the first line conductor 6a and the center conductor 3a are made of a conductive adhesive such as solder. Electrically connected via.

【0032】また、回路基板6−Bの上面に形成された
第2の線路導体6bは、図2に示すように、一端が半導
体素子5に電気的に接続され、他端が回路基板6−Bの
上面の縁部に達しており、かつ途中に高抵抗部8が設け
られ、下面に接地導体層6c−Bが形成されている。ま
た、回路基板6−Bの側面に上下面を貫通するとともに
上面側開口に線路導体6bの他端が達している切欠き部
16が形成されており、かつ切欠き部16の内面に線路
導体6bの他端と接地導体層6c−Bとを電気的に接続
する導体層16bが形成されている。また、好ましく
は、切欠き部16の幅が線路導体6bよりも幅広である
場合、線路導体6bの他端において、切欠き部16の周
縁部に線路導体6bと導体層16bとを電気的に接続す
るための周縁部導体層(第2の導体層)16aが形成さ
れていてもよい。このようにして、第2の線路導体6b
が切欠き部16の内面に設けられた導体層16bを介し
て接地導体層6c−Bに電気的に接続される。
As shown in FIG. 2, one end of the second line conductor 6b formed on the upper surface of the circuit board 6-B is electrically connected to the semiconductor element 5, and the other end thereof is the circuit board 6-. A high resistance portion 8 is provided on the way to the edge of the upper surface of B, and a ground conductor layer 6c-B is formed on the lower surface. Further, a cutout portion 16 is formed on the side surface of the circuit board 6-B so as to penetrate the upper and lower surfaces and reach the other end of the line conductor 6b at the upper surface side opening, and the line conductor is formed on the inner surface of the cutout portion 16. A conductor layer 16b that electrically connects the other end of 6b and the ground conductor layer 6c-B is formed. Further, preferably, when the width of the cutout portion 16 is wider than that of the line conductor 6b, the line conductor 6b and the conductor layer 16b are electrically connected to the peripheral edge portion of the cutout portion 16 at the other end of the line conductor 6b. A peripheral conductor layer (second conductor layer) 16a for connection may be formed. In this way, the second line conductor 6b
Are electrically connected to the ground conductor layer 6c-B via the conductor layer 16b provided on the inner surface of the cutout portion 16.

【0033】図2に示したように、第2の線路導体6b
の他端において切欠き部16が設けられ、第2の線路導
体6bの他端から切欠き部16の内面および接地導体層
6c−Bにかけて導体層16bが形成されていることか
ら、第2の線路導体6bを伝送する終端用信号のうち高
抵抗部8において電気エネルギーから熱エネルギーに変
換しきれないものを、切欠き部16の内面に形成された
導体層16bで枠体2に向けて放射させることにより、
終端用信号を確実に接地させることができる。その結
果、第2の線路導体6bの他端における終端用信号の高
周波信号成分の反射を有効に減少させることができる。
As shown in FIG. 2, the second line conductor 6b
The cutout portion 16 is provided at the other end of the second line conductor 6b, and the conductor layer 16b is formed from the other end of the second line conductor 6b to the inner surface of the cutout portion 16 and the ground conductor layer 6c-B. Of the terminating signals transmitted through the line conductor 6b, those that cannot be converted from electrical energy to thermal energy in the high resistance portion 8 are radiated toward the frame body 2 by the conductor layer 16b formed on the inner surface of the cutout portion 16. By letting
The termination signal can be reliably grounded. As a result, the reflection of the high frequency signal component of the termination signal at the other end of the second line conductor 6b can be effectively reduced.

【0034】第2の線路導体6bの途中に設けられた高
抵抗部8は、Ta2N,Ni−Cr合金等から成り、回
路基板6に印刷塗布された後に焼成されるか、薄膜形成
法により形成され、所望の抵抗値を有する厚み、幅、形
状になるように形成される。抵抗値を微小調整するため
に、高抵抗部8の一部をレーザ加工によって除去するこ
ともできる。
The high resistance portion 8 provided in the middle of the second line conductor 6b is made of Ta 2 N, Ni--Cr alloy or the like, and is fired after being printed and applied to the circuit board 6, or is formed by a thin film forming method. And is formed so as to have a thickness, width, and shape having a desired resistance value. In order to finely adjust the resistance value, a part of the high resistance portion 8 can be removed by laser processing.

【0035】本発明において、好ましくは、切欠き部1
6の幅が第2の線路導体6bより幅広であるのが良く、
この場合、第2の線路導体6bを伝送する終端用信号の
うち高抵抗部8で電気エネルギーから熱エネルギーに変
換しきれないものを、切欠き部16の内面に形成された
導体層16bで枠体2に向けて放射させ易くする。これ
により、終端用信号をより確実に接地させることがで
き、第2の線路導体6bの他端における終端用信号の高
周波信号成分の反射を有効に減少させ得る。
In the present invention, preferably the notch 1
6 is preferably wider than the second line conductor 6b,
In this case, among the termination signals transmitted through the second line conductor 6b, those that cannot be converted from electrical energy to thermal energy in the high resistance portion 8 are framed by the conductor layer 16b formed on the inner surface of the cutout portion 16. Easily radiate toward the body 2. As a result, the termination signal can be grounded more reliably, and the reflection of the high-frequency signal component of the termination signal at the other end of the second line conductor 6b can be effectively reduced.

【0036】また好ましくは、図3のように、回路基板
6−Bの上面に第2の線路導体6bに略平行にかつ取り
囲むように形成されるとともに第2の線路導体6bの他
端側に接続された同一面接地導体層17を形成すること
により、第2の線路導体6bの他端で第2の線路導体6
bを伝送する終端用信号を電気的に接地するための接地
導体層の面積を拡大できる。そのため、第2の線路導体
6bから接地導体層に向けての終端用信号の伝送をスム
ーズに行なうことができ、第2の線路導体6bの他端に
おける終端用信号の高周波信号成分の反射を有効に減少
させ得る。
Preferably, as shown in FIG. 3, it is formed on the upper surface of the circuit board 6-B so as to be substantially parallel to and surround the second line conductor 6b and on the other end side of the second line conductor 6b. By forming the connected same-plane ground conductor layer 17, the second line conductor 6 is formed at the other end of the second line conductor 6b.
The area of the ground conductor layer for electrically grounding the terminating signal transmitting b can be increased. Therefore, the termination signal can be smoothly transmitted from the second line conductor 6b to the ground conductor layer, and the reflection of the high-frequency signal component of the termination signal at the other end of the second line conductor 6b is effective. Can be reduced to.

【0037】また、第2の線路導体6bに略平行にかつ
取り囲むように同一面接地導体層17が設けられている
ため、第2の線路導体6bから同一面接地導体層17に
終端用信号の高周波信号成分を空間および間隙を介して
短絡させることができ、第2の線路導体6bにおいて終
端用信号を減衰させてより確実に接地させることができ
る。
Further, since the coplanar ground conductor layer 17 is provided so as to be substantially parallel to and surround the second line conductor 6b, the termination signal is supplied from the second line conductor 6b to the coplanar ground conductor layer 17. The high frequency signal component can be short-circuited through the space and the gap, and the terminating signal can be attenuated in the second line conductor 6b and grounded more reliably.

【0038】この場合、同一面接地導体層17は、回路
基板6−Bの上面に第2の線路導体6bを取り囲むよう
に設けられるが、好ましくは、回路基板6−Bの上面の
略全周に設けられるのがよく、同一面接地導体層17か
ら高周波信号成分が枠体2に向けて放射され易くなる。
即ち、第2の線路導体6bに設けられた高抵抗部8にお
いて接地しきれない終端用信号を放射させることによっ
て、終端用信号をより確実に接地することができる。
In this case, the same-plane ground conductor layer 17 is provided on the upper surface of the circuit board 6-B so as to surround the second line conductor 6b, but preferably, it is substantially the entire circumference of the upper surface of the circuit board 6-B. It is preferable that the high frequency signal component is radiated from the same-plane grounding conductor layer 17 toward the frame body 2.
That is, the termination signal can be grounded more reliably by radiating the termination signal that cannot be grounded in the high resistance portion 8 provided in the second line conductor 6b.

【0039】このようにして、第2の線路導体6bを伝
わる終端用信号をより確実に接地することができ、第2
の線路導体6bを伝わる終端用信号の高周波信号成分に
よって接地導体層6c−Bからの反射によるノイズが発
生しそのノイズが半導体素子5に入り込んで誤動作する
のを防止し、半導体素子5を正常に作動させ得る。
In this way, the terminating signal transmitted through the second line conductor 6b can be grounded more reliably,
The high frequency signal component of the terminating signal transmitted through the line conductor 6b prevents noise due to reflection from the ground conductor layer 6c-B and prevents the noise from entering the semiconductor element 5 and malfunctioning. Can be activated.

【0040】そして、枠体2の上面にFe−Ni−Co
合金等の金属から成る蓋体4を半田付けやシームウエル
ド法により接合することにより、製品としての半導体装
置となる。蓋体4により、容器内部に収容した半導体素
子5を気密に収容し、半導体素子5を長期にわたり正常
かつ安定に作動させることができる。この半導体装置
は、基体1が外部電気回路基板に実装され、同軸コネク
タ3と外部電気回路に接続された同軸ケーブルとを接続
することにより、内部に収容した半導体素子5が外部電
気回路に電気的に接続され、半導体素子5が高周波信号
で作動することとなる。
Then, Fe-Ni-Co is formed on the upper surface of the frame body 2.
The lid 4 made of a metal such as an alloy is joined by soldering or the seam weld method to obtain a semiconductor device as a product. The lid 4 allows the semiconductor element 5 accommodated in the container to be hermetically accommodated, and the semiconductor element 5 can be normally and stably operated for a long period of time. In this semiconductor device, the base 1 is mounted on an external electric circuit board, and the coaxial connector 3 and the coaxial cable connected to the external electric circuit are connected to each other, so that the semiconductor element 5 housed inside is electrically connected to the external electric circuit. And the semiconductor element 5 operates with a high frequency signal.

【0041】本発明において、半導体素子5に入出力さ
れる高周波信号の好ましい周波数は5〜20GHz程度
であり、この場合に高周波信号の伝送特性を良好なもの
とすることができる。
In the present invention, the preferable frequency of the high frequency signal input to and output from the semiconductor element 5 is about 5 to 20 GHz, and in this case, the transmission characteristic of the high frequency signal can be improved.

【0042】[0042]

【実施例】以下に本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.

【0043】(実施例)本発明の実施例と比較例につい
て、第2の線路導体6bの伝送特性を以下のように解析
した。伝送特性の解析は、図7(a)〜(f)に示す6
種類の解析モデルについて行なった。これらの解析モデ
ルは、図1の構成をモデル化したものである。即ち、回
路基板6が回路基板6−A,回路基板6−Bから成りそ
れぞれ棚部2b−A,2b−Bに搭載された構成をモデ
ル化したものである。
(Example) With respect to the example of the present invention and the comparative example, the transmission characteristics of the second line conductor 6b were analyzed as follows. The analysis of the transmission characteristics is shown in FIG.
The analysis model of the kind was performed. These analytical models are models of the configuration of FIG. That is, the circuit board 6 is made up of a circuit board 6-A and a circuit board 6-B and is mounted on the shelves 2b-A and 2b-B, respectively.

【0044】図7(a)は、本発明の実施例の回路基板
で、切欠き部16を設けた解析モデル(モデルA)であ
り、切欠き部16の幅がW=0.5mmの場合である。
(b)は、モデルAにおいて切欠き部16の幅がW=
1.0mmの場合である。(c)は、モデルAにおいて
切欠き部16の幅がW=2.0mmの場合である。
(d)は、比較例の構成であり、第2の線路導体26b
と接地導体層26c−Bとを回路基板26側面に設けた
導体層26dにより電気的に導通させた場合の解析モデ
ル(モデルB)である。(e)は、比較例の構成であ
り、第2の線路導体26bと接地導体層26c−Bを直
径0.5mmの貫通孔26eの内面に設けた導体層によ
り電気的に導通させた場合の解析モデル(モデルC)で
ある。(f)は、切欠き部16の幅がW=2.0mmで
あり、第2の線路導体6bを取り囲むように同一面接地
導体層17が設けられた場合の解析モデル(モデルD)
である。
FIG. 7A is an analysis model (model A) in which the circuit board of the embodiment of the present invention is provided with the cutout portion 16, and the width of the cutout portion 16 is W = 0.5 mm. Is.
(B) shows that in the model A, the width of the cutout portion 16 is W =
This is the case of 1.0 mm. (C) is the case where the width of the cutout portion 16 in the model A is W = 2.0 mm.
(D) is the configuration of the comparative example, and the second line conductor 26b
2 is an analytical model (model B) in the case where the conductor layer 26c provided on the side surface of the circuit board 26 and the ground conductor layer 26c-B are electrically connected to each other. (E) is a configuration of a comparative example, in the case where the second line conductor 26b and the ground conductor layer 26c-B are electrically connected by a conductor layer provided on the inner surface of the through hole 26e having a diameter of 0.5 mm. It is an analysis model (model C). (F) is an analytical model (model D) in the case where the width of the notch portion 16 is W = 2.0 mm and the same-plane ground conductor layer 17 is provided so as to surround the second line conductor 6b.
Is.

【0045】各解析モデルにおいて、回路基板6−B
(26−B)(厚さ1.0mm)はアルミナセラミック
ス(比誘電率εr=9.4)からなり、回路基板6−B
(26−B)の上面にはTa2Nから成る50Ωの高抵
抗部8(28)を有する線路導体6b(26b)を形成
した。そして、ボンディングワイヤ7b(27b)が接
続される側と反対側の回路基板6−Bの側面の第2の線
路導体6b(26b)を延長した部位に、切欠き部16
と導体層16b、または導体層26dを形成した。ま
た、図7(e)では、高抵抗部28とボンディングワイ
ヤ27bが接続される側と反対側の回路基板26の側面
との間に貫通孔26eを設け、貫通孔26e内面に導体
層を形成したことにより、第2の線路導体26bを回路
基板26の下面の接地導体層26c−Bに電気的に接続
した。
In each analysis model, the circuit board 6-B
(26-B) (thickness 1.0 mm) is made of alumina ceramics (relative permittivity εr = 9.4), and the circuit board 6-B
A line conductor 6b (26b) having a 50 Ω high resistance portion 8 (28) made of Ta 2 N was formed on the upper surface of (26-B). Then, the cutout portion 16 is provided at a portion of the side surface of the circuit board 6-B opposite to the side to which the bonding wire 7b (27b) is connected, on which the second line conductor 6b (26b) is extended.
And the conductor layer 16b or the conductor layer 26d was formed. Further, in FIG. 7E, a through hole 26e is provided between the side where the high resistance portion 28 and the bonding wire 27b are connected and the side surface of the circuit board 26 on the opposite side, and a conductor layer is formed on the inner surface of the through hole 26e. As a result, the second line conductor 26b was electrically connected to the ground conductor layer 26c-B on the lower surface of the circuit board 26.

【0046】各解析モデルでは、半導体素子5の終端用
電極の両脇に接地用電極が設けられているものについて
モデル化しているため、その接地用電極にボンディング
ワイヤ7b(27b)を介して接続される接地電極層
を、回路基板6−B(26−B)の上面の縁部で第2の
線路導体6b(26b)の両側に形成した。その接地電
極層は、回路基板6(26)の側面に設けられた配線導
体を介して接地導体層6c−Bに電気的に接続されるよ
うにした。
In each analysis model, the grounding electrode is provided on both sides of the termination electrode of the semiconductor element 5, so that the grounding electrode is connected via the bonding wire 7b (27b). The ground electrode layer is formed on both sides of the second line conductor 6b (26b) at the edge of the upper surface of the circuit board 6-B (26-B). The ground electrode layer was electrically connected to the ground conductor layer 6c-B via a wiring conductor provided on the side surface of the circuit board 6 (26).

【0047】また各解析モデルにおける、基体1(1
1)の材質はFe−Ni−Co合金、枠体2(22)の
材質はFe−Ni−Co合金、ボンディングワイヤ7b
(27b)の材質はAuであり、それぞれ同様の材質か
ら成るものとし、回路基板6−B(26−B)、第2の
線路導体6b(26b)、切欠き部16、接地電極層お
よび同一面接地導体層17の詳細な寸法は、それぞれ図
7(a)〜(f)に示す通りとした(単位はmm)。こ
れらの解析モデルに対し、0〜20GHzの周波数帯域
について、第2の線路導体6b(26b)を伝送する終
端用信号の反射損失をシミュレーションにより求めた。
In each analysis model, the substrate 1 (1
The material of 1) is a Fe-Ni-Co alloy, the material of the frame 2 (22) is a Fe-Ni-Co alloy, and the bonding wire 7b.
The material of (27b) is Au, which is made of the same material, and is the same as that of the circuit board 6-B (26-B), the second line conductor 6b (26b), the cutout portion 16, the ground electrode layer, and the same. The detailed dimensions of the surface ground conductor layer 17 are as shown in FIGS. 7A to 7F (unit: mm). With respect to these analysis models, the reflection loss of the termination signal transmitted through the second line conductor 6b (26b) was obtained by simulation in the frequency band of 0 to 20 GHz.

【0048】図8は各解析モデルの反射損失のグラフで
ある。同図において、モデルAとモデルBとの比較を行
なうと、周波数が5〜20GHzの場合、従来のモデル
Bに比べ、本発明のモデルAで切欠き部16の幅W=
1.0mm,2.0mmにおいて反射損失が改善されて
いることがわかる。
FIG. 8 is a graph of the reflection loss of each analytical model. In the figure, comparing the model A and the model B, when the frequency is 5 to 20 GHz, the width W of the cutout portion 16 in the model A of the present invention is W =
It can be seen that the reflection loss is improved at 1.0 mm and 2.0 mm.

【0049】モデルAとモデルBの解析結果の比較にお
いて、各解析モデルを構成する各部材は、それぞれ同様
の材質から成っており、第2の線路導体6b(26b)
部、接地導体層6c(26c)部、導体層6d(26
d)部および高抵抗部8(28)に起因する伝送損失は
同じとみなせることから、各解析モデルの伝送損失の違
いは、切欠き部16と切欠き部16内面の導体層16b
の有無、切欠き部16の幅Wに基づくものとみなせる。
In the comparison of the analysis results of the model A and the model B, each member constituting each analysis model is made of the same material, and the second line conductor 6b (26b)
Part, ground conductor layer 6c (26c) part, conductor layer 6d (26
Since the transmission loss due to the d) portion and the high resistance portion 8 (28) can be regarded as the same, the difference in the transmission loss between the analysis models is that the cutout portion 16 and the conductor layer 16b on the inner surface of the cutout portion 16 are different.
It can be considered that it is based on the presence or absence and the width W of the cutout portion 16.

【0050】従って、本発明のモデルAで切欠き部16
の幅WがW=1.0mm,2.0mmの場合は、従来の
モデルBに比べ、5〜20GHzの反射特性に優れた良
好な信号線路を構成することがわかった。これは、切欠
き部16と切欠き部16内面に導体層16bを設けるこ
とによって、第2の線路導体6bを伝送する終端用信号
のうち高抵抗部8において電気エネルギーから熱エネル
ギーに変換しきれないものを、導体層16bで枠体2に
向けて放射させることにより終端用信号を確実に接地さ
せて、第2の線路導体6bの他端での終端用信号の反射
を減少できたためである。ここで、切欠き部16の幅が
W=0.5mmの場合、切欠き部16の幅が狭く終端用
信号を放射させる機能を十分発揮できず、反射特性を改
善できなかったものと考えられる。
Therefore, in the model A of the present invention, the notch 16
It was found that, when the width W of W is 1.0 mm and 2.0 mm, a good signal line having excellent reflection characteristics of 5 to 20 GHz is formed as compared with the conventional model B. This is because, by providing the cutout portion 16 and the conductor layer 16b on the inner surface of the cutout portion 16, the electrical energy in the high resistance portion 8 of the termination signal transmitted through the second line conductor 6b can be completely converted into thermal energy. This is because the terminating signal can be reliably grounded by radiating the non-existing one toward the frame body 2 by the conductor layer 16b, and the reflection of the terminating signal at the other end of the second line conductor 6b can be reduced. . Here, when the width of the cutout portion 16 is W = 0.5 mm, it is considered that the width of the cutout portion 16 was small and the function of radiating the termination signal could not be sufficiently exerted, and the reflection characteristics could not be improved. .

【0051】このことから、終端用信号を放射させる機
能を発揮させるためには、切欠き部16の幅を適切な大
きさとする必要がある。図8の結果より、切欠き部16
の幅Wが広い場合に反射特性が良いと考えられ、線路導
体6bの幅以上であるのが好ましいことが判った。
Therefore, in order to exert the function of radiating the termination signal, it is necessary to make the width of the notch 16 appropriate. From the result of FIG. 8, the notch 16
It is considered that the reflection characteristic is good when the width W is wide, and it is preferable that the width W is not less than the width of the line conductor 6b.

【0052】また、本発明のモデルAで切欠き部16の
幅WがW=0.5mmの場合と比較例の構成のモデルC
とを比較すると、モデルAの反射特性が優れていた。こ
れは、回路基板6−B(26−B)上面の第2の線路導
体6b(26b)と下面の接地導体層6c−B(26c
−B)との電気的接続は、内面に導体層を設けた貫通孔
26eによって行なうよりも、内面に導体層16bを設
けた切欠き部16を介して行なう方が良く、導体層16
bが終端用信号を放射させて反射特性を改善できたと考
えられる。
Further, in the model A of the present invention, the width W of the notch portion 16 is W = 0.5 mm, and the model C of the configuration of the comparative example.
When compared with, the reflection characteristics of the model A were excellent. This is because the second line conductor 6b (26b) on the upper surface of the circuit board 6-B (26-B) and the ground conductor layer 6c-B (26c) on the lower surface.
-B) is electrically connected to the conductor layer 16 through the notch 16 having the conductor layer 16b on the inner surface, rather than through the through hole 26e having the conductor layer on the inner surface.
It is considered that b emitted the terminating signal to improve the reflection characteristic.

【0053】また、本発明のモデルDは、モデルAの切
欠き部16の幅WをW=2.0mmとしたモデルにおい
て、回路基板6−B上面の略全周に第2の線路導体6b
を取り囲むように形成されるとともに第2の線路導体6
bの他端側に接続された同一面接地導体層17を設けた
ものであり、モデルA以上に反射特性が改善された。
In the model D of the present invention, in the model A in which the width W of the cutout portion 16 is W = 2.0 mm, the second line conductor 6b is formed substantially all around the upper surface of the circuit board 6-B.
Is formed so as to surround the second line conductor 6
The ground plane conductor layer 17 connected to the other end side of b is provided, and the reflection characteristic is improved more than the model A.

【0054】これは、第2の線路導体6bの他端で、第
2の線路導体6bを伝送する終端用信号を接地させるた
めの接地導体層6c−Bの面積を拡大でき、第2の線路
導体6bから接地導体層6c−Bに向けての終端用信号
の伝送をスムーズに行なうことができ、他端における終
端用信号の反射を減少させることができたためと考えら
れる。また、同一面接地導体層17により、第2の線路
導体6bから同一面接地導体層17に終端用信号を空間
および間隙を介して短絡させることができ、第2の線路
導体6bにおいて終端用信号を減衰させて確実に接地さ
せることができたためであると考えられる。さらに、第
2の線路導体6bに設けられた高抵抗部8で接地しきれ
ない終端用信号を同一面接地導体層17において枠体2
に向けて放射させることにより、終端用信号をより確実
に接地させることができたためと考えられる。
This makes it possible to increase the area of the ground conductor layer 6c-B for grounding the terminating signal transmitted through the second line conductor 6b at the other end of the second line conductor 6b. It is considered that the termination signal could be smoothly transmitted from the conductor 6b to the ground conductor layer 6c-B, and the reflection of the termination signal at the other end could be reduced. Further, the same-plane grounding conductor layer 17 can short-circuit the terminating signal from the second line conductor 6b to the same-plane grounding conductor layer 17 through a space and a gap, and the second line conductor 6b can terminate the terminating signal. It is thought that this is because the ground was attenuated and could be reliably grounded. Further, a termination signal that cannot be grounded by the high resistance portion 8 provided in the second line conductor 6b is provided in the frame body 2 in the same-plane grounding conductor layer 17.
It is considered that the terminating signal could be grounded more reliably by radiating the signal toward the terminal.

【0055】上述のように終端用信号を確実に接地する
ことで、モデルDが終端用信号の最も良好な反射特性を
有すると考えられる。このような、終端用信号を確実に
接地することによる反射特性の向上は終端用信号の周波
数が高くなるほど重要である。
By reliably grounding the termination signal as described above, it is considered that the model D has the best reflection characteristic of the termination signal. The improvement of the reflection characteristics by surely grounding the termination signal is more important as the frequency of the termination signal becomes higher.

【0056】なお、本発明は上記実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲内であれば
種々の変更は可能である。
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention.

【0057】[0057]

【発明の効果】本発明は、半導体パッケージ内面の棚部
に載置された回路基板は、その上面に一端が半導体素子
に電気的に接続され他端が上面の周縁部に達していると
ともに途中に高抵抗部を設けた接地用の線路導体が形成
され、下面に接地導体層が形成されており、側面に上下
面を貫通するとともに上面側開口に線路導体の他端が達
している切欠き部が形成されており、かつ切欠き部の内
面に線路導体の他端と接地導体層とを電気的に接続する
導体層が形成されていることにより、線路導体を伝送す
る終端用信号のうち高抵抗部で電気エネルギーから熱エ
ネルギーに変換しきれないものを、切欠き部の内面に形
成された導体層で枠体に向けて放射させることにより、
終端用信号を確実に接地させることができ、線路導体の
他端における終端用信号の高周波信号成分の反射を有効
に減少させることができる。
As described above, according to the present invention, the circuit board placed on the shelf of the inner surface of the semiconductor package has one end electrically connected to the semiconductor element on the upper surface and the other end reaching the peripheral portion of the upper surface. A line conductor for grounding with a high resistance part is formed on the ground conductor layer, and a ground conductor layer is formed on the lower surface.The notch cuts through the upper and lower surfaces of the side surface and the other end of the line conductor reaches the upper opening. Of the terminating signal transmitted through the line conductor by forming the portion and forming the conductor layer electrically connecting the other end of the line conductor and the ground conductor layer on the inner surface of the cutout portion. By radiating what cannot be converted from electrical energy to thermal energy in the high resistance part toward the frame by the conductor layer formed on the inner surface of the cutout part,
The termination signal can be reliably grounded, and the reflection of the high-frequency signal component of the termination signal at the other end of the line conductor can be effectively reduced.

【0058】本発明は、好ましくは切欠き部が線路導体
よりも幅広であるようにすることにより、高抵抗部で電
気的に接地しきれない終端用信号を、切欠き部の内面の
導体層で枠体に向けて放射させ易くすることによって、
終端用信号をより確実に接地させることができる。
According to the present invention, preferably, the notch portion is wider than the line conductor, so that a termination signal which cannot be electrically grounded in the high resistance portion can be provided on the inner conductor layer of the notch portion. By making it easier to radiate toward the frame,
The terminal signal can be grounded more reliably.

【0059】また好ましくは、回路基板の上面に線路導
体を取り囲むように形成されるとともに線路導体の他端
側に接続された同一面接地導体層が形成されることによ
り、線路導体の他端において終端用信号を接地させるた
めの接地導体層の面積を拡大できるため、線路導体から
接地導体層に向けての終端用信号の伝送をスムーズに行
なうことができ、線路導体の他端における終端用信号の
高周波信号成分の反射を有効に減少させ得る。また、線
路導体から同一面接地導体層に終端用信号の高周波信号
成分を空間および間隙を介して短絡させることができ、
線路導体において終端用信号を減衰させてより確実に接
地することができる。さらに、線路導体に設けられた高
抵抗部で接地しきれない終端用信号を同一面接地導体層
で枠体に向けて放射させることによって、終端用信号を
より確実に接地させ得る。
Further, preferably, the same-plane ground conductor layer is formed on the upper surface of the circuit board so as to surround the line conductor and is connected to the other end side of the line conductor, so that the other end of the line conductor is formed. Since the area of the ground conductor layer for grounding the termination signal can be increased, the termination signal can be smoothly transmitted from the line conductor to the ground conductor layer, and the termination signal at the other end of the line conductor can be transmitted. Can effectively reduce the reflection of the high frequency signal component of. In addition, the high frequency signal component of the termination signal can be short-circuited from the line conductor to the same-plane ground conductor layer through a space and a gap,
The termination signal can be attenuated in the line conductor and grounded more reliably. Further, the termination signal, which cannot be grounded at the high resistance portion provided in the line conductor, is radiated toward the frame body in the same-plane grounding conductor layer, so that the termination signal can be grounded more reliably.

【0060】従って、線路導体を伝送する終端用信号の
高周波信号成分によって反射によるノイズが発生しその
ノイズが半導体素子に入り込むのを防止し、半導体素子
を正常に作動させることが可能となる。
Therefore, it is possible to prevent noise due to reflection from being generated by the high frequency signal component of the terminating signal transmitted through the line conductor and prevent the noise from entering the semiconductor element, and to operate the semiconductor element normally.

【0061】本発明の半導体装置は、本発明の半導体素
子収納用パッケージと、棚部に載置された回路基板と、
載置部に載置されるとともに回路基板の線路導体の一端
に電気的に接続された半導体素子と、枠体の上面に接合
された蓋体とを具備したことにより、上記本発明の作用
効果を有する半導体パッケージを用いた信頼性の高いも
のとなる。
A semiconductor device of the present invention comprises a package for accommodating a semiconductor element of the present invention, a circuit board placed on a shelf,
Since the semiconductor element mounted on the mounting portion and electrically connected to one end of the line conductor of the circuit board and the lid body joined to the upper surface of the frame body are provided, the above-mentioned effects of the present invention A highly reliable semiconductor package using

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体パッケージについて実施の形態
の例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor package of the present invention.

【図2】本発明の半導体パッケージ内に収容された回路
基板の要部拡大平面図である。
FIG. 2 is an enlarged plan view of an essential part of a circuit board housed in a semiconductor package of the present invention.

【図3】本発明の半導体パッケージ内に収容された回路
基板の要部拡大平面図である。
FIG. 3 is an enlarged plan view of an essential part of a circuit board housed in a semiconductor package of the present invention.

【図4】従来の半導体パッケージの断面図である。FIG. 4 is a sectional view of a conventional semiconductor package.

【図5】従来の半導体パッケージ内に収容された回路基
板の要部拡大平面図である。
FIG. 5 is an enlarged plan view of an essential part of a circuit board housed in a conventional semiconductor package.

【図6】従来の半導体パッケージ内に収容された回路基
板の要部拡大平面図である。
FIG. 6 is an enlarged plan view of an essential part of a circuit board housed in a conventional semiconductor package.

【図7】(a)〜(c),(f)は本発明の半導体パッ
ケージの回路基板の各実施例を示し、(d),(e)は
比較例の半導体パッケージにおける回路基板の各例を示
すものであり、(a)は本発明の回路基板の解析モデル
(モデルA)の平面図、(b)は本発明の回路基板の解
析モデル(モデルAの他の例)の平面図、(c)は本発
明の回路基板の解析モデル(モデルAの他の例)の平面
図、(d)は比較例の回路基板の解析モデル(モデル
B)の平面図、(e)は比較例の回路基板の解析モデル
(モデルC)の平面図、(f)は本発明の回路基板の解
析モデル(モデルD)の平面図である。
7A to 7C show examples of the circuit board of the semiconductor package of the present invention, and FIGS. 7D to 7E show examples of the circuit board of the semiconductor package of the comparative example. FIG. 5A is a plan view of an analysis model (model A) of the circuit board of the present invention, and FIG. 9B is a plan view of an analysis model of the circuit board of the present invention (another example of the model A). (C) is a plan view of an analysis model (another example of model A) of a circuit board of the present invention, (d) is a plan view of an analysis model (model B) of a circuit board of a comparative example, and (e) is a comparative example. 3A is a plan view of an analysis model (model C) of the circuit board of FIG. 4F is a plan view of the analysis model (model D) of the circuit board of the present invention.

【図8】図7のモデルA〜Dについて反射損失の解析結
果を示すグラフである。
8 is a graph showing the analysis results of reflection loss for models A to D in FIG.

【符号の説明】[Explanation of symbols]

1:基体 1a:載置部 2:枠体 2b:棚部 4:蓋体 5:半導体素子 6:回路基板 6b:第2の線路導体 6c:接地導体層 8:高抵抗部 16:切欠き部 16b:導体層 17:同一面接地導体層 1: Base 1a: Placement part 2: Frame body 2b: Shelf 4: Lid 5: Semiconductor element 6: Circuit board 6b: Second line conductor 6c: Ground conductor layer 8: High resistance part 16: Notch 16b: conductor layer 17: Same-plane ground conductor layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 上側主面に半導体素子を載置するための
載置部を有する基体と、前記上側主面の外周部に前記載
置部を囲繞するように接合され、内面に回路基板を載置
するための棚部を有する枠体とを具備した半導体素子収
納用パッケージにおいて、前記回路基板は、その上面に
一端が前記半導体素子に電気的に接続され他端が前記上
面の縁部に達しておりかつ途中に高抵抗部を設けた接地
用の線路導体が形成され、下面に接地導体層が形成され
ており、側面に上下面を貫通するとともに上面側開口に
前記線路導体の他端が達している切欠き部が形成されて
おり、かつ該切欠き部の内面に前記線路導体の他端と前
記接地導体層とを電気的に接続する導体層が形成されて
いることを特徴とする半導体素子収納用パッケージ。
1. A base body having a mounting portion for mounting a semiconductor element on an upper main surface, and an outer peripheral portion of the upper main surface are joined to surround the mounting portion, and a circuit board is provided on an inner surface. In a package for housing a semiconductor element, which comprises a frame having a shelf for mounting, the circuit board has one end electrically connected to the semiconductor element on an upper surface and the other end on an edge portion of the upper surface. A line conductor for grounding, which has reached a high resistance part in the middle, is formed, and a ground conductor layer is formed on the lower surface, which penetrates the upper and lower surfaces on the side surface and the other end of the line conductor on the upper surface side opening. Is formed, and a conductor layer for electrically connecting the other end of the line conductor and the ground conductor layer is formed on the inner surface of the notch. Package for semiconductor device storage.
【請求項2】 前記切欠き部は前記線路導体よりも幅広
であることを特徴とする請求項1記載の半導体素子収納
用パッケージ。
2. The package for accommodating a semiconductor element according to claim 1, wherein the cutout portion is wider than the line conductor.
【請求項3】 前記回路基板の上面に前記線路導体を取
り囲むように形成されるとともに前記線路導体の他端側
に接続された同一面接地導体層が形成されていることを
特徴とする請求項1または請求項2記載の半導体素子収
納用パッケージ。
3. The same-plane ground conductor layer is formed on the upper surface of the circuit board so as to surround the line conductor and is connected to the other end of the line conductor. The package for housing a semiconductor device according to claim 1 or 2.
【請求項4】 請求項1〜3のいずれかに記載の半導体
素子収納用パッケージと、前記棚部に載置された前記回
路基板と、前記載置部に載置されるとともに前記回路基
板の前記線路導体の一端に電気的に接続された前記半導
体素子と、前記枠体の上面に接合された蓋体とを具備し
たことを特徴とする半導体装置。
4. The package for housing a semiconductor element according to claim 1, the circuit board mounted on the shelf, and the circuit board mounted on the mounting part. A semiconductor device comprising: the semiconductor element electrically connected to one end of the line conductor; and a lid body joined to an upper surface of the frame body.
JP2001193746A 2001-06-26 2001-06-26 Semiconductor element storage package and semiconductor device Expired - Fee Related JP3652279B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001193746A JP3652279B2 (en) 2001-06-26 2001-06-26 Semiconductor element storage package and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001193746A JP3652279B2 (en) 2001-06-26 2001-06-26 Semiconductor element storage package and semiconductor device

Publications (2)

Publication Number Publication Date
JP2003007883A true JP2003007883A (en) 2003-01-10
JP3652279B2 JP3652279B2 (en) 2005-05-25

Family

ID=19031970

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3652279B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319645A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device
JP2002319644A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125903A (en) * 1990-09-17 1992-04-27 Hirose Electric Co Ltd Termination resistor for high frequency
JPH04188652A (en) * 1990-11-19 1992-07-07 Shinko Electric Ind Co Ltd High frequency element package and manufacture thereof
JPH06318804A (en) * 1993-05-10 1994-11-15 Mitsubishi Electric Corp Resistive terminator
JPH08279704A (en) * 1995-04-04 1996-10-22 Advantest Corp Resistance element for termination
JPH1174705A (en) * 1997-08-29 1999-03-16 Oki Electric Ind Co Ltd Microwave circuit
JP2000349179A (en) * 1999-06-03 2000-12-15 Sumitomo Metal Electronics Devices Inc Structure of package for high-frequency device
JP2000357755A (en) * 1999-06-15 2000-12-26 Sumitomo Metal Electronics Devices Inc Package for high-frequency device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04125903A (en) * 1990-09-17 1992-04-27 Hirose Electric Co Ltd Termination resistor for high frequency
JPH04188652A (en) * 1990-11-19 1992-07-07 Shinko Electric Ind Co Ltd High frequency element package and manufacture thereof
JPH06318804A (en) * 1993-05-10 1994-11-15 Mitsubishi Electric Corp Resistive terminator
JPH08279704A (en) * 1995-04-04 1996-10-22 Advantest Corp Resistance element for termination
JPH1174705A (en) * 1997-08-29 1999-03-16 Oki Electric Ind Co Ltd Microwave circuit
JP2000349179A (en) * 1999-06-03 2000-12-15 Sumitomo Metal Electronics Devices Inc Structure of package for high-frequency device
JP2000357755A (en) * 1999-06-15 2000-12-26 Sumitomo Metal Electronics Devices Inc Package for high-frequency device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002319645A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device
JP2002319644A (en) * 2001-04-20 2002-10-31 Kyocera Corp Package for housing semiconductor element and semiconductor device

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