JP4164011B2 - Semiconductor element storage package and semiconductor device - Google Patents

Semiconductor element storage package and semiconductor device Download PDF

Info

Publication number
JP4164011B2
JP4164011B2 JP2003303724A JP2003303724A JP4164011B2 JP 4164011 B2 JP4164011 B2 JP 4164011B2 JP 2003303724 A JP2003303724 A JP 2003303724A JP 2003303724 A JP2003303724 A JP 2003303724A JP 4164011 B2 JP4164011 B2 JP 4164011B2
Authority
JP
Japan
Prior art keywords
line conductor
semiconductor element
conductor
circuit board
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003303724A
Other languages
Japanese (ja)
Other versions
JP2005072507A (en
Inventor
義信 澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003303724A priority Critical patent/JP4164011B2/en
Publication of JP2005072507A publication Critical patent/JP2005072507A/en
Application granted granted Critical
Publication of JP4164011B2 publication Critical patent/JP4164011B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Semiconductor Lasers (AREA)

Description

本発明は、高周波信号で作動する半導体素子を収納するための半導体素子収納用パッケージに関する。   The present invention relates to a semiconductor element housing package for housing a semiconductor element that operates with a high-frequency signal.

従来、マイクロ波帯やミリ波帯等の高周波信号を用いる各種半導体素子を収納する半導体素子収納用パッケージ(以下、単にパッケージともいう)には、半導体素子を電気的に接続するための導体パターンとしての線路導体が設けられている。このようなパッケージの断面図を図3(a)に、および平面図を図3(b)に示す。同図において、31は基体、32は金属製の枠体、34は蓋体、36は回路基板である。   2. Description of the Related Art Conventionally, a semiconductor element storage package (hereinafter also simply referred to as a package) for storing various semiconductor elements using high-frequency signals such as a microwave band and a millimeter wave band is used as a conductor pattern for electrically connecting the semiconductor elements. Line conductors are provided. A sectional view of such a package is shown in FIG. 3A, and a plan view is shown in FIG. In the figure, 31 is a base, 32 is a metal frame, 34 is a lid, and 36 is a circuit board.

基体31は鉄(Fe)−ニッケル(Ni)−コバルト(Co)合金や銅(Cu)−タングステン(W)等の金属から成る四角形状の板状体であり、その上側主面の中央部には、IC,LSI,半導体レーザ(LD),フォトダイオード(PD)等の半導体素子35を搭載して成る回路基板36が搭載されている。回路基板36は、例えばアルミナ(Al)質焼結体,窒化アルミニウム(AlN)質焼結体,ムライト(3Al−2SiO)質焼結体等のセラミックスから成り、上面の中央部に半導体素子35を載置するための載置部31aを有している。 The base 31 is a rectangular plate-shaped body made of a metal such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy or copper (Cu) -tungsten (W), and is formed at the center of the upper main surface. A circuit board 36 on which a semiconductor element 35 such as an IC, LSI, semiconductor laser (LD), photodiode (PD) or the like is mounted is mounted. The circuit board 36 is made of ceramics such as alumina (Al 2 O 3 ) sintered body, aluminum nitride (AlN) sintered body, mullite (3Al 2 O 3 -2SiO 2 ) sintered body, and the like. A mounting portion 31a for mounting the semiconductor element 35 is provided at the center.

回路基板36の下面には、接地導体層36dが被着されており、銀(Ag)ろう,Ag−銅(Cu)ろう等のろう材や半田によって接地導体層36dと基体31とが強固に接着固定される。   A ground conductor layer 36d is deposited on the lower surface of the circuit board 36, and the ground conductor layer 36d and the base 31 are firmly bonded by a brazing material such as silver (Ag) brazing, Ag-copper (Cu) brazing, or solder. Bonded and fixed.

回路基板36の載置部31aに載置された半導体素子35は、その電極が回路基板36に被着されている第1の線路導体36aおよび第2の線路導体36bにそれぞれボンディングワイヤ37a,37bを介して電気的に接続されている。   The semiconductor element 35 mounted on the mounting portion 31a of the circuit board 36 is bonded to the first line conductor 36a and the second line conductor 36b whose electrodes are attached to the circuit board 36, respectively. It is electrically connected via.

さらに、第2の線路導体36bと接地導体36cとは、高抵抗体38を介して終端接続されており、接地導体36cは端面の接地導体36eを介して接地導体層36dに接続されている。このように第2の線路導体36bの終端を高抵抗体38を介して接地導体36cに接続することにより、第2の線路導体36bに流れる終端用信号としての高周波信号の反射を防ぎ、半導体素子35が誤動作するのを防いでいる。   Further, the second line conductor 36b and the ground conductor 36c are terminated and connected via a high resistance 38, and the ground conductor 36c is connected to the ground conductor layer 36d via a ground conductor 36e on the end face. By connecting the end of the second line conductor 36b to the ground conductor 36c via the high resistance 38 in this way, reflection of a high-frequency signal as a termination signal flowing through the second line conductor 36b is prevented, and the semiconductor element 35 prevents malfunctioning.

基体31の上側主面の外周部には回路基板36を囲繞するようにして枠体32が立設されており、枠体32は基体31とともにその内側に半導体素子35を収容する空所を形成する。枠体32は基体31と同様にFe−Ni−Co合金やCu−Wの焼結材等から成り、基体31と一体成形されるか、または基体31にAgろう,Ag−Cuろう等のろう材を介してろう付けされるか、またはシーム溶接法等の溶接法により接合されることによって、基体31の上側主面の外周部に立設される。   A frame body 32 is erected on the outer peripheral portion of the upper main surface of the base body 31 so as to surround the circuit board 36. The frame body 32 forms a space for housing the semiconductor element 35 along with the base body 31. To do. The frame 32 is made of an Fe—Ni—Co alloy, a sintered material of Cu—W, or the like, similar to the base 31, and is formed integrally with the base 31, or is brazed to the base 31 such as Ag solder, Ag—Cu solder, or the like. It is erected on the outer peripheral portion of the upper main surface of the base 31 by being brazed through a material or joined by a welding method such as a seam welding method.

枠体32の側面にはグラスビーズ33が嵌着される貫通孔32aが形成されており、貫通孔32a内にグラスビーズ33を嵌め込むとともに半田等の封着材を貫通孔32a内の隙間に挿入し、しかる後、加熱して封着材を溶融させ、溶融した封着材を毛細管現象によりグラスビーズ33と貫通孔32aの内壁との隙間に充填させることによって、グラスビーズ33が貫通孔32a内に封着材を介して嵌着接合される。   A through hole 32a into which the glass beads 33 are fitted is formed on the side surface of the frame 32. The glass beads 33 are fitted into the through holes 32a and a sealing material such as solder is placed in the gaps in the through holes 32a. The glass beads 33 are inserted into the through holes 32a by heating and melting the sealing material and filling the melted sealing material into the gap between the glass beads 33 and the inner walls of the through holes 32a by capillary action. It is fitted and joined through a sealing material.

グラスビーズ33には、中心軸部分に信号線路としてFe−Ni−Co合金等の金属から成る棒状の中心導体33aが固定されている。中心導体33aは半田等から成る導電性接着材を介して回路基板36の第1の線路導体36aに電気的に接続される。このグラスビーズ33には、外部電気回路(図示せず)に接続された同軸ケーブル(図示せず)が装着されることによって、内部に収納された半導体素子35がグラスビーズ33の中心導体33aを介して外部電気回路に電気的に接続されることとなる。   A rod-shaped center conductor 33a made of a metal such as an Fe—Ni—Co alloy is fixed to the glass bead 33 as a signal line at the center axis portion. The center conductor 33a is electrically connected to the first line conductor 36a of the circuit board 36 through a conductive adhesive made of solder or the like. A coaxial cable (not shown) connected to an external electric circuit (not shown) is attached to the glass bead 33, so that the semiconductor element 35 housed therein can connect the central conductor 33a of the glass bead 33. Through the external electric circuit.

最後に、基体31および枠体32から成る容器内部に半導体素子35を収容し、枠体32の上面に蓋体34をろう付け法やシームウエルド法等の溶接法により接合し、容器内部を気密に封止することによって製品としての半導体装置となる。
特開1999-38372号公報
Finally, the semiconductor element 35 is accommodated inside the container composed of the base body 31 and the frame body 32, and the lid body 34 is joined to the upper surface of the frame body 32 by a welding method such as a brazing method or a seam weld method. By being sealed in, a semiconductor device as a product is obtained.
JP 1999-38372

しかしながら、従来の半導体パッケージにおいては、半導体素子35の高周波化が進むにつれ、第2の線路導体36bおよび接地導体36c間に形成される高抵抗体38の抵抗値のバラツキが原因となって、高抵抗体38での高周波信号の反射によるノイズが発生し、そのノイズが半導体素子35内に入り込んで、半導体素子35の誤動作を発生させるといった問題点が発生していた。   However, in the conventional semiconductor package, as the frequency of the semiconductor element 35 is increased, the resistance value of the high resistor 38 formed between the second line conductor 36b and the ground conductor 36c is increased. There has been a problem that noise is generated due to reflection of the high-frequency signal at the resistor 38, and the noise enters the semiconductor element 35, causing malfunction of the semiconductor element 35.

また、マイクロ波帯やミリ波帯等の高周波信号においては、高抵抗体38から接地導体層36dまでに形成される接地導体36c,36eの寄生インダクタンス成分によって、高抵抗体38から見たインピーダンス値が変動し、高抵抗体38が所望の終端特性を得られないという新たな問題が発生してきた。   In addition, in a high frequency signal such as a microwave band and a millimeter wave band, an impedance value viewed from the high resistance 38 due to a parasitic inductance component of the ground conductors 36c and 36e formed from the high resistance 38 to the ground conductor layer 36d. As a result, there has been a new problem that the high resistance 38 cannot obtain the desired termination characteristics.

さらに、第2の線路導体36b上で、定在波により共振が発生し、所望の終端特性が得られないといった問題点も発生してきた。   In addition, resonance has occurred on the second line conductor 36b due to the standing wave, and the desired termination characteristics cannot be obtained.

本発明は上記問題点に鑑み完成されたものであり、その目的は、半導体素子へ高周波信号の反射成分が入り込んで半導体素子が誤作動を起こすのを防ぐことができる、信頼性の高い半導体素子収納用パッケージおよびこれを用いた半導体装置を提供することにある。   The present invention has been completed in view of the above problems, and an object of the present invention is to provide a highly reliable semiconductor device capable of preventing a semiconductor component from malfunctioning due to a reflection component of a high-frequency signal entering the semiconductor device. An object is to provide a storage package and a semiconductor device using the same.

本発明の半導体素子収納用パッケージは、上側主面に高周波信号で駆動される半導体素子を載置するための載置部を有する回路基板と、上面の中央部に前記回路基板が搭載された基体と、該基体の上面の外周部に前記回路基板を囲繞するように接合された枠体とを具備しており、前記回路基板の前記上側主面に、前記載置部の周縁部から外周に向かって形成された線路導体と、該線路導体の両側および前記外周側の一端を一定間隔をもって取り囲む同一面接地導体と、前記線路導体の前記外周側の一端部の両側に接続されるとともに、前記線路導体の線路方向に対して対称に斜め方向に延出して前記同一面接地導体に接続される2本の高抵抗体とが形成されており、前記線路導体の前記載置部側の他端と前記高抵抗体との距離が前記高周波信号の波長の1/2未満であることを特徴とする。   A package for housing a semiconductor element according to the present invention includes a circuit board having a mounting portion for mounting a semiconductor element driven by a high-frequency signal on an upper main surface, and a base on which the circuit board is mounted at the center of the upper surface. And a frame joined to the outer peripheral portion of the upper surface of the base body so as to surround the circuit board, and on the upper main surface of the circuit board, from the peripheral portion of the mounting portion to the outer periphery. A line conductor formed toward the surface, a coplanar grounding conductor that surrounds both ends of the line conductor and the one end on the outer periphery side at a constant interval, and connected to both sides of the end portion on the outer periphery side of the line conductor, and The two other high-resistance elements that extend in an oblique direction symmetrical to the line direction of the line conductor and are connected to the same-surface ground conductor are formed, and the other end of the line conductor on the mounting portion side described above And a distance between the high-resistance element and the high-frequency signal Wherein the of less than half a wavelength.

本発明の半導体装置は、上記構成の半導体素子収納用パッケージと、前記載置部に載置されるとともに前記線路導体に電気的に接続された半導体素子と、前記枠体の上面に取着された蓋体とを具備していることを特徴とする。   The semiconductor device of the present invention is attached to the upper surface of the frame body, the semiconductor element storage package having the above-described configuration, the semiconductor element mounted on the mounting portion and electrically connected to the line conductor. And a lid.

本発明の半導体素子収納用パッケージによれば、回路基板の上側主面に、載置部の周縁部から外周に向かって形成された線路導体と、線路導体の両側および回路基板外周側の一端を一定間隔をもって取り囲む同一面接地導体と、線路導体の回路基板外周側の一端部の両側に接続されるとともに、線路導体の線路方向に対して対称に斜め方向に延出して同一面接地導体に接続される2本の高抵抗体とが形成されており、線路導体の載置部側の他端と高抵抗体との距離が高周波信号の波長の1/2未満であることから、高抵抗体をこの接地導体に配線で引き回すことなく直接、短い距離で接続することによって、高抵抗体から接地導体までの寄生インダクタンス成分や寄生キャパシタンス成分を低減することができる。このような寄生インダクタンス成分や寄生キャパシタンス成分は周波数に依存してインピーダンス値を変動させるため、高抵抗体から接地導体までの寄生インダクタンス成分や寄生キャパシタンス成分を低減できることにより線路導体の一端部に接続された高抵抗体から見た線路導体のインピーダンス値の変動を小さくすることができ、その結果、半導体素子の終端用電極に接続される線路導体について高周波帯域までも安定した終端特性を得ることが可能となる。   According to the package for housing a semiconductor element of the present invention, the line conductor formed on the upper main surface of the circuit board from the periphery of the mounting part toward the outer periphery, both sides of the line conductor and one end of the circuit board on the outer periphery side. Connected to both sides of the same-surface grounding conductor that surrounds with a certain interval and one end of the circuit board outer peripheral side of the line conductor, and extends in an oblique direction symmetrical to the line direction of the line conductor and connected to the same-surface grounding conductor The two high resistance bodies are formed, and the distance between the other end of the line conductor on the placement portion side and the high resistance body is less than ½ of the wavelength of the high frequency signal. By connecting directly to the ground conductor with a short distance without wiring, the parasitic inductance component and the parasitic capacitance component from the high resistance body to the ground conductor can be reduced. Since these parasitic inductance components and parasitic capacitance components change the impedance value depending on the frequency, they can be connected to one end of the line conductor by reducing the parasitic inductance components and parasitic capacitance components from the high resistance to the ground conductor. As a result, the line conductor connected to the termination electrode of the semiconductor element can have stable termination characteristics up to the high frequency band. It becomes.

さらに、線路導体の線路方向に対して対称に斜め方向に延出して同一面接地導体に接続される2本の高抵抗体が形成されているため、高抵抗体の1つ当りに要求される抵抗値のバラツキの範囲を緩和することができるとともに、高抵抗体に発生する寄生インダクタンス成分を低減することができるため、線路導体について高周波帯域まで使用可能な終端抵抗を得ることが可能となる。また、高抵抗体が線路導体の線路方向に対して斜め方向に延出しているので、線路導体から高抵抗体に滑らかに高周波信号を伝送させることが可能となり、線路導体と高抵抗体との境界で高周波信号が反射するのを有効に抑制することができる。   Furthermore, since two high resistance bodies that extend in a diagonal direction symmetrical to the line direction of the line conductors and are connected to the same surface ground conductor are formed, each high resistance body is required. Since the range of variation in resistance value can be relaxed and the parasitic inductance component generated in the high-resistance element can be reduced, it is possible to obtain a termination resistor that can be used up to the high-frequency band for the line conductor. Further, since the high resistance body extends in an oblique direction with respect to the line direction of the line conductor, it becomes possible to smoothly transmit a high-frequency signal from the line conductor to the high resistance body. It is possible to effectively suppress the reflection of the high frequency signal at the boundary.

さらにまた、線路導体の載置部側の他端と高抵抗体との距離が高周波信号の波長の1/2未満であることから、線路導体に高周波信号に対する共振現象が発生することを防ぐことができるため、使用周波数において共振現象が発生することがなく、使用周波数の高周波信号に対して良好な伝送特性を得ることが可能となる。   Furthermore, since the distance between the other end of the line conductor on the mounting portion side and the high resistance is less than ½ of the wavelength of the high-frequency signal, the line conductor is prevented from causing a resonance phenomenon with respect to the high-frequency signal. Therefore, a resonance phenomenon does not occur at the use frequency, and good transmission characteristics can be obtained for a high-frequency signal at the use frequency.

従って、本発明の半導体素子収納用パッケージは、以上のような構成により、線路導体を伝わる高周波信号の反射によるノイズや共振が発生することを防止し、半導体素子を正常に作動させることができる。   Therefore, the package for housing a semiconductor element of the present invention can prevent the occurrence of noise and resonance due to reflection of a high-frequency signal transmitted through the line conductor, and allow the semiconductor element to operate normally with the above configuration.

また、本発明の半導体装置によれば、上記構成の半導体素子収納用パッケージと、載置部に載置されるとともに線路導体に電気的に接続された半導体素子と、枠体の上面に取着された蓋体とを具備していることから、半導体素子へ高周波信号の反射成分が入り込んで半導体素子が誤作動を起こすのを防ぐことができる、伝送信頼性の高い半導体装置を提供することができる。   Further, according to the semiconductor device of the present invention, the semiconductor element storage package having the above configuration, the semiconductor element mounted on the mounting portion and electrically connected to the line conductor, and attached to the upper surface of the frame body Therefore, it is possible to provide a semiconductor device with high transmission reliability that can prevent a reflection component of a high-frequency signal from entering a semiconductor element and causing the semiconductor element to malfunction. it can.

本発明の半導体素子収納用パッケージについて以下に詳細に説明する。図1(a)は本発明の半導体素子収納用パッケージの実施の形態の一例を示す断面図であり、図1(b)は(a)の平面図である。これらの図において、1は基体、2は枠体、4は蓋体、6は回路基板である。   The semiconductor element storage package of the present invention will be described in detail below. FIG. 1A is a cross-sectional view showing an example of an embodiment of a package for housing a semiconductor element of the present invention, and FIG. 1B is a plan view of FIG. In these drawings, 1 is a base, 2 is a frame, 4 is a lid, and 6 is a circuit board.

基体1は、Fe−Ni−Co合金等の金属やCu−Wの焼結材等から成る四角形の板状体であり、そのインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法、または射出成形と切削加工等を施すことによって、所定の形状に製作される。基体1の上側主面の中央部には、IC,LSI,LD,PD等の半導体素子5を載置するための載置部1aを有する回路基板6が搭載されている。   The substrate 1 is a rectangular plate-like body made of a metal such as an Fe-Ni-Co alloy, a sintered material of Cu-W, or the like, and a conventionally well-known metal processing method such as rolling or punching on the ingot, or It is manufactured in a predetermined shape by performing injection molding and cutting. A circuit board 6 having a mounting portion 1a for mounting a semiconductor element 5 such as an IC, LSI, LD, or PD is mounted on the central portion of the upper main surface of the base 1.

回路基板6は、例えばAl質焼結体,AlN質焼結体,3Al−2SiO質焼結体等のセラミックスから成り、回路基板6の上面中央部には半導体素子5を載置するための載置部1aが形成されている。また、回路基板6の下面には接地導体層6dが被着形成されており、Agろう,Ag−Cuろう等のろう材やAu−Sn半田,Pb−Sn半田等の半田によって接地導体層6dと載置部1aとが強固に接着固定される。 The circuit board 6 is made of ceramics such as an Al 2 O 3 sintered body, an AlN sintered body, a 3Al 2 O 3 -2SiO 2 sintered body, and the semiconductor element 5 at the center of the upper surface of the circuit board 6. Is placed. Also, a ground conductor layer 6d is formed on the lower surface of the circuit board 6, and the ground conductor layer 6d is made of a brazing material such as Ag brazing or Ag-Cu brazing or solder such as Au-Sn solder or Pb-Sn solder. And the mounting portion 1a are firmly bonded and fixed.

半導体素子5は、その電極が回路基板6の上面に被着形成されている線路導体6a(以下、第1の線路導体という)および第線路導体6b(以下第2の線路導体という)にそれぞれボンディングワイヤ7a,7bを介して電気的に接続される。   The semiconductor element 5 is bonded to a line conductor 6a (hereinafter, referred to as a first line conductor) and a second line conductor 6b (hereinafter, referred to as a second line conductor), whose electrodes are deposited on the upper surface of the circuit board 6, respectively. They are electrically connected via wires 7a and 7b.

回路基板6は、例えばAl質焼結体から成る場合、以下のようにして作製される。まず、Al,酸化珪素(SiO),酸化カルシウム(CaO),酸化マグネシウム(MgO)等の原料粉末に適当な有機バインダや可塑剤,分散剤,溶剤等を添加混合して泥漿状となす。これを従来周知のドクターブレード法でシート状となすことによってセラミックグリーンシートを得る。しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施す、または、Al,SiO,CaO,MgO等の原料粉末を金型に充填しプレス成型することによって、所定の形状に成形する。そのセラミックグリーンシートに回路基板6上面の第1の線路導体6a,第2の線路導体6b,同一面接地導体6c、回路基板6端面の接地導体6e、回路基板6下面の接地導体層6dとなる金属ペーストを印刷塗布し、還元雰囲気中で約1600℃の温度で焼成することによって製作される。 When the circuit board 6 is made of, for example, an Al 2 O 3 sintered material, the circuit board 6 is manufactured as follows. First, a suitable organic binder, plasticizer, dispersant, solvent, etc. are added to and mixed with raw material powders such as Al 2 O 3 , silicon oxide (SiO 2 ), calcium oxide (CaO), magnesium oxide (MgO), etc. And A ceramic green sheet is obtained by making this into a sheet by a conventionally known doctor blade method. Thereafter, the ceramic green sheet is appropriately punched, or raw material powder such as Al 2 O 3 , SiO 2 , CaO, MgO is filled into a mold and press-molded to form a predetermined shape. . The ceramic green sheet becomes the first line conductor 6a, the second line conductor 6b on the upper surface of the circuit board 6, the same surface ground conductor 6c, the ground conductor 6e on the end surface of the circuit board 6, and the ground conductor layer 6d on the lower surface of the circuit board 6. It is manufactured by printing and applying a metal paste and firing at a temperature of about 1600 ° C. in a reducing atmosphere.

第1の線路導体6a,第2の線路導体6b,同一面接地導体6c,端面の接地導体6eおよび接地導体層6dとなる金属ペーストは、W,モリブデン(Mo),マンガン(Mn)等の高融点金属粉末に適当な有機バインダや溶剤を添加混合してペースト状となしたものを従来周知のスクリーン印刷法を採用して印刷することにより、セラミックグリーンシートまたはセラミックスの成形体に印刷塗布される。   The metal paste used for the first line conductor 6a, the second line conductor 6b, the same-surface ground conductor 6c, the ground conductor 6e on the end face, and the ground conductor layer 6d is made of a material such as W, molybdenum (Mo), manganese (Mn), etc. A paste made by adding a suitable organic binder or solvent to the melting point metal powder and then printing is applied to a ceramic green sheet or ceramic body by printing using a well-known screen printing method. .

なお、第1の線路導体6a,第2の線路導体6b,同一面接地導体6c,端面の接地導体6eおよび接地導体層6dは薄膜形成法によって形成されていても良く、その場合、第1の線路導体6a,第2の線路導体6b,同一面接地導体6c,端面の接地導体6eおよび接地導体層6dは、窒化タンタル(TaN),ニクロム(Ni−Cr合金),チタン(Ti),パラジウム(Pd),白金(Pt),Au等から形成され、セラミックグリーンシートを焼成した後に周知の薄膜形成法によって形成される。 The first line conductor 6a, the second line conductor 6b, the same-surface ground conductor 6c, the ground conductor 6e on the end surface, and the ground conductor layer 6d may be formed by a thin film forming method. The line conductor 6a, the second line conductor 6b, the coplanar ground conductor 6c, the ground conductor 6e on the end face, and the ground conductor layer 6d are tantalum nitride (Ta 2 N), nichrome (Ni—Cr alloy), titanium (Ti), It is made of palladium (Pd), platinum (Pt), Au or the like, and is formed by a well-known thin film forming method after firing the ceramic green sheet.

また、基体1の上側主面の外周部には回路基板6を囲繞するようにして枠体2が立設するように接合されており、枠体2は基体1とともにその内側に半導体素子5を収容する空所を形成する。この枠体2は、基体1と同様にFe−Ni−Co合金やCu−Wの焼結材等から成り、基体1と一体成形される、または基体1にAgろう等のろう材を介してろう付けされる、またはシーム溶接法等の溶接法により接合されることによって、基体1の上側主面の外周部に立設される。   Further, a frame body 2 is joined to the outer peripheral portion of the upper main surface of the base body 1 so as to surround the circuit board 6, and the frame body 2 and the base body 1 are provided with the semiconductor element 5 inside thereof. Forms a space to accommodate. The frame 2 is made of a Fe—Ni—Co alloy, a Cu—W sintered material, or the like, similar to the base 1, and is integrally formed with the base 1 or via a brazing material such as Ag brazing. By being brazed or joined by a welding method such as a seam welding method, the base body 1 is erected on the outer peripheral portion of the upper main surface.

なお、枠体2は上記のような金属から成るか、またはセラミックス等の誘電体材料から成っていてもよい。枠体2がセラミックスからなる場合、その表面にメタライズ層等の導体層が形成されているのが好ましい。このように枠体2を形成した場合には、内部の半導体素子5によって発生する放射ノイズまでも効果的に接地することができ、さらに半導体素子5の動作を安定化させることが可能となる。   The frame 2 may be made of the above metal or a dielectric material such as ceramics. When the frame 2 is made of ceramics, it is preferable that a conductor layer such as a metallized layer is formed on the surface thereof. When the frame body 2 is formed in this manner, even radiation noise generated by the internal semiconductor element 5 can be effectively grounded, and the operation of the semiconductor element 5 can be stabilized.

また、外部より半導体素子5に駆動信号等を入力させる入出力端子として、例えばグラスビーズ3が用いられ、以下のようにして枠体2に設置される。まず、枠体2の側面にグラスビーズ3が嵌着される貫通孔2aを形成し、貫通孔2a内にグラスビーズ3を嵌め込むとともにAu−Sn半田やPb−Sn半田等の封着材を貫通孔2aとの隙間に挿入する。しかる後、加熱して封着材を溶融させ、溶融した封着材を毛細管現象によりグラスビーズ3と貫通孔2aの内壁との隙間に充填することによって、グラスビーズ3が貫通孔2a内に半田等の封着材を介して嵌着接合される。   Further, as an input / output terminal for inputting a drive signal or the like to the semiconductor element 5 from the outside, for example, glass beads 3 are used and installed in the frame body 2 as follows. First, a through-hole 2a into which the glass beads 3 are fitted is formed on the side surface of the frame body 2, and the glass beads 3 are fitted into the through-holes 2a and a sealing material such as Au-Sn solder or Pb-Sn solder is used. It inserts in the clearance gap with the through-hole 2a. After that, the sealing material is melted by heating, and the molten sealing material is filled in the gap between the glass beads 3 and the inner walls of the through holes 2a by capillary action, so that the glass beads 3 are soldered into the through holes 2a. It is fitted and joined via a sealing material such as.

グラスビーズ3は、内部に収容する半導体素子5を外部電気回路に接続された同軸ケーブルに電気的に接続するものであり、Fe−Ni−Co合金等の金属から成る円筒形等の筒状の外周導体にガラス等の絶縁体が充填され、中心軸にFe−Ni−Co合金等の金属から成る中心導体3aが固定されて成る。この中心導体3aのパッケージ内側に位置する一端部は、半田等から成る導電性接着材を介して回路基板6の第1の線路導体6aに電気的に接続される。また、中心導体3aのパッケージ外側に位置する他端部に外部電気回路に接続された同軸ケーブルが装着される。そして、半導体素子5の電極と回路基板6の上面に形成された第1の線路導体6aとがボンディングワイヤ7aにより電気的に接続されることによって、パッケージの内部に収納された半導体素子5がグラスビーズ3の中心導体3aを介して外部電気回路に電気的に接続されることとなる。   The glass bead 3 is for electrically connecting the semiconductor element 5 accommodated therein to a coaxial cable connected to an external electric circuit, and has a cylindrical shape such as a cylindrical shape made of a metal such as an Fe—Ni—Co alloy. An outer conductor is filled with an insulator such as glass, and a central conductor 3a made of a metal such as an Fe-Ni-Co alloy is fixed to the central axis. One end portion of the center conductor 3a located inside the package is electrically connected to the first line conductor 6a of the circuit board 6 through a conductive adhesive made of solder or the like. A coaxial cable connected to an external electric circuit is attached to the other end portion of the center conductor 3a located outside the package. Then, the electrode of the semiconductor element 5 and the first line conductor 6a formed on the upper surface of the circuit board 6 are electrically connected by the bonding wire 7a, so that the semiconductor element 5 housed in the package is glass. The beads 3 are electrically connected to the external electric circuit via the center conductor 3a.

また、図2は本発明のパッケージにおける回路基板6の要部拡大平面図である。図2に示す例によれば、回路基板6の上側主面に形成された第2の線路導体6bは、載置部1a側の他端部が半導体素子5に電気的に接続されており、回路基板6の外周側の一端部の両側が、第2の線路導体6bの線路方向に対して対称に斜め方向に延出して同一面接地導体6cに接続される2本の高抵抗体8が接続されている。そして、第2の線路導体6bの載置部1a側の他端と高抵抗体8との距離が高周波信号の波長λの1/2未満である。   FIG. 2 is an enlarged plan view of a main part of the circuit board 6 in the package of the present invention. According to the example shown in FIG. 2, the second line conductor 6 b formed on the upper main surface of the circuit board 6 is electrically connected to the semiconductor element 5 at the other end on the mounting portion 1 a side. Two high resistance bodies 8 are connected to the same plane ground conductor 6c so that both sides of one end on the outer peripheral side of the circuit board 6 extend obliquely symmetrically with respect to the line direction of the second line conductor 6b. It is connected. The distance between the other end of the second line conductor 6b on the mounting portion 1a side and the high resistor 8 is less than ½ of the wavelength λ of the high frequency signal.

同一面接地導体6cは、第2の線路導体6bの両側および回路基板6外周側の一端を一定間隔をもって取り囲んでおり、好ましくは、回路基板6上面の外周部まで設けられるのがよい。このように同一面接地導体6cを形成することにより、第2の線路導体6bの接地電位を強化できるとともに、高抵抗体8をこの同一面接地導体6cに配線で引き回すことなく直接、短い距離で接続することができ、高抵抗体8から同一面接地導体6cまでの寄生インダクタンス成分や寄生キャパシタンス成分を低減することができ、その結果、第2の線路導体6bの他端側に接続された高抵抗体8から見た第2の線路導体6bのインピーダンス値の変動を小さくすることができるため、第2の線路導体6bについて高周波帯域まで良好な終端特性を得ることが可能となる。   The same-surface ground conductor 6c surrounds both sides of the second line conductor 6b and one end on the outer peripheral side of the circuit board 6 with a constant interval, and is preferably provided up to the outer peripheral part on the upper surface of the circuit board 6. By forming the same-surface ground conductor 6c in this way, the ground potential of the second line conductor 6b can be strengthened, and the high resistor 8 can be directly connected at a short distance without being routed by the same-surface ground conductor 6c. The parasitic inductance component and the parasitic capacitance component from the high resistance body 8 to the same plane grounding conductor 6c can be reduced, and as a result, the high level connected to the other end side of the second line conductor 6b. Since the fluctuation of the impedance value of the second line conductor 6b viewed from the resistor 8 can be reduced, it is possible to obtain good termination characteristics up to the high frequency band for the second line conductor 6b.

また、第2の線路導体6bの載置部1a側の他端と高抵抗体8との距離が高周波信号の波長の1/2未満であることから、第2の線路導体6bの一端部と高抵抗体8との接続部までの長さで発生する共振現象を使用周波数よりも高周波側へとシフトさせることができるため、使用周波数において共振現象が発生することがなく、使用周波数の高周波信号に対して良好な伝送特性を得ることが可能となる。   In addition, since the distance between the other end of the second line conductor 6b on the mounting portion 1a side and the high resistance 8 is less than ½ of the wavelength of the high-frequency signal, one end of the second line conductor 6b Since the resonance phenomenon that occurs in the length up to the connection portion with the high-resistance body 8 can be shifted to a higher frequency side than the use frequency, the resonance phenomenon does not occur at the use frequency, and the high-frequency signal at the use frequency does not occur. In contrast, it is possible to obtain good transmission characteristics.

さらに、第2の線路導体6bの線路方向に対して対称に斜め方向に延出して同一面接地導体6cに接続される2本の高抵抗体8が形成されていることから、高抵抗体8は第2の線路導体6bに対して並列に接続されることとなるため、高抵抗体8の1つ当たりに要求される抵抗値を所望の抵抗値よりも大きく設定することができる。このため高抵抗体8の1つ当たりに要求される抵抗値のバラツキの許容範囲も緩和でき、製造歩留まりを向上することができる。また、高抵抗体8の寄生インダクタンス成分も第2の線路導体6bに対して並列に接続されることになるため、寄生インダクタンス成分も低減することが可能となり第2の線路導体6bについてさらに高周波帯域まで使用可能な終端特性を得ることが可能となる。また、高抵抗体8が第2の線路導体6bの線路方向に対して斜め方向に延出しているので、第2の線路導体6bから高抵抗体8に滑らかに高周波信号を伝送させることが可能となり、第2の線路導体6bと高抵抗体8との境界で高周波信号が反射するのを有効に抑制することができる。   Furthermore, since the two high resistance bodies 8 extending in the oblique direction symmetrical to the line direction of the second line conductor 6b and connected to the same plane ground conductor 6c are formed, the high resistance body 8 is formed. Are connected in parallel to the second line conductor 6b, so that the resistance value required per one of the high resistance bodies 8 can be set larger than the desired resistance value. For this reason, the tolerance range of the resistance value required per one high-resistance element 8 can be relaxed, and the manufacturing yield can be improved. Further, since the parasitic inductance component of the high-resistance element 8 is also connected in parallel to the second line conductor 6b, the parasitic inductance component can be reduced, and the second line conductor 6b can be further reduced in the high frequency band. It is possible to obtain termination characteristics that can be used up to. Moreover, since the high resistance body 8 extends in an oblique direction with respect to the line direction of the second line conductor 6b, it is possible to smoothly transmit a high-frequency signal from the second line conductor 6b to the high resistance body 8. Thus, reflection of a high frequency signal at the boundary between the second line conductor 6b and the high resistance body 8 can be effectively suppressed.

このような高抵抗体8は、TaN,Ni−Cr合金等の材料から成り、回路基板6に印刷塗布された後に焼成されて形成されるか、薄膜形成法により形成される。また、高抵抗体8による終端抵抗値は、伝送される高周波信号の周波数や第2の線路導体6bの特性インピーダンスに応じて、高抵抗体8の厚みや幅,形状を適宜設定することによって、所望の値に設定される。例えば、抵抗値を微小調整するために、高抵抗体8の一部をレーザ加工によって除去し、精度よく抵抗値を調整することもできる。 Such a high resistance body 8 is made of a material such as Ta 2 N, Ni—Cr alloy, and is formed by being printed and applied to the circuit board 6 and then baked or formed by a thin film forming method. Moreover, the termination resistance value by the high resistance body 8 is set by appropriately setting the thickness, width, and shape of the high resistance body 8 according to the frequency of the transmitted high frequency signal and the characteristic impedance of the second line conductor 6b. Set to desired value. For example, in order to finely adjust the resistance value, a part of the high resistance body 8 can be removed by laser processing, and the resistance value can be adjusted with high accuracy.

高抵抗体8は、第2の線路導体6bの回路基板6外周側の一端部の両側から一端(先端)を覆うように接続されているのがよい。好ましくは、図2に示すように、第2の線路導体6bの回路基板6外周側の一端部が先端に向かうに伴って漸次細くなっているのがよい。これにより、第2の線路導体6bから高抵抗体8に高周波信号が滑らかに伝送することができ、高周波信号の反射をより有効に抑制することができる。   The high resistance body 8 is preferably connected so as to cover one end (tip) from both sides of one end portion of the second line conductor 6b on the outer peripheral side of the circuit board 6. Preferably, as shown in FIG. 2, the one end of the second line conductor 6b on the outer peripheral side of the circuit board 6 is gradually tapered toward the tip. Thereby, a high frequency signal can be smoothly transmitted from the 2nd line conductor 6b to the high resistance body 8, and reflection of a high frequency signal can be suppressed more effectively.

また、高抵抗体8は屈曲部を有していない曲線や直線であるのがよい。より好ましくは、直線であるのがよい。これにより、屈曲によって高周波信号の反射が生じるのを有効に防止できる。また、高抵抗体8の幅は、高周波信号を滑らかに伝送して反射損失を防止するという観点からは、第2の線路導体6bから同一面接地導体6cにかけて一定の幅であるのがよく、例えば図2に示すように、高抵抗体8は正方形状や長方形状の形状に形成されるのがよい。   Moreover, the high resistance body 8 is good to be a curve and a straight line which do not have a bending part. More preferably, it is a straight line. Thereby, it is possible to effectively prevent the reflection of the high frequency signal due to the bending. In addition, the width of the high resistance body 8 is preferably a constant width from the second line conductor 6b to the same plane ground conductor 6c from the viewpoint of smoothly transmitting a high-frequency signal and preventing reflection loss. For example, as shown in FIG. 2, the high resistor 8 is preferably formed in a square or rectangular shape.

また、高抵抗体8の線路方向と第2の線路導体6bの線路方向とのなす角度は、20〜70度であるのがよい。より好ましくは40〜50度であるのがよい。20度未満であれば、2本の高抵抗体8間で接触し易くなり、安定な抵抗値のものを得るのが困難になる。また、70度を超えると、高周波信号が第2の線路導体6bから高抵抗体8に滑らかに伝送し難くなり、高周波信号の反射が起こりやすくなる。   In addition, the angle formed by the line direction of the high-resistance element 8 and the line direction of the second line conductor 6b is preferably 20 to 70 degrees. More preferably, it is 40 to 50 degrees. If it is less than 20 degree | times, it will become easy to contact between the two high resistance bodies 8, and it will become difficult to obtain the thing of stable resistance value. On the other hand, when the angle exceeds 70 degrees, it is difficult to smoothly transmit a high frequency signal from the second line conductor 6b to the high resistance body 8, and reflection of the high frequency signal is likely to occur.

そして、本発明の半導体素子収納用パッケージの回路基板6上に半導体素子5を載置固定するとともにボンディングワイヤ7a,7bを介して第1の線路導体6aおよび第2の線路導体6bに電気的に接続し、枠体2の上面にFe−Ni−Co合金等の金属から成る蓋体4を半田付けやシームウエルド法等により接合することによって、本発明の半導体装置となる。この本発明の半導体装置によれば、容器内部に半導体素子5を気密に収納して半導体素子5を長期にわたり正常かつ安定に作動させることができ、基体1が外部電気回路基板に固定実装され、グラスビーズ3と外部電気回路に接続された同軸ケーブルとを接続することにより、内部に収納した半導体素子5が外部電気回路に電気的に接続され、半導体素子5が高周波信号で作動することとなる。   Then, the semiconductor element 5 is placed and fixed on the circuit board 6 of the semiconductor element storage package of the present invention, and electrically connected to the first line conductor 6a and the second line conductor 6b via the bonding wires 7a and 7b. The semiconductor device of the present invention is obtained by connecting and bonding the lid 4 made of a metal such as Fe—Ni—Co alloy to the upper surface of the frame 2 by soldering, seam welding, or the like. According to the semiconductor device of the present invention, the semiconductor element 5 can be hermetically accommodated inside the container so that the semiconductor element 5 can be operated normally and stably over a long period of time. The base 1 is fixedly mounted on the external electric circuit board, By connecting the glass beads 3 and the coaxial cable connected to the external electric circuit, the semiconductor element 5 housed therein is electrically connected to the external electric circuit, and the semiconductor element 5 operates with a high-frequency signal. .

本発明の半導体素子収納用パッケージおよび半導体装置における高周波信号の好ましい周波数帯は、マイクロ波やミリ波帯領域であり、高抵抗体8における寄生インダクタンス値や寄生キャパシタンス値を適切に調整,制御することによって高周波帯域における高抵抗体8の抵抗値を所望の値に調節できることから、これらの周波数帯における高周波信号の伝送特性を良好なものとすることができる。   The preferred frequency band of the high frequency signal in the semiconductor element housing package and the semiconductor device of the present invention is a microwave or millimeter wave band region, and the parasitic inductance value and the parasitic capacitance value in the high resistor 8 are appropriately adjusted and controlled. Thus, the resistance value of the high resistor 8 in the high frequency band can be adjusted to a desired value, so that the transmission characteristic of the high frequency signal in these frequency bands can be improved.

また、回路基板6は、例えばIC,LSI,半導体レーザ(LD),フォトダイオード(PD)等の半導体素子5が2つ以上の回路ブロックに分割されていてもよく、その場合は、各半導体素子5が接続されたそれぞれの回路ブロックにおいて、本発明の構成とすればよい。   The circuit board 6 may be divided into two or more circuit blocks, for example, a semiconductor element 5 such as an IC, an LSI, a semiconductor laser (LD), or a photodiode (PD). Each circuit block to which 5 is connected may have the configuration of the present invention.

なお、本発明は以上の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲内で種々の変更を行なっても何ら差し支えない。   It should be noted that the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the present invention.

(a)は本発明の半導体素子収納用パッケージの実施の形態の一例を示す断面図、(b)は(a)の半導体素子収納用パッケージの平面図である。(A) is sectional drawing which shows an example of embodiment of the package for semiconductor element accommodation of this invention, (b) is a top view of the package for semiconductor element accommodation of (a). 図1の半導体素子収納用パッケージにおける回路基板の要部拡大平面図である。FIG. 2 is an enlarged plan view of a main part of a circuit board in the semiconductor element storage package of FIG. 1. (a)は従来の半導体素子収納用パッケージの断面図、(b)は(a)の半導体素子収納用パッケージの平面図である。(A) is sectional drawing of the conventional package for semiconductor element accommodation, (b) is a top view of the package for semiconductor element accommodation of (a).

符号の説明Explanation of symbols

1:基体
1a:載置部
2:枠体
2a:貫通孔
3:グラスビーズ
3a:中心導体
4:蓋体
5:半導体素子
6:回路基板
6a:第1の線路導体
6b:第2の線路導体
6c:同一面接地導体
6d:接地導体層
6e:端面の接地導体
7a,7b:ボンディングワイヤ
8:高抵抗体
DESCRIPTION OF SYMBOLS 1: Base | substrate 1a: Mounting part 2: Frame body 2a: Through-hole 3: Glass bead 3a: Center conductor 4: Cover body 5: Semiconductor element 6: Circuit board 6a: 1st line conductor 6b: 2nd line conductor 6c: Ground conductor on the same surface 6d: Ground conductor layer 6e: Ground conductor on the end face 7a, 7b: Bonding wire 8: High resistance body

Claims (2)

上側主面に高周波信号で駆動される半導体素子を載置するための載置部を有する回路基板と、上面の中央部に前記回路基板が搭載された基体と、該基体の上面の外周部に前記回路基板を囲繞するように接合された枠体とを具備しており、前記回路基板の前記上側主面に、前記載置部の周縁部から外周に向かって形成された線路導体と、該線路導体の両側および前記外周側の一端を一定間隔をもって取り囲む同一面接地導体と、前記線路導体の前記外周側の一端部の両側に接続されるとともに、前記線路導体の線路方向に対して対称に斜め方向に延出して前記同一面接地導体に接続される2本の高抵抗体とが形成されており、前記線路導体の前記載置部側の他端と前記高抵抗体との距離が前記高周波信号の波長の1/2未満であることを特徴とする半導体素子収納用パッケージ。 A circuit board having a mounting portion for mounting a semiconductor element driven by a high-frequency signal on the upper main surface, a base on which the circuit board is mounted at the center of the upper surface, and an outer peripheral portion of the upper surface of the base A frame body joined so as to surround the circuit board, and on the upper main surface of the circuit board, a line conductor formed from the periphery of the mounting portion toward the outer periphery, It is connected to both sides of one end of the outer peripheral side of the line conductor and the same surface ground conductor that surrounds both ends of the line conductor and one end of the outer peripheral side with a constant interval, and is symmetrical with respect to the line direction of the line conductor Two high resistance bodies extending in an oblique direction and connected to the same surface ground conductor are formed, and the distance between the other end on the placement portion side of the line conductor and the high resistance body is It is less than half of the wavelength of the high frequency signal. Semiconductor device package for housing that. 請求項1記載の半導体素子収納用パッケージと、前記載置部に載置されるとともに前記線路導体に電気的に接続された半導体素子と、前記枠体の上面に取着された蓋体とを具備していることを特徴とする半導体装置。 A package for housing a semiconductor element according to claim 1, a semiconductor element mounted on the mounting portion and electrically connected to the line conductor, and a lid attached to the upper surface of the frame body A semiconductor device comprising the semiconductor device.
JP2003303724A 2003-08-27 2003-08-27 Semiconductor element storage package and semiconductor device Expired - Fee Related JP4164011B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003303724A JP4164011B2 (en) 2003-08-27 2003-08-27 Semiconductor element storage package and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003303724A JP4164011B2 (en) 2003-08-27 2003-08-27 Semiconductor element storage package and semiconductor device

Publications (2)

Publication Number Publication Date
JP2005072507A JP2005072507A (en) 2005-03-17
JP4164011B2 true JP4164011B2 (en) 2008-10-08

Family

ID=34407609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003303724A Expired - Fee Related JP4164011B2 (en) 2003-08-27 2003-08-27 Semiconductor element storage package and semiconductor device

Country Status (1)

Country Link
JP (1) JP4164011B2 (en)

Also Published As

Publication number Publication date
JP2005072507A (en) 2005-03-17

Similar Documents

Publication Publication Date Title
JP5309039B2 (en) High-frequency wiring board, electronic component storage package, electronic device and communication device
JP5241609B2 (en) Structure, connection terminal, package, and electronic device
JP4903738B2 (en) Electronic component storage package and electronic device
JP5178476B2 (en) Wiring board, semiconductor element storage package, and semiconductor device
JP4377768B2 (en) Semiconductor element storage package and semiconductor device
JP4789636B2 (en) Semiconductor element storage package and semiconductor device
JP4969490B2 (en) Substrate holding member and package, and electronic device
JP3981645B2 (en) I / O terminal and semiconductor element storage package and semiconductor device
JP7145311B2 (en) Wiring substrates, packages for electronic components, and electronic devices
JP4164011B2 (en) Semiconductor element storage package and semiconductor device
JP3702241B2 (en) Semiconductor element storage package and semiconductor device
JP3720726B2 (en) Semiconductor element storage package and semiconductor device
JP4210207B2 (en) High frequency wiring board
JP3690656B2 (en) Semiconductor element storage package and semiconductor device
JP3805272B2 (en) Semiconductor element storage package and semiconductor device
JP3934972B2 (en) Circuit board, semiconductor element storage package, and semiconductor device
JP4373831B2 (en) Electronic component storage package and electronic device
JP3780509B2 (en) Semiconductor element storage package and semiconductor device
JP3652278B2 (en) Semiconductor element storage package and semiconductor device
JP3934971B2 (en) Circuit board, semiconductor element storage package, and semiconductor device
JP3652279B2 (en) Semiconductor element storage package and semiconductor device
JP2019175939A (en) Package for semiconductor element and semiconductor device
JP4206321B2 (en) Semiconductor element storage package and semiconductor device
JP2006128323A (en) Semiconductor device and storing package thereof
JP2007149955A (en) Terminal resistance substrate for high frequency and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060807

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061226

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080701

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080725

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110801

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120801

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130801

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees