JP2002533738A - Method for testing a semiconductor product die and an assembly including a test die for the test - Google Patents

Abstract

(57) [Summary] A test assembly (2000) for testing a product circuit (202, 302, 304) of a product die (2011, 300). In one embodiment, a test assembly includes a test die (2010, 400) and an interconnect board (2008) that electrically couples the test die to a host controller (2002). The test die can be designed according to a design methodology (100) for the test die and the product die, including the step of simultaneously designing the test circuit (202A, 402, 404) and the product circuit into an integrated design (102). The test circuit can be designed to provide a high degree of defect coverage for the corresponding product circuit, regardless of the amount of silicon area required by the test circuit. The design methodology then partitions the integrated design into test and product dies (104). The test die contains test circuits, and the product die contains product circuits. A product die can include several test circuits. The product and test dies are then fabricated on separate semiconductor wafers. By splitting the product and test circuits into separate dies, embedded test circuits on the product die can be eliminated or minimized. This tends to reduce the size of the product die and reduce the cost of manufacturing the product die while maintaining a high test coverage of the product circuits within the product die. The test dies can then be used to test multiple product dies on one or more wafers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to integrated circuit (IC) semiconductor devices, and more particularly to testing such devices.

[0002]

[Prior art]

As the complexity and density of integrated circuit designs increase, design methodologies are designed to improve testability and quality of the final product (Design-For-Test-DFT).
) It is required to fabricate circuits using technology. Test methodologies are also required to produce high quality, low cost test solutions.

[0003] One conventional design methodology is to first design an integrated circuit using software design tools, simulate the overall function of the design or individual circuits in the design, and then Some processes include a process of generating test vectors for testing various functions. The test vector is typically
Generated by an automated software tool (eg, an automatic test pattern generator or ATPG) that provides a fixed fault coverage or defect simulation for circuits in a product. Then, such a test vector is
It is provided to an automatic testing equipment (ATE) or tester, typically in the form of a computer readable file. ATE is a manufacturing environment for testing dies on wafers, and packaging testing
Used in (packaged test). Integrated circuit designs are becoming more complex and faster, which places more demands on test equipment. This tends to increase the cost of the ATE and therefore the manufacturing cost. Further, as integrated circuit design becomes more complex, the time required to test the circuit will increase. This also increases manufacturing costs.

During wafer-level testing of a die, test signals are provided via input or input / output (I / O) bonding pads on the die and the test results are output or I / O.
Monitored on the / O bonding pad. A good die that has passed wafer-level testing is singulated, typically by electrically connecting its bonding pads to the package via bonding wires, solder balls, or other contact structures. Be packaged. In accordance with the bonding wires or solder balls, the bonding pads are generally very large compared to the circuit elements of the integrated circuit. Typical bond pad size is 100μm
× 100μm (4 mils × 4 mils). The bonding pads are also typically arranged in a regular pattern, for example, in a grid pattern along the periphery of the die, or in rows and columns passing approximately through the center of the die (lead-on-center: lead-on-center).

In order to improve the test coverage of individual circuits, test circuits are integrated into the design itself
DFT tools were developed. For example, a built-in self test (BIST) circuit can be inserted into a design to test individual circuit blocks. BIST
It is particularly useful for testing circuit blocks that are not easily accessible by the bonding pads of the device under test (DUT). Automated DFT tools (such as those provided by Mentor Graphics, Oregon) for generating BIST circuits (such as memory BIST for testing memory blocks and logical BIST for testing logic blocks) are well known It is. The result of the test performed by the BIST circuit is
Provided directly to external I / O or indirectly to external I / O via a boundary scan circuit that can be included in the design. Additional internally incorporated test circuits, such as SCAN chain circuits, can be added to the design to increase the internal testability of internal and sequential designs. .

If one die already provides all of its peripheral, grid, or lead-on-center bonding pad locations for the function of one device, then the on-chip test circuit may be used. Adding additional bonding pads in a given bonding pad arrangement to support would significantly increase the die size. The cost of the die tends to increase correspondingly. In general, larger die sizes are more prone to defects, resulting in higher manufacturing costs. Furthermore, on-chip test circuits can significantly increase test time. This is because loading the test input data and then outputting the test results from the few available bonding pads may require many clock cycles. On-chip test circuits also do not allow for direct external access to internal circuit nodes. Test input data and test results are SC
Monitoring is only possible after passing through the AN circuit or BIST circuit. This may require additional circuitry that can mask the failure of the circuit under test, or may cause a new failure by the SCAN or BIST circuit.

Furthermore, many designs have limited I / O. This is because a given packaging scheme can only accommodate a limited number of leads (eg, bonding wires). In addition, those same lead locations must be used to test the I / O function of the die. Accessing more points in the circuit is advantageous (especially for testing). It would also be advantageous to be able to locate the access point with a high degree of positional freedom. It is also advantageous that the size of the access point is small, that there are many access points, and that any or selective positioning of the access point is performed.

In the case of embedded test circuits, integrated circuit design methodology first designs the integrated circuit using a software design tool, and determines the overall function of the integrated circuit or individual circuits in the design. Simulating, generating an embedded test circuit for testing individual circuits or circuit blocks in the design, and generating test vectors for performing a functional test of the device by ATE. Becomes

[0009] The amount of embedded test circuitry added to a particular design typically benefits from increased defect coverage and possible shortened test times, and increases the cost of manufacturing the end product. It is necessary to balance the disadvantages of increasing die size and the potential for manufacturing defects. In an extreme example, a design can include complex embedded test circuits that test every circuit node of every internal circuit, but such designs are prohibitively expensive. This is because the die size is basically a function of the size of the test circuit. In another example, the design may include no embedded test circuitry and test the functionality of the design at the wafer level or in a packaged form, relying solely on test vectors provided by the ATE. It is possible. However, this method reduces the defect detection range,
It tends to reduce product quality and increase manufacturing costs through the use of expensive ATEs and increased test times. One method for minimizing the cost of using expensive ATE is disclosed in US Pat. No. 5,497,079. The U.S. Patent condenses the general purpose functions of the ATE into a general purpose function test chip. The test chip can test another semiconductor chip under the control of the host computer. The test chip can be placed on a probe card, or can be brought into electrical contact with a chip to be tested via a motherboard. Another method is 1997 1
No. 08 / 784,862, filed on Mar. 15, 2009. In the application, a wafer level test of a semiconductor chip is performed by a test chip having a general-purpose test circuit.

[0010] Between the above two extremes, a typical integrated circuit design will reach a balance between the amount of embedded test circuitry and the tests to be performed by the ATE.
Typically, embedded test circuits are limited to about 5-15% of the total die area of the design,
Test vectors are generated for the ATE to test the overall functionality of the design. However, the defect detection range resulting from this equilibrium is less than the optimal defect detection range, and still requires the use of expensive ATE.

[0011]

[Problems to be solved by the invention]

It is desirable to have a design and test methodology that breaks the linear relationship between defect coverage or testability and the cost of testing or manufacturing the design.

[0012]

[Means for Solving the Problems]

One embodiment of the invention is directed to a test assembly for testing a product circuit of a product die. In one embodiment, the test assembly includes a test die and an interconnect board for electrically coupling the test die to a host controller that communicates with the test die. The test die can be designed according to a design methodology that includes designing test circuits and product circuits simultaneously in a unified design. The test circuit can be designed to provide a high degree of defect coverage for the corresponding product circuit, regardless of the amount of silicon area required by the test circuit. The design methodology then divides the integrated design into a test die and a product die. The test die includes test circuits, and the product die includes product circuits. The product die and test die are then fabricated on separate semiconductor wafers. By splitting the product and test circuits into separate dies, embedded test circuits can be eliminated or minimized on the product die. This tends to reduce the size of the product die and reduce the cost of manufacturing the product die, while maintaining a high test coverage of the product circuits within the product die. The test die is then used to test multiple product dies on one or more wafers.

[0013] Other objects, features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Although the features and advantages of the present invention are illustrated by its embodiments, this is by no means intended to limit the scope of the invention to that particular embodiment.

In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art can practice the invention without these specific details. In some embodiments, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.

FIG. 1 is a design methodology for designing a product die and a corresponding test die.
100 is one embodiment of the present invention. The test die includes a test circuit that provides test signals to or monitors signals from one or more circuits on the product die.
2 through 4 show product dies and test dies generated by the design methodology 100. FIG.

Throughout this specification, the terms “product die” and “product device” refer to an example of an integrated circuit formed on a semiconductor wafer or on an insulating substrate or other suitable substrate. Such terms also refer to a device under test (DUT). The term “product circuit” refers to the circuit of a product die, and includes integrated semiconductor circuits, integrated microelectromechanical structures or systems (MEMS).
al structure or systems) or other active or passive elements including appropriate circuit elements. Further, the terms "test die" and "test device" refer to an integrated circuit formed on a semiconductor wafer or on an insulating substrate or other suitable substrate. The test die includes circuitry for providing test signals to the product die and / or monitoring signals from the product die. The test die can also be comprised of active or passive devices, including integrated semiconductor circuits, integrated MEMS, or other suitable circuit elements for testing or monitoring product dies. Later, a test die and a product die are provided in a land grid array (land grid array) package (for example, a ball grid array (BGA)).
d Array) packages, Pin Grid Array (PGA) packages, control collapse chip connection packages, flip chip packages, other surface mount packages, dual in-line packages (DIP), etc. It can be packaged into any known package.

In step 102, a circuit integrated design 200 for a product die and a test die 200
Designed with. The design uses conventional software tools to create product circuits 202, 20
4, 206 and test circuits 202A, 204A, 206A (eg, in VHDL or Verilog HDL format) can be implemented in a conventional computer aided design (CAD) system. Test circuits 202A, 204A, 206A, sometimes collectively referred to as "test benches", are designed to be as robust as desired. That is, the test circuits 202A, 204A, and 206A correspond to the corresponding product circuits 202, 204, and 20.
Each of the six can be designed to include the desired number of test functions to test. One test circuit is 100% for the corresponding product circuit
Can be designed to provide a desired defect detection range different from the above. Previous Design-F
In contrast to the or-Test (DFT) design methodology, the test circuits 202A, 204A, 206A can be designed as described above regardless of the amount of silicon die area for performing the test circuits. . In one embodiment, the test circuit and the product circuit can each be designed such that the resulting product die and test die have approximately the same size. In another embodiment, the product die and test die can be different sizes.

At step 104, the product circuit and the test circuit are connected to separate product dies and one or two
Each is divided into one or more test dies. Splitting the test circuit into separate test dies allows for minimizing or eliminating test circuits on the product die. This reduces the die size of the product die, thereby reducing the likelihood of manufacturing defects and increasing the testability of the product die while generally reducing manufacturing costs. External test circuits that provide test stimuli can increase the number of tests without affecting the size of the product die 300. If the BIST circuit is not included in the test input or output signal path, the possibility of determining the position of the defect more accurately is increased. This is because there are no on-chip test circuits that mask defects or create additional defects. Furthermore, the speed parameters or timing of signals input to and output from circuit blocks or circuit nodes can be adjusted without delays caused by intervening on-chip test circuits.
Measurement and monitoring can be performed more accurately.

The product die design is taped out at step 106 and the test die design is separately taped out at step 108. The resulting product die 300 is then fabricated on a semiconductor wafer (not shown) along with many other identical product dies.
The product circuits 302, 304, 306 included in the product die 300 are product circuits 202, 204, 20 respectively.
It can be any digital, analog or other circuit corresponding to 6.

The resulting test die 400 is fabricated to include test circuits 402, 404, 406. The test circuits 402, 404, and 406 correspond to the test circuits 202A, 204A, and 206A, respectively, and test and monitor signals from the product circuits 302, 304, and 306, respectively.
It can be any digital, analog, or other test or monitoring circuit. For example, each test circuit is a functional circuit for testing the logical operation of a product circuit (eg, test pattern generator, sequencer, digital signal processor (DSP), formatter, analog-to-digital converter, digital-to-analog converter, It can include circuits for testing AC parameters (eg, timing of internal signals, circuit speed, etc.) and DC parameters (eg, voltage and current levels, power loss, etc.).

While each test circuit is designed to support a particular test of the corresponding production circuit, one embodiment of an exemplary test circuit 500 is shown in FIG. The test circuit 500 includes a control logic circuit 502 that controls the overall operation of the test circuit 500. The control logic circuit 502 can be, for example, a sequencer. Associated with the control logic 502 are a pattern generator 504, analysis logic 506, one or more parameter measurement units (PMUs) 510, one or more digital power supplies (DPS) 512, and The clock logic circuit 514 operates. Pattern generator 504 generates one or more test patterns that are sent to product circuits within product die 300 via input / output (I / O) circuit 508. Pattern generator 504 can include a memory for storing patterns. The analysis logic 506 analyzes signals received from the product circuit of the product die 300 via the I / O circuit 508. The analysis logic circuit 506 outputs the expected result to the I / O circuit.
Comparison logic may be included to compare the signal received from 508. PMU51
0 measures the voltage and current level of the signal received by the I / O circuit 508. For example, PMU 510 can measure leakage current, source current and voltage, sink current and voltage, power loss, and the like. The DPS512 provides one or more power supply voltages to the product circuit under test. In alternative embodiments, power can be supplied from sources other than the test die. The clock logic circuit 514 can provide a clock signal to a product circuit to be tested. In the case of an asynchronous circuit, no clock signal is required. Also in this case, the test circuit 500
1 shows an embodiment of a test circuit such as test circuits 402, 404, and 406. Other embodiments can be used. All of the circuit blocks shown in FIG. 5 can be included in each of the test circuits 402, 404, and 406, or any one or more of the circuit blocks in FIG. 5 can be shared by a plurality of test circuits 402, 404, and 406. Is possible.

Here, FIG. 1 to FIG. 4 are referred to again. The splitting step 104, which can be implemented in a CAD DFT software tool, first determines the logical interconnection points between each product circuit and its corresponding test circuit, then the product die and test die. Create a logical and physical description of each of the. The interconnection points result in special contact points or contact pads (test pads) 310,410. The pad 310 provides a test signal to the product circuit 302, 304, 306, or an output signal from the circuit. As described in detail below, the pad 310
02, 404, and 406 can be brought into electrical contact with the pad 410 of the test die 400 by one contact structure (for example, a spring contact element or a probe of a probe card).

As shown in FIGS. 3 and 4, pads 310 and 410 can be physically located around a particular circuit under test, or provide more direct access to particular circuit nodes. It can be arranged on a circuit. Generally, pad 310,
The 410 can be disposed at any location on the product die and the test die, including the area surrounded by the bonding pads 312 of the product die 300 as shown in FIG. The pads 310, 410 can also be arranged in the same predetermined arrangement as the bonding pads, or outside the area surrounded by the bonding pads. The bonding pad 312 is a conventional input, output, or I / O pad that receives the tip of the probe or receives a bonding wire or solder ball during wafer sorting (wafer sorting). Bonding pads 312 are conventionally used to operate product die 300 as a whole. Similarly, test die 400 may be used to test the overall functionality of test die 400 (eg, during wafer sort) or to bond the test die to pins on a semiconductor package. Includes a possible bonding pad 412.

When the pads 310 are located in the area surrounded by the bonding pads 312, the size of the product die 300 does not increase if the pads 310 have a given size and number. Furthermore, by moving the test circuit to a separate test die,
The bonding pads previously used to communicate with the internal test circuitry can be omitted. This further reduces the size of the product die 300. In another embodiment, the addition of pads 310 may increase the size of product die 300. In one embodiment, the size of pad 310 can be smaller than bonding pad 312.

In an alternative embodiment, the splitting step 104 may determine that no additional interconnection points are needed to test the product die 300.
For example, in the dividing step 104, the bonding pads 312 are connected to the product circuits 302, 304, and 306.
Can be used to test the entire function of the bonding pad
It can be determined that 312 can be reassigned to be used to interface with test circuits 402, 404, and / or 406 when using test die 400. In this embodiment, the number of special contact pads can be zero or less than required in the above embodiment.

After the division in the division step 104, some BIST circuits such as the BIST circuit 308 are
It is possible to hold at 300. For example, to test high speed circuits that would be improperly imposed by the addition of pad 310, or to provide pad 310 to interface with test die 400 if there is not enough space on product die 300. , The BIST circuit can be advantageously retained on the product die 300.

In another embodiment, the design methodology 100 can use an existing or predetermined test circuit to generate a suitable production circuit. For example, in step 102, a product circuit can be designed to be tested by a predetermined test circuit at a desired level of defect detection range. Next, steps 104 to 108 perform the same processing as described above.
This embodiment is particularly appropriate, for example, if the product circuit on the product die is predictable, such as a memory circuit. Test circuits for testing such highly predictable architectures are well-known and well-tested (i.e., those that generate march patterns, galloping matrix patterns, etc.) and can be implemented on existing test circuits. It can only be used if the product circuit has to be adjusted to accommodate it. Further, the test circuit may have been previously formed on an existing test die, and the dividing step 104 determines how to lay out the product circuit to maintain the predetermined test circuit,
That is, it is possible to add an interconnection point between the test circuit and the product circuit.

FIG. 6 illustrates another embodiment of a design methodology 600 for designing one or more of the product die 300 of FIG. 3 and the test die 400 of FIG.

In step 602, product design data for the product circuits 202, 204, 206 is generated, and in step 603, test design data for the test circuits 202A, 204A, 206A is generated. The design data is generated by a CAD software design tool according to an input from a circuit designer regarding the circuit. The design data is VDHL, Verilog
It can exist in the computer in HDL format. The test design data can be automatically generated by a CAD DFT software tool with or without input from a circuit designer. As described above with respect to the design methodology 100, the test design data is such that the test circuit generated by the data is as robust as desired by the circuit designer.

At step 606, a register transfer level (RTL) description of the integrated design including both product data and design data is generated and verified by the CAD software.
At step 606, a logical composition and verification of the integrated RTL description is generated. At this point, the software description of the integrated product and test circuit is complete.

The test software tool 608 takes the integrated design output from step 606 and tapes out the product die 300, one or more separate test dies 400, and the interconnect description. Next, data to be created is generated. At step 610, the software tool 608 splits the integrated design into separate product die and test die descriptions and generates a physical layout (eg, in silicon). This step is performed taking into account physical constraints 612 and user preferences (ie preferences) 614. The constraints 612, 614 may be input to the software tool 608 prior to the execution of the design methodology 600, or the software tool 608 may prompt the user for this input at runtime.

Physical constraints 612 include, for example, the resulting product and test die size, the number of bonding pads or special contact pads on each die, the bonding pads and special contacts on each die. These include pad size, process constraints, or process technology. The physical constraints 612 can be used by the software tool 608 to determine the circuitry and amount to split between the product die and the test die. As an example, the maximum die size of product die 300 can be programmed as a parameter of software tool 608 when performing step 610. If the splitting of the product and test circuits creates too many specialized contact pads on the product die 300, and the size of the product die exceeds the desired die size, the software tool 608 may be used. Reconfiguring the test circuit so that fewer interconnect points are required for the product die so that some of the test circuits on the test die are
It is possible to replace the BIST circuit (ie, the BIST circuit 308 of FIG. 3, etc.) and / or eliminate some of the test circuits. In another embodiment, a design constraint may be that special contact pads should not be created on the product die and / or test die. Software Tool 608 is a product die dual purpose (
The first purpose is to test all functions of the product die, and the second purpose is to test individual product circuits using test circuits. Appropriate circuitry to enable or program this dual function can be included in the product die and / or test die.

In another embodiment, the software tool 608 includes a multi-test die where the required test circuits are best implemented in various process technologies (eg, BiCMOS vs. CMOS), and thus support test circuits from different process technologies. Can be determined. In yet another embodiment, the software tool 608 is implemented on a test die where some of the required test circuits have analog circuits and other required test circuits have digital circuits. It can be determined that it is best performed.

Another constraint that can be considered by software tool 608 is that one or more of the test circuits on the test die are predetermined. For example, as described above, a product circuit can be designed to be tested in a predetermined level of defect detection range by a predetermined test circuit. Certain test circuits are particularly useful, for example, when the product circuit of a product die is predictable, such as a memory circuit. In this embodiment, the software tool 608 divides the circuit so as to properly adjust the product circuit while maintaining the predetermined test circuit, or to properly add interconnection points between the test circuit and the product circuit. Is determined. In addition, the test circuits may have been previously formed on an existing test die, and the software tool 608 may be configured to (e.g., adjust the product circuit properly or interconnect points between the test circuit and the product circuit). Can be determined how to lay out the product circuit to maintain the predetermined test circuit.

The software tool 608 also performs step 608 taking into account other predetermined constraints, such as user preferences 614. User or circuit designer preferences 6
14 includes, for example, the cost of providing an interconnect between the product die and the test die, the cost of the product die, the cost of the test die, the timing priority, the test accuracy, the defect detection range, and the control of the test die and the test die, or Includes the cost of interconnection between the test die and an external host device in communication. The term "cost" is used herein in a broad sense and includes manufacturability, ease of use, and the like.

The cost of providing an interconnect between a product die and a test die includes the costs associated with forming special contact pads, forming the interconnect elements for communicating between the product die and the test die. Includes cost, ease of performing wafer sorting, and further testing with a specific number of special contact pads located on the product and test dies. If the cost of providing the interconnect is low, the circuit designer should show that the software tool 608 can split the circuit regardless of the number of interconnects required between the product die and the test die Can be. However, if the cost of providing the interconnect is high, the circuit designer can indicate that the software tool 608 should split the circuit to minimize or limit the number of interconnects. .

The financial cost of the resulting product and test dies can also be used by software tool 608 to determine how to partition the product and test circuits. For example, after splitting, if there is enough space on the product die to place special contact pads for product circuit testing without increasing product die size, add special contact pads And placing the corresponding test circuitry in the test die does not increase the financial cost of the product die. Thus, in this example, the software tool 608 can partition the production and test circuits to generate all of the required interconnection points. However, after the split, there is enough space to add all of the initially desired special contact pads to the product die (or test die) without increasing the die size of the product die and hence the financial cost of the product die. If not, the software tool 608 may reduce the number of interconnects and pads to keep the financial cost of the product and test dies below a predetermined user preference.

Timing priorities and test accuracy are also used by software tool 608 to determine how to divide product and test dies. For example, high speed product circuits can be unnecessarily imposed and delayed by the addition of special contact pads. As such, software tool 608 may incorporate some of the test circuitry into the product die as a BIST circuit to test the circuitry, thereby preventing timing and test accuracy delays. .

The defect coverage for testing product circuits can also be used by the software tool 608 to determine how to divide product and test dies. For example, if 100% or other high defect coverage is desired by the circuit designer, the test circuits generated in steps 602-606 need to be generated for both test dies and product and test dies. It can be divided into as many interconnect points or special contact pads as possible. However, if the circuit designer desires a low defect detection range, some of the test circuits generated by steps 602-606 will not be split into test dies. The circuit designer can input a product circuit that is more important to test than others, or a desired level of test range desired for each product circuit. Software Tools 60
8 can use the input to determine which test circuits to maintain and which to reject in the final test die.

The interconnection cost of the network between the test die and the external device can also be used by the software tool 608 to determine how to divide the product die and the test die. The external device can be, for example, a host controller or other device for reporting product die test results. In another embodiment, software tool 608 is capable of generating multiple test dies, each having specific test circuitry for one or more product dies. The number of interconnection points, such as bonding pads 410 or special contact pads 412 of FIG. 4, required to support communication between the devices will affect the size of the test die and, therefore, will be affected by user input. It is possible to limit (or not limit).

After the division of the product and test circuits into product and test die descriptions, logical and timing verification of the product die is performed at step 616 to provide logical and timing verification of the test die. Is executed in step 618. Logical and timing verification of the combined product die and test die system operating together is performed at step 620. In response to steps 616-620, software tool 608 determines in step 622 whether all of physical constraints 612 and user preferences 614 have been satisfied. If the constraints 612, 614 are satisfied, the product die is taped out at step 624 and the test die is taped out at step 628, allowing a description of the interconnection points between the dies to be generated. If the constraints 612,614 are not satisfied, the software tool 608 repeats the above process. That is, the software tool 608 returns to step 610,
In a second trial to satisfy the constraints 612, 614, the product circuit and test circuit are subdivided. The process continues until all constraints are satisfied. If the software tool 608 determines that all the constraints cannot be satisfied, it stops the process and notifies the designer to that effect. The designer can then change the design or change the constraints.

One embodiment of the dividing step 610 is shown in step 710 of FIG. The dividing step 71
0 determines the layout of product dies and test dies using conventional weighting techniques. For example, a weighting function is formed at step 702 in response to the complete system logic description, physical constraints 612, and user preferences 614 from step 606. The weighting function describes the relative trade-offs and constraints for a given partition. Many different numerical analysis techniques can be used to find the optimal solution for the partitioning problem described by the weighting function.
One such technique is "simulated annealing," in which case,
A design tool simulates the physical annealing process by mathematically raising the system to a high temperature. This allows a solution to be found quickly with minimal effort or cost. When applied in step 704, the simulated annealing may include the number of special contact pads, the amount of test circuits, the amount of test circuits, so that the best division of product and test circuits between the product and test dies is determined. Or by changing any physical constraints or user preferences, it can be used to find the optimal solution.

The partitioning of the design in step 704 can make circuit adjustments in test circuits, production circuits, and / or BIST circuits on production dies. To adjust the circuit,
Includes the addition, removal, or modification of test circuits and / or BIST circuits to optimally test product circuits. The circuit adjustment can also include the addition of additional test circuits to the test nodes introduced by the partition itself. This step
It can be completed automatically or based on interaction with the circuit designer.

Once the partition is generated in step 704, the solution is tested, evaluated, and / or simulated in step 706 to determine whether an optimal solution has been generated and to satisfy all of the constraints 612, 614. Is determined. If the weighting function is correctly specified, the tested solution is
A description of the product dies, test dies, and interconnects that meet all of the constraints 612, 614 and have (or do not) have BIST circuitry will be generated. If the user is not satisfied with the solution, adjust the constraints to form a new weighting function and a new circuit partition between the product die and test die, special contact pads,
And die size and the like.

FIG. 8 shows a design methodology 800 as a modification of the design methodology 600 of FIG. 6 (or the design methodology 100 of FIG. 1). In some applications, the resulting test die generated by the design methodology 600 (or 100) may communicate with a tester or host controller, such as an ATE, a general purpose computer, or other control logic or system. It becomes something. The tester may, for example, start and stop tests performed by the test dies, power the test dies, indicate a test sequence to the test circuits of the test dies, indicate a test sequence between multiple test dies, and receive from the test dies. It can create an inventory and report on test results. The tester can also be used to test the product dies as a whole, for example, during wafer sort when testing individual product circuits or nodes using test dies, and a separate probe controlled by the tester It is possible to test the product die as a whole using the card. Thus, the test can be selected to be distributed between the tester and the test die.

In the design methodology 800, test design data supplied to the RTL synthesis and verification step 604 is determined in steps 804-810. At step 808, the test is split between the tester and the test die in response to a test requirement 804 for testing the product circuit and a description 806 of the tester's capabilities. If the test is to be performed by a test die (determined in step 810), the test is provided to step 604 as part of the test design data along with the product circuit design data. However, if the test is to be executed by a tester, the test is stored in a test file 812 for the tester.

The design methodology described in the previous embodiments can be implemented with software routines that can be implemented on a general-purpose computer or workstation or custom CAD system. One embodiment of a general-purpose computer system 900 on which the software routines are stored and executed is shown in FIG. Many other computer system embodiments may be used.

Computer system 900 includes a computer 928 having a main memory 902, a static memory 904, a mass storage device 906, and a processor 912, communicating via one or more internal buses 910. Main memory 902 stores, for example, program code, system code, and / or one or more software routines that are embodiments of various design methodologies, a dynamic random access memory (DRAM) or other volatile memory. Alternatively, a non-volatile memory can be used. Static memory 904, which may be cache memory, may be used to store program code, system code, and / or one or more software routines that are embodiments of various design methodologies. Is possible. Mass storage device 906 can be any mass storage device, such as a CD-ROM, floppy disk, hard disk, laser disk, flash memory card, or magnetic storage device. The mass storage device 906 can also store program code, system code, and / or one or more software routines that are embodiments of various design methodologies. Processor 912 can be any control logic that coordinates data flow in computer system 928. For example, processor 912 can be a microprocessor or one or more other digital signal processing devices.

Computer 928 can communicate with one or more peripheral devices via bus 926. The peripherals include a display 914 for displaying a graphical representation of the product die and test die logic circuits and circuit elements generated by the design methodology, and / or software routines of the design methodology, a computer 9.
A keyboard 916 for inputting data to 28, a cursor control device 918 such as a mouse, a trackball or a stylus, a signal generating device 920 for providing other input signals to the computer 928, a hard copy device 922 such as a printer, And an audio recording and reproducing device 924. Special Contact Pads Referring to FIGS. Special contacts or special contact pads 310
00 test circuits 402, 404, 406 without having to test the entire function.
Provides test input data to the product circuits 302, 304, 306 or the product circuits 302, 304, 306
To monitor the signal from the Throughout the remainder of this chapter, reference will be made to specific contact pads 310 and bonding pads 312, but the same description applies equally to special contact pads 410 and bonding pads 412. .

The special contact pads 310 may also be used when the internal circuits 302-306 are not otherwise individually testable and / or are not accessible via the bonding pads 312. It also provides a means for testing circuits 302-306. For example, the product circuit 302 can be an embedded memory that cannot be directly accessed via the bonding pad 312. Address and input data are provided through some of the special contact pads 310 to provide test patterns to the embedded memory, and another group of special contact pads 310
Can receive data read from the memory. To extend the defect detection range, an external circuit that provides test patterns for the embedded memory can provide any number of test patterns.

In another embodiment, the product circuit 302 can be a programmable circuit, such as a non-volatile memory or a programmable logic circuit. Special contact pads
Data can be programmed into the internal circuit via 330. For example, after the integrated circuit 300 is manufactured, the programmable circuit 302 has BIOS information, a program code,
And it is possible to program or update the system software.

As shown in product die 300, special contact pads 310 also operate with BIST circuit 308 (or other on-chip test circuit) to enable internal circuit 306 to respond to test stimuli provided by BIST circuit 308. It is possible to monitor the response. This can be achieved without the need to add additional bonding pads 312 or to use existing bonding pads 312 to communicate the BIST circuit 308.

As shown in FIG. 3, special contact pads 310 are located in the area surrounded by surrounding bonding pads 312. Since the special contact pad 310 is not arranged at a predetermined position around the bonding pad 312, the size of the product die 300 does not increase due to the addition of the special contact pad 310. In other embodiments, the number and arrangement of special contact pads 310 may increase the size of product die 300.

The special contact pads 310 can also be interspersed between the bonding pads 312, or can be located outside the area surrounded by the bonding pads 312. In one embodiment where special contact pads 310 are interspersed between bonding pads 312, it is advantageous to make special contact pads 310 smaller than bonding pads 312 so as not to increase the size of product die 300. It is.

The special contact pad 310 can be of any size, including a size smaller than the bonding pad 312. If the special contact pad 310 is smaller than the bonding pad 312, more special contact pads on the product die 300 can be added without increasing the size of the die beyond the size defined by the surrounding bonding pads 312. It becomes possible to arrange. The increased number of specialized contact pads can increase the number and / or complexity of tests that can be provided to internal circuitry, thereby increasing the test coverage and robustness of the test Becomes In one embodiment, the bonding pad 312 is about 100 μm.
It can be m × 100 μm (4 mil × 4 mil), and a special contact pad can have one side of 5-10 μm. In another embodiment, the special contact pad may be less than 5 μm on a side. In yet another embodiment,
To accommodate different spatial locations on the die (eg, “between the bonding pads 312” and “the area surrounded by the bonding pads 312”), or the tips of various probes, bonding wires, or solder balls. The possibility of adapting to different dimensions or to different functions of the circuit under test (e.g. the node providing the output signal needs a larger pad than the pad providing the input signal and vice versa) Can be manufactured to have different sizes. The lower limit of the size of the special contact pad may be limited by the alignment accuracy between the probe and the pad and the size of the probe.

The special contact pad 310 can be formed in a substantially square shape, a rectangular shape, or any other geometric shape. The special contact pad 310 can also have a different height than the bonding pad 312. The special contact pads 310 can be made using conventional photolithographic processes commonly used to form bonding pads and other relatively flat conductive lands. In one embodiment, the special contact pads can be made from one or more metal layers, including aluminum, copper, gold, or other metals or conductive materials.

The special contact pads 310 are not permanently bonded out to integrated circuit packages (eg, typical plastic and ceramic chip packages), but are used to test input information (eg, address, control, or data signals). ) Or to monitor internal test nodes or signals. But,
The special contact pad is large enough to receive an electrical contact element (as described in detail below). The special contact pads 310, when not bonded to the package, typically require significantly smaller support circuits than those typically required by the bonding pads 312. Typical bonding pads include support circuits that require a significant amount of silicon die area. Examples of support circuits include electrostatic discharge (ESD) protection structures such as resistors, capacitors, and / or diodes, latch-up prevention circuits such as guard rings, circuits and signal lines external to integrated devices, or Examples include a buffer for buffering an internal signal received from an external signal line, a logic or voltage conversion circuit, and a noise reduction circuit. Special contact pads 310 can reduce the amount of support circuitry required.
For external probes that make electrical contact with special contact pads and monitor signals at those contacts, little or no ESD protection is required and little or no buffering is required. For example, as shown in FIG.
It is possible to use an I / O buffer 320 between the device and a special contact pad 310.
The I / O buffer 320 can be controlled by a control signal 322. I / O
Buffer 320 can be as low as one tenth to one hundredth of what would be needed if the bonding pads had to drive heavy loads in a PCB environment. Further, little or no latch-up support or noise reduction circuitry is required. For example, all that is required for each special contact pad for the noise reduction circuit is a weak pull-up resistor. Generally, special contact pads require only 1-50% of the support circuits typically required for bonding pads.

FIGS. 3 and 4 show that the special contact pads 310 and 410 are arranged in the area surrounded by the bonding pads 312 and 412 arranged on the periphery, but the special contact pads are other contact pads. It is also possible to arrange them in the layout of a product die or a test die. The integrated circuit 1100 (product die or test die) shown in FIG. 11 includes bonding pads 312 aligned in an LGA pattern for bonding to contact balls (eg, solder or other metal interconnects) in a C4 or flip chip configuration. ing. The special contact pads 310 are selectively distributed inside or outside the grid pattern. In this embodiment, the special contact pads 310 are smaller than the bonding pads 312 or contact balls and do not increase the size of the integrated circuit 1100 beyond the minimum size required for a given number of bonding pads 312. It has become. In an alternative embodiment, the special contact pad 310 can be the same size as the bonding pad 312.

FIG. 12 shows a special contact pad 310 located between two bonding pads 312.
FIG. 4 is a cross-sectional view of the device viewed from the side. The bonding pad 312 has a contact ball 1204 formed on its upper part, and has a minimum distance 1202 between their centers (about 250 μm (about 10 mil)).
) Are generally separated. The minimum diameter 1208 of the contact ball 1204 is typically about 25-76
μm (1-3 mils) and the minimum distance 1206 between the edges of the contact ball 1204 is:
Typically on the order of about 178-229 μm (7-9 mils). The special contact pad 310 can be a suitable size between the bonding pads 312 and is about 229 μm (9 mil)
It is possible to have a smaller width 1210. In another embodiment, the special contact pad 310 may have a width of about 25-127 μm (about 1-5 mil). In yet another embodiment, the special contact pads 310 can have a width of less than about 1 mil. The special contact pad 310 can be formed in a substantially square shape, a rectangular shape, or other geometric shapes. The special contact pad 310 can also have a different height than the bonding pad 312.

The embodiment shown in FIGS. 11 and 12 also provides a socket or printed circuit board (PCB)
), An LGA package such as a BGA package, a PGA package, a C4 package, or a flip-chip package having pins or contact balls for interfacing. Special contact pad 310 receives the test signal,
Or, there may be additional pins or pads that can provide test output signals or other signals to the probe, socket, or PCB.

FIG. 12 also shows a special contact pad 310 located between two peripherally aligned bonding pads 312 (as shown in FIG. 3). Bonding pad
Contact ball 1204 need not be formed on 312.

FIG. 13 shows an integrated circuit 1300 (product die or test die) including bonding pads 312 arranged in a row (or row) in a lead-on center pattern. Special contact pads 310 are selectively distributed inside and outside of the lead-on center pattern to provide test signals to or from internal circuits 1302, 1304 of the integrated circuit 1300. Can be used to monitor the signals of

FIGS. 3 and 4 show that product circuit blocks or internal circuit nodes can be tested or monitored with special contact pads. FIG. 14 shows that successive product circuits 1402, 1404, 1406 can also be tested with special contact pads, with or without the use of bonding pads. In this embodiment, test input data is provided from test circuitry on the test die to special contact pads 1412 and embedded memory 1402. In an alternative embodiment,
Input data can be provided from bonding pads. Test data may include addresses, control signals (eg, read, write, etc.), and / or test patterns. Assuming that the test data is the address of one location in memory 1402, the data stored at the accessed address is provided through I / O interface 1404 and by special contact pads 1413. It is possible to monitor. The access time (ie, address to data out) of the memory 1402 is controlled by the special touch pad 1
It is possible to measure more accurately by using 412 and 1413. This is because no additional time is introduced due to circuit blocks such as the I / O interface 1404 and the I / O driver 1406. Conventional approaches using BIST circuitry generally involve additional on-chip circuitry to provide address signals (eg, to memory 1402), and then external circuitry can be implemented with one or more bonding pads 1416 Can be monitored. However, this conventional approach cannot directly monitor the output of memory 1402 (as with the use of special touch pad 1413), and therefore can directly measure the actual access time of memory 1402. You can't.

In response to data read from memory 1402, I / O interface 1404 can format the data prior to providing it to I / O driver 1406. The I / O interface 1404 can receive control signals on a special contact pad 1414, i.e., internal circuit nodes within the I / O interface 1404 can be monitored by the special contact pad 1414. is there. I via I / O interface 1404
Data output to the / O driver 1406 can be monitored via special contact pads 1415. The I / O driver 1406 can then drive data to the bonding pad 1416.

The special contact pads 1413, 1415 and the bonding pad 1416 are connected to the memory 1402, the I / O interface, so that illegal data received at the bonding pad 1416 can be isolated to the circuit that caused the defect. 1404 and can be used to monitor the output of each of the I / O drivers 1406. Address is for example memory 14
In the conventional BIST technique provided to 02, the source of the fraudulent data received at the bonding pad 1416 is unknown.

The embodiment shown in FIG. 14 includes a specific example of accessing data in the embedded memory 1402, which is used to introduce and monitor signals for any other series of circuit blocks. Is also true.

Special contact pads can also be used not only to isolate defects, but also to enable redundant circuits that are used to replace defective circuits. FIG. 16 illustrates one embodiment of a test circuit on a test die that uses special contact pads to identify defective circuit blocks and enable redundant circuits to replace the defective circuit blocks. I have. This embodiment also uses the example of accessing data in an embedded memory, but can be extended to one of a series of circuits having redundant circuits.

FIG. 16 illustrates a redundant I / O that can be replaced with a defective I / O interface 1404.
It includes an interface 1405. The output of memory 1402 is provided to both I / O interfaces 1404, 1405. The output of the I / O interface 1404 can be monitored by the test die via a special contact pad 1415, and the output of the redundant I / O interface 1405 can be monitored by the test die via a special contact pad 1417. Can be. If the output of the I / O interface 1404 indicates as expected that the output of the I / O interface 1404 is operating properly, provide the signal on line 1423 to the I / O driver 1406 Multiplexer 140
8 comprises the control signal on line 1421. However, I / O interface 1404
Output indicates that the I / O interface 1404 is not operating properly, and if the output of the redundant I / O interface 1405 is as expected, Multiplexer 1408 is configured with control signals on line 1423 so that signals can be provided to I / O driver 1406. The signal output by the multiplexer 1408 can be monitored via a special contact pad 1419.

The control signal on line 1423 can be driven by switch 1410 to the appropriate voltage level or logic state. Special contact pad 1417,1 according to TOGGLE signal
The voltage V3 or V2 will be selected in response to monitoring the signal at 415. The TOGGLE signal can be controlled by a test circuit on the test die via another special contact or bonding pad.

FIG. 15 illustrates a switch 1500 that is one embodiment of the switch 1410 of FIG. Other embodiments of the switch 1410 can be used. The switch 1500
The PMOS transistor included in the PMOS transistor is energized to the ON state by coupling its gate to ground, its source is coupled to the power supply VDD, and its drain is connected to the signal line 1.
421. Switch 1500 also includes a fuse element 1504 coupled between signal line 1421 and ground. The fuse element 1504 can be a metal fuse, a resistance fuse, or a memory element. When fuse element 1504 blows in response to the TOGGLE signal, signal line 1421 is pulled to VDD and the signal on line 1425 is output, for example, by multiplexer 1408. If the fuse element 1504 does not blow, the signal line 1421 is pulled to ground by the fuse
The signal on 23 is output, for example, by multiplexer 1408. Fuse element 1504 can be blown using several well-known techniques, including the use of laser pulses or current. As an example, a special contact pad can be used to provide a current to cut fuse element 1504.

FIG. 17 shows an alternative embodiment of the redundancy mechanism of FIG. In FIG. 17, a plurality of fuse groups 1702, 1704, 1706, 1708 can be arranged before and after the I / O interface. When one of the I / O interfaces is identified as defective, the defective I / O interface can be isolated by a suitable fuse group. For example, if the I / O interface 1404 is defective and the I / O interface 1405 is operating properly, disconnect the fuse group 1704, 1708 to isolate the I / O interface 1404. Is possible. The fuse groups 1704, 1708 are
It is possible to cut through special contact pads (not shown) that provide one or more signals that carry a large current to the device. It is also possible to use alternative means for blowing the fuse.

As described above with respect to FIG. 3, special contact pads can be used with on-chip test circuits to test product circuits. FIG. 18 illustrates the use of one (or more) special contact pads 1810 to provide a clock signal, a reset signal,
9 illustrates one embodiment of providing an enable signal, or other control signal, to a BIST circuit 1802. In response, BIST circuit 1802 provides one or more test signals to internal circuit 1804 and / or internal circuit 1806. The results of the internal test are then monitored at bonding pad 1808 (or, alternatively, another special contact pad). In another embodiment, a special contact pad may be used to provide an enable or clock signal to any other internal circuitry.

Similarly, as shown in FIG. 19, one (or more) special contact pads 1910
Can be used to provide a clock signal, reset signal, enable signal, or other control signal to the shift register elements 1906, 1908 of the SCAN circuit.
The SCAN circuit couples between bonding pads 1906, 1908 (or alternatively one or more special contact pads) that can receive SCAN input data SI and provide SCAN output data SO It is possible to do.

In an alternative embodiment, one or both of the pads 1212 can be special contact pads. This increases design flexibility in the location and use of the SCAN circuit. For example, this allows testing of a variety of different internal circuits or circuit blocks using a number of SCAN regions or circuits that differ in size and complexity from one another. Test Methodologies and Test Assemblies The test dies generated by one of the multiple design methodologies described above can be used to test or monitor product die signals using various test assemblies.

FIG. 20 is a side cross-sectional view of one embodiment of a test assembly 2000 for performing a wafer-level sort test of a product die 2011 by a test die 2010. The product die 2011 can be the product die 300 of FIG.
0 can be the test die 400 of FIG.

The test assembly 2000 includes an interconnect and support substrate 2008, a test die 2010,
And Product No. 2012. The interconnect and support substrate 2008 provides an electrical interconnect between the test die 2010 and the host 2002. The substrate 2008 also includes a test die
Provide structural support for 2010. Substrate 2008 may be one or more printed circuit boards (PCBs) that perform electrical interconnect and support functions. The substrate 2008 can be attached to a structure that supports the wafer 2012 (for example, a wafer prober or chuck (not shown)).

The host 2002 communicates with the test die 2010 via the board 2008. Host 2002 starts and stops testing, catalogs test results and displays them to users,
Alternatively, a signal for transmitting other test data to the test die 2010 can be transmitted. Any type of host may be used, including a general purpose computer, ATE, or any other control logic.

The test die 2010 includes special contact pads 2006 and bonding pads 2004. Spring contact elements 2020, 2018 are arranged on those pads. Product dies 2011 are formed on a wafer 2012, which can include other product dies 2011. Wafer 2012
Can be placed on a suitable support structure such as a vacuum chuck (not shown).

The spring contact elements 2018 are formed in a predetermined arrangement so as to provide an electrical connection between the bonding pad 2004 and the bonding pad 2014 when the test die 2010 is biased toward the product die 2012. You. Spring contact element 2020 provides an electrical connection between special contact pad 2004 and special contact pad 2016 when test die 2010 is biased toward product die 2012. In one embodiment, the contact element
2018 shows bonding pads arranged in a grid array pattern on die 2011
It is possible to arrange in a corresponding grid array pattern to contact 2014. The spring contact elements 2020 are aligned within a predetermined grid array pattern, external to the grid array pattern, or the grid to make electrical contact with corresponding special contact pads 2016 on the die 2011. It is possible to disperse and arrange in an array pattern. Alternatively, the spring contact elements 2018 can be arranged in a peripheral pattern such that they contact the bonding pads 2014 located on the die 2011 in a corresponding peripheral pattern. Spring contact element 2020
Aligned within a predetermined peripheral pattern, aligned outside of the peripheral pattern, or within an area surrounded by the peripheral pattern so as to make electrical contact with a corresponding special contact pad 2016 on the die 2011. It is possible to arrange and arrange. In yet another embodiment, the spring contact elements 2018 can be arranged in a lead-on-center arrangement to align with the corresponding lead-on-center bonding pads 2014, and the spring-contact element 2020 can have a corresponding special contact. It can be located inside or outside of the lead-on center arrangement to align with the pad 2016. In yet another embodiment, the bonding pads 2014 and special contact pads 2016 can be arranged in any other arrangement.

When the test die 2010 is biased toward and contacts the product die 2011, one or more of the product circuits may be simultaneously or sequentially tested.
Can be tested by the test circuit of FIG. Product die 2011 can also be tested as a whole. The wafer 2012 may include a number of product dies 2011, and the test dies 2010 may step across the wafer 2012 to test each product die. In the alternative embodiment shown in FIG. 21, multiple test dies 2010 are used in parallel to test multiple product dies 2011 on wafer 2012, thereby increasing test throughput. The test methodology shown in FIG. 21 can be extended so that the test die wafer 2009 simultaneously tests the corresponding product die wafer 2012.

FIG. 20 shows that the test die 2010 has bonding pads 2014 and special contact pads.
It shows that it has contact elements 2018 and 2020 to communicate with 2016 respectively, but it is also possible to use a number of independent test dies to probe special contact pads 2016 and / or bonding pads 2014. It is possible. For example, a first test die including a bonding pad 2004 having a spring contact element 2018 attached thereto.
It is possible to use 2010 first to make contact with the bonding pads 2014 of the product die 2011. The first test die is capable of functionally testing the product die 2011 as a whole. Subsequently, special contact pads 2006 and spring contact elements
It is possible to use a second test die 2010 including 2020. The second test die 2010 can be used to test one or more of the product circuits of the product die 2011 simultaneously or sequentially. In another embodiment, it is possible to use multiple test dies that mix spring contact elements 2018,2020.
The number of test dies and the configuration of the test dies are determined by one or more of the design methodologies described above.

In an alternative embodiment, as shown in FIG. 22, it is possible to attach the spring contact elements 2018, 2020 to the bonding pads 2014 and special contact pads 2016 on the die 2011. In yet another embodiment, some of the spring contact elements 2018, 2020 can be attached to the test die 2010 and some of the spring contact elements 2018, 2020 can be attached to the die 2011.

Also, the bonding pads 2016 and special contact pads 2016 can be of different heights. For example, as shown in FIG.
It is possible to make 14 higher than the special contact pad 2016 (or vice versa).
In this embodiment, probes 2018, 2020 extend to different depths (or have different heights). That is, the probe 2020 extends to a position lower than the probe 2018 to make contact with the special contact pad 2016. In yet another embodiment, the bonding pads 2004 and the special contact pads 2006 of the test die 2010 can have different heights from each other.

FIG. 24 is a side sectional view of a spring contact element 2400 which is an embodiment of the spring contact elements 2018 and 2020 of FIGS. 20 to 23. The spring contact element 2400 has a base
2402, an elongated elastic member 2404, an elongated contact tip 2406, and a pyramid-shaped contact structure 2408. Applicant's co-pending US patent application Ser. No. 08 / 526,246 (1995
(Filed September 21), and applicant's co-pending US patent application Ser. No. 08 / 558,332 (Jan.
Filed Jan. 15), and applicant's co-pending US patent application Ser. No. 08 / 789,147 (Jan.
Applicant's co-pending US patent application Ser. No. 08 / 819,464, filed Mar.
Applicant's co-pending US patent application Ser. No. 08 / 189,761 (November 1998)
Many other embodiments of the spring contact element can be used, including those disclosed in US Pat.

[0086] The structure 2406 can be of any shape. FIG. 25 illustrates one embodiment of a structure 2406 with a relatively wide end for contacting the member 2404 and a relatively narrow end for supporting a pyramidal contact structure 2408. have.

FIG. 26 illustrates one embodiment of a pyramid-shaped contact structure 2408. Other shapes can be used. The structure 2408 can advantageously be much smaller than the typical tungsten probe tip of a cantilevered probe and the C4 contact ball of flip chip probe card technology. Pyramid contact structure 2408
May have a length dimension 2414 and a width dimension 2416 of about 1-5 μm. In alternative embodiments, the length dimension 2414 and the width dimension 2416 can be sub-micron. The small size of the contact structure 2408 allows a special contact pad to be smaller than a bonding pad. As mentioned, if the special contact pad is smaller than the bonding pad, the product die 2011
It is possible to add a special contact pad to an integrated circuit such as this without increasing the die size. Furthermore, small special contact pads can be arranged between the solder ball bonding pads.

FIGS. 43A and 43B show another spring contact element embodiment disclosed in US patent application Ser. No. 09 / 189,761. The spring contact element 4300 is coupled to the substrate 4306 and has an elongated elastic member 4304, a tip structure 4308, and a blade 4302. Blades 4302 are used to make electrical connections with bonding pads or special contact pads. Blade 4302 can be advantageously used to provide good electrical connection to contacted bonding pads or special contact pads when cutting, slicing, or penetrating the top surface of the pad. It is.
The blade 4302 can be positioned on the tip structure 4308 in a substantially horizontal direction, or in any other direction.

FIGS. 44A and 44B are perspective and side views illustrating another embodiment using a blade on the tip structure of a spring contact element. Blade 4400 is a blade having a plurality of heights disposed on tip structure 4406. The blade 4400 has a tip structure 4406
Main blade 4402 towards the front edge of the rear blade and rear blade towards the tip structure 4406
4404.

FIG. 45 is a perspective view showing another blade structure formed on the tip structure 4500. The blade of FIG. 45 is formed having a substantially rectangular base 4502 and a generally triangular portion 4504.

FIG. 27 illustrates another embodiment of a test assembly 2700 for performing a wafer-level sort test of a product die 2011. In this embodiment, two (
It is possible to use a test die 2010 (or more than two) to test multiple different product circuits of a single product die 2011 simultaneously or sequentially. When testing a single product die using multiple test dies, the physical mapping or location of the bonding pads 2014 and special contact pads 2016 will determine which test die tests which product circuit of the product die 2011 or It will determine whether to monitor.
Each test die must contact all of the pads that need to be tested by the test die.

[0092] The plurality of test dies of the assembly 2700 can be generated by the design methodology described above. For example, determine (eg, via software tool 608 in FIG. 6) that the test circuitry required to test the product circuits of product die 2011 is best implemented in a number of different process technologies (eg, BiCMOS and CMOS). It is possible to create different test dies to support test circuits with different process technologies. In another embodiment, the software tool 608 is configured such that some of the required test circuits are best implemented in analog circuits on a first test die, whereas the required test circuits are different in a second test die. It is possible to determine what is best performed in digital circuitry on the test die.

FIG. 28 shows another test assembly 2800 in which two (or more) product dies 2011 are tested by a single test die 2010. In this embodiment, a single test die 2010 may include multiple tests that can be performed (simultaneously or non-simultaneously) on both product dies. In one embodiment, test die 2010 may include a single test circuit having multiple interconnect points or pads for providing replicated signals to multiple product dies 2011. In an alternative embodiment, test die 2010 may include multiple replicated test circuits for contacting multiple product dies. Alternatively, each product die 2011
Can include a unique circuit that can be tested by a single test die 2010.

The test assembly 2900 of FIG. 29 converts a plurality of product dies 2011 to a plurality of test dies 20.
1 illustrates one embodiment of a hierarchical approach to testing with 10; As shown in FIG. 29, each product die 2010 can be tested by a separate test die 2010. Test die 2902 is a second level level that communicates with host 2002 to support or control multiple test dies 2010. For example, test die
2902 may be a shared resource that includes circuits commonly used by all of the test dies 2010. It is advantageous to move this common circuit to a test die 2902, for example, to reduce the size of the test die 2010. For example, an automatic pattern generator (APG) circuit or other test vector generation or storage circuit can be moved to test die 2902 and shared by each of multiple test dies 2010. Then
Test die 2010 may simply include a formatter, driver, and timing generator for the pattern provided by test die 2902. This eliminates the need to duplicate the APG circuit on each of the test dies 2010.

The test dies 2902 can simultaneously support all test dies 2010 by simultaneously providing a common test pattern to each of the test dies 2010, and the test die 2902 can be one or two of the test dies 2011. For one or more,
It is possible to perform an integrated function and optionally (eg, continuously) provide tests or patterns.

The design methodology described above can determine when it is advantageous to split a test circuit into one or more test dies. For example, a relatively large circuit (APG
) Can be shared by two or more test dies, the circuit can be moved to a shared test die 2902 to reduce the die size of each test die 2010.

FIG. 30 shows a test assembly 3000 including a shared test die 2902. In this embodiment, each test die 2010 is dedicated to each corresponding product die 2011 and provides a different test for each product die. But test die 29
02 can be used simultaneously or in an integrated manner to provide a shared test or test pattern to the test die 3002 for use by each of the product dies 2011.

The embodiments shown in FIGS. 21 to 28 may include one or more test dies and one or more product dies (contact structures) designed in accordance with the design methodology described above.
(Via 2018, 2020) direct electrical connection. FIG. 31 illustrates a test assembly 3100 that performs a wafer-level sort test of a product die 3111 with a test die 3104. The test die 3104 includes a contact 3108 and an interconnect substrate 3106.
Is electrically connected indirectly to the product die 3110 via the. Contact 3108 may be an epoxy ring probe card, a membrane probe card, or any other type of probe card assembly, such as those provided by FormFactor, Inc. (Livermore, CA) and Wentworth Laboratories (Bookfield, CT). It can be any type of probe card.

The test die 3104 is the test die 400 of FIG. 4 generated by the above-described design methodology.
One or more test dies can be used. Product die 3111
Again, this may be one or more product dies, such as product die 300 of FIG. 3 generated by the design methodology described above. Product die 3111, other product die 31
Formed on a wafer 3110 that can include 11. Wafer 3110 can be placed on a suitable support structure, such as a vacuum chunk (not shown). Product die
3111 also includes bonding pads 3114 for receiving contact elements 3112 and special contact pads 3116. The contact element 3112 can include a cantilevered probe needle, a contact ball of a membrane probe card, a spring contact element as described above, or any other electrical contact element.

The interconnect substrate 3106 provides electrical interconnection between the test dies 3104 and the contacts 3108. As shown in FIG. 31, the test die 3104 can be placed on the upper portion 3120 of the substrate 3106. Alternatively, test die 3104 may be located on lower portion 31 of substrate 3106.
22 is possible. In yet another embodiment, the test die 3104 comprises:
It is possible to place it directly on the contact 3108.

To electrically connect test die 3104 to two or more product dies 3111, interconnect substrate 3106 may include sufficient routing and contacts 3108 may have a sufficient number of contacts. Element 3112 can be included. For example, an entire product die wafer can be tested simultaneously by one or more test dies.

In one embodiment, test die 3104 can be mounted on substrate 3106 and its bonding pads and special contact pads can be bonded out to substrate 3106, or packaged first in a suitable semiconductor package. Can then be electrically connected to the substrate 3106.

The substrate 3106 also provides structural support for the test dies 3104 and contacts 3108. Substrate 3106 may be one or more PCBs that perform electrical interconnect and support functions, and may be attached to a structure that supports wafer 3110 (eg, a wafer prober or chuck not shown). Is possible.

The host 3102 communicates with the test die 3104. The host 3102 sends signals to start and stop the test, create a catalog of test results and display it to the user, or send other test data to the test die 3104. Any type of host can be used, such as a personal computer, ATE, or any other control logic.

FIG. 32 shows a test assembly 3200, which is an embodiment of the test assembly 3100, in which the contacts 3108 include a probe card 3120. Test assembly 3200 includes test head 3204 and probe card assembly 3210.
Probe card assembly 3213 includes an interconnect board 3106 (eg, a test load board), a test die 3104, and a probe card 3210. Test die 3104
It can be located below the 3106 or on the probe card 3210 itself.

The probe card 3210 is a cantilevered or needle probe card that includes a cantilevered probe 3220 that provides for sending and receiving signals to and from the product die 3111. Probe 3220 can be constructed from any suitable conductive material, including tungsten. As shown in a plan view of the probe card 3220 in FIG. 33, the probe 3220 is connected to a contact pin or point 3304 that contacts a test circuit on the test die 3104. The probe card 3210 can be fixed to the substrate 3106 via one or more fixing pins 3302, screws, or other fixing means.

The probe 3220 is arranged to contact a special contact pad 3116 when the probe assembly 3213 is biased toward the product die 3111. In an alternative embodiment, the product circuit is first tested by probing special contact pads 3116 and then product die 3111 by probing bonding pads 3114.
It is possible to use a separate probe card to test as a whole.

FIG. 34 shows that probes for probing one or more special contact pads 3116 and one or more bonding pads 3114 can be provided on the same probe card 3410. 7 shows another possible embodiment. In this embodiment, probe 3220 can send and receive signals to and from special contact pad 3116 as many times as probe 3218 sends and receives signals to and from bonding pad 3114. It is. Probe 3118 is connected to bonding pad 31
It is formed with a predetermined alignment corresponding to the 14 alignments. As shown in the plan view of the probe card 3410 in FIG. 35, the probe 3118 forms a relatively rectangular shape that will contact the surrounding bonding pads 3114 on the product die 3111. The probe 3120 is not generally arranged in the same predetermined alignment as the probe 3118, but extends into a region surrounded by the probe 3118 (and the bonding pad 3114). In an alternative embodiment, probe 1320 is a probe
3118 can be outside the area enclosed by
18 and the bonding pad 3114 can be arranged in the same predetermined alignment. In another embodiment, the probe 3118 can be configured in a lead-on-center arrangement or other predetermined arrangement to align with a similar arrangement of the bonding pads 3114 on the product die 3111, and the probe 3120 , Can be configured inside or outside the array of probes 3118 to align with corresponding special contact pads 3116. In still other embodiments, bonding pads 3114 and special contact pads 3116 can be configured with any other alignment.

The probe card 3410 includes one or more contact pins 3502 that provide an electrical connection between the substrate 3104 and the probes 3218, 3220. Test die 3104 (Fig. 3
It can be located on the probe card 3410 (as shown in FIG. 3), or it can be located outside the probe card 3410 (eg, on the substrate 3106), in which case the electrical connections are Wired to 3502 or directly connected to interconnection point 3304.

In the embodiment shown in FIGS. 32 to 35, the bonding pad 3114 and the special contact pad 3116 can have different heights from each other. For example, the bonding pad 3114 can be higher (or lower) than the special contact pad 3116. In this embodiment, the probes 3118, 3120 can extend to different depths. That is, it is possible that the probe 3120 extends to a position lower than the probe 3118 and comes into contact with the special contact pad 3116.

FIG. 36 shows another embodiment of test assembly 3100, test assembly 3600.
Is shown. The test assembly 3600 includes a test head 3204 and a probe card assembly 3613. The probe card assembly 3613 is connected to the interconnect board 3106
, A test die 3104, and a membrane probe card 3620. Membrane probe card 3620 includes contact balls 3618, 3620 that, when urged into contact with product die 3111, provide signals to and from bonding pads 3114 and special contact pads 3116. The contact balls or probes 3618, 3620 can be constructed from any suitable conductive material, including solder.

As shown in the plan view of the probe card 3610 in FIG. 37, the contact balls 3618 can be arranged in a grid array so as to contact the bonding pads 3114 arranged in a corresponding grid array pattern. The contact balls 3620 can be arranged in a predetermined grid array, or can be interspersed in a grid array pattern as shown in FIG. 37 to match special contact pads 3116 on the product die 3111. Is possible. Alternatively, as shown in FIG.
Can be arranged in a peripheral pattern so as to contact the bonding pads 3114 arranged in the corresponding peripheral pattern. The contact balls 3620 can be arranged in a predetermined peripheral pattern outside the peripheral pattern or in the peripheral pattern as shown in FIG. 38 to align with the corresponding special contact pads 3116. In yet another embodiment, the contact balls 3618 can be arranged in a lead-on-center arrangement to align with the lead-on-center bonding pads on the product die 3110, with the contact balls 3620 being the corresponding special contact pads It can be placed inside or outside of the lead-on-center arrangement so as to align with.

In another embodiment, the contact ball 3620 can be replaced with the previously described spring contact element. In this embodiment, the special contact pads 3116 can be selectively arranged in a grid array of bonding pads 3114 as shown in FIG. It is possible to make the size smaller than the size of the bonding pad 3114 as shown in FIG. 12 so that the size does not increase. In still other embodiments, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

The test die 3104 is electrically connected to one or more probes 3620 via the substrate 3106. Test die 3104 is also electrically connected to one or more probes 3618 via substrate 3106. Alternatively, test die 3104 may be located directly on probe card 3610, or may be located at any other location in test assembly 3600.

FIGS. 36-38 show that a single membrane probe card can be used to communicate with special contact pads 3116 and bonding pads 3114, but in an alternative embodiment. It is possible to probe special contact pads 3116 and bonding pads 3114 using separate membrane probe cards. That is, using one or more probe cards, first, only the special contact pads 3116 are brought into contact with one or more contact balls 3618 and one or more of the product dies 3111 It is possible to test product circuits. Subsequently, using one or more additional probe cards, the bonding pads 3114 can be sequentially contacted with one or more contact balls 3220 to test the product die 3111 as a whole. is there. In yet another embodiment, the contact ball 3618
, 3620 can be used.

In an alternative embodiment, bonding pads 3114 and special contact pads 3116 can be of different heights. For example, the bonding pad 3114 can be higher (or lower) than the contact pad 3116. In this embodiment, the contact balls 3218, 3220 can have different heights from each other. That is, the contact ball 3220 can extend to a position lower than the contact ball 3218 to make contact with the special contact pad 1516. Alternatively, other probe elements, such as spring contact elements, can be used to probe shorter special contact pads 3116.

FIG. 39 shows a test assembly 3900, another embodiment of a test assembly 3100, that includes a test head 3204 and a cobra-type probe card assembly 3913. The cobra probe card assembly is available from Wentworth Laboratories (
Brookfield CT.). The probe card assembly 3913 includes an interconnect substrate 3106, a space transformer (wired or ceramic) 3908, and a head assembly 3907. The head assembly 3907 has an upper plate 3909
, Spacer 3910, lower plate 3911, test die 3104, and cobra probe 3918, 3920
including. When activated toward product die 3111, probes 3918 and 3920 provide for the transmission and reception of signals to and from bonding pad 3114 and special contact pad 3116, respectively.

The test die 3104 is electrically connected to one or more probes 3920 and
One or more probes 3918 are also electrically connected. The test die 3104 is connected to the lower side of the upper die 3909 and the upper side 3902 of the lower plate 3911 as shown in FIG.
It can be located on 3106 or at any other location in test assembly 3900.

Probes 3918 are typically formed in a grid array and contact bonding pads 3914 arranged in a corresponding grid array pattern. Probe 3920
Can be connected to special contact pads 1816, aligned in a predetermined grid array and distributed outside the grid array pattern or dispersed within the grid array pattern as shown in FIG. Alternatively, as shown in FIG. 41, the probes 3918 are arranged in a peripheral pattern, and the product die 31 is arranged in a corresponding peripheral pattern.
The probe 3018 can be brought into contact with the bonding pads 3114 arranged on 11. The probe 3920 can be probed with a specific peripheral pattern, external to the peripheral pattern, or aligned within the peripheral pattern as shown in FIG. In yet another embodiment, the probes 3918 can be arranged in a lead-on-center arrangement to align with the lead-on-center bonding pads on the product die 3111, and the probe 3920 is
It can be aligned inside or outside the lead-on-center arrangement to align with the corresponding special contact pads. In yet another embodiment, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

Although FIGS. 39-41 show that a single probe card assembly can be used to communicate with special contact pads 3116 and bonding pads 3114, an alternative embodiment is shown. It is possible to probe special contact pads 3116 and bonding pads 3114 using separate probe cards. That is, using one or more probe cards, first, only the special contact pads 3116 are brought into contact with one or more probes 3920 to make the product die 3111.
It is possible to test related product circuits. Subsequently, the product die 3111 can be tested as a whole by using one or more additional probe cards to sequentially contact the bonding pads 3114 with one or more probes 3018. . In yet another embodiment, multiple probe card assemblies having a mix of probes 3918, 3920 can be used.

In an alternative embodiment, the bonding pad 3114 and the special contact pad 3116 can be of different heights. For example, bonding pads
It is possible for 3114 to be higher (or lower) than contact pad 3116. In this embodiment, the probes 3918, 3920 can extend to different depths (or have different heights). That is, probe 3920 can extend to a position lower than probe 3918 to make contact with special contact pad 3116.

FIG. 42 shows a test head 3204 and a probe card assembly 4213 (eg, Form
FIG. 18 illustrates another embodiment of a test assembly 3100, test assembly 4200, including Factor, Inc. (provided by Livermore, CA). One embodiment of a probe card assembly 4213 is disclosed in PCT International Application No. WO 96/38858. The probe card assembly 4213 includes the probe card 4204, an interposer (interpo
ser) 4206, a space transformer 4210, and spring contact elements 4218, 4220. Product die 3
When biased toward 111, the spring contact elements 4218, 4220 provide for sending and receiving signals to and from the bonding pad 3114 and the special contact pad 3116, respectively.

The test die 3104 is electrically connected to one or more probes 4220 and is electrically connected to one or more probes 4218. Interconnection is provided by probe card 4204, intervening means 4206, or space converter 4210. The test die 3104 can be located below the intervening means 4206, as shown in FIG.
It can be located at any other location of the 4200.

The spring contact elements 4218 are provided in a predetermined arrangement to provide for sending and receiving signals to and from the corresponding bonding pads 3114. In one embodiment, probe 4218 is
They are arranged in a grid array pattern. The spring contact elements 4220 can be aligned with a predetermined grid array, distributed outside the grid array pattern, or dispersed within the grid array pattern to align with the corresponding special contact pads 3116. In another embodiment, the spring contact elements 4218 can be arranged in a peripheral pattern. The spring contact elements 4220 can be arranged in an area surrounded by a predetermined peripheral pattern, outside of the peripheral pattern, or distributed in the peripheral pattern to align with the corresponding special contact pad 3116. . In yet another embodiment,
The spring contact elements 4218 can be arranged in a lead-on-center arrangement, and the spring contact elements 4220 can be arranged inside or outside the lead-on-center arrangement to align with corresponding special contact pads. In still other embodiments, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

FIG. 42 illustrates a special contact pad 3116 using a single probe card assembly.
And it is possible to communicate with bonding pads 3114, but in an alternative embodiment, a separate probe card assembly (or probe card) may be used to provide special contact pads 3116 and bonding pads 3114. Can be probed. That is, using one or more probe card assemblies, first contacting only the special contact pads 3116 with one or more spring contact elements 4220 to one or two of the product dies 3111 It is possible to test the above product circuit. Subsequently, using one or more additional probe card assemblies, bonding pads 3114 may be connected to one or more spring contact elements 42.
It is possible to test product die 3111 as a whole by contacting 18. In yet another embodiment, multiple probe card assemblies having a mix of spring contact elements 4218, 4220 can be used.

In an alternative embodiment, the bonding pad 3114 and the special contact pad 3116 can be of different heights. For example, bonding pads
It is possible for 3114 to be higher (or lower) than special contact pads 3116. In this embodiment, the probes 4218, 4220 can extend to different depths (or have different heights). That is, probe 4220 is replaced by probe 4218
It is possible to extend to a lower position to make contact with a special contact pad 3116.

In an alternative embodiment, spring contact elements 4218, 4220 can be attached to bonding pads 3114 and special contact pads 3116 on product die 3111. In this embodiment, the space transformer 4210 can include pads for making contact with the spring contact elements 4218, 4220. In yet another embodiment, the spring contact element 4218
Or, attach some of the 4220 to the space transformer 4210 and use the spring contact element 4218 or 4220
Can be attached to the product die 3111.

A product die generated by the above-described design methodology can also be inserted into a socket and tested by a test die. The product die can be packaged into any known package for semiconductor integrated circuits and may not be packaged (e.g., chip-scale configuration
)). Any common known socket can be used to support the product die. The test die can be attached to a printed circuit board, can be in direct contact with the product die (eg, via a spring contact element, etc.), or can be attached to the product die via contacts, edge connectors, etc. Indirect contact is also possible.

FIG. 46 is solder-down for mounting to a printed circuit board (PCB) 4610 and for making pressure contact with the bonding pads 4612 and special contact pads 4614 of the LGA package 4604. (Surface mounting) One embodiment of an LGA socket 4600 is shown. The LGA package 4604 can include a product die designed according to the design methodology described above. As used in this document, the term "socket"
Means an electrical component having an interconnecting element suitable for making an electrical connection with a terminal or connection point of another electrical component. The socket shown in FIG. 46 is intended to enable a semiconductor package to be detachably connected to a circuit board. Another embodiment of the socket 4600 is disclosed in applicant's U.S. Patent No. 7,772,451.

The PCB 4610 has a plurality of terminals or pads 4618, and the package 4604 has a plurality of bonding pads 4612 and special contact pads 4614. Socket 4600
Provides a means for electrically interconnecting terminals 4618 to pads 4612, 4614. A test circuit provided on the PCB 4610 or a test circuit in communication with the PCB 4610 provides a signal to the pads 4612, 4614 through the socket 4600, or
It is possible to monitor the signal from 2,4614. For example, the programmable circuits in package 4604 can be programmed or monitored via spring contact elements 4616, special contact pads 4614, and / or pads 4612.

The socket 4600 includes a support substrate 4608 formed from, for example, a conventional PCB material. The support substrate 4608 includes a spring contact element 4616 formed on its top surface and a pad 4622 formed on its bottom surface. The spring contact element 4616 is for the package 4604 to come into contact with the pads 4612 and 4614 of the package 4604 when urged downward by the force applied to the upper side of the package 4604 by the holding means 4602. It is also possible to use other contact elements besides the spring contact elements. The support substrate 4608 also includes conductive means 4624 for providing electrical interconnection between the spring contact elements 4616 and the pads 4622.
including. In an alternative embodiment, the spring contact element 4616 can be connected directly to the terminal 4618.

A contact ball (such as a conventional solder ball) is located on the bottom surface of pad 4622. The contact balls 4622 function as contact structures disposed on the bottom surface of the support substrate 4608 to contact corresponding pads or terminals 4618 on the PCB 4610. Other electrical contact structures can be used.

The socket 4600 also includes a frame 4606 attached to the PCB 4602. The frame 4606 includes lands 4626 to support the package 4604. socket
4600 also includes holding means 4602 disposed on frame 4626 and package 4604. The retaining means 4602 retains the package 4604 on the land 4626 so that the spring contact element 4616 remains in electrical contact with the pads 4612, 4614. Any other suitable mechanical means, such as a spring clip, can be used for the retaining means 4602.

FIG. 47 shows another embodiment of a socket 4600 in which a test die 4630 is located on a PCB 4610. The test die 4630 can be designed according to the design methodology described above. Terminals or pads 4618 can be formed on test die 4630 to provide an electrical interface with contact balls 4620. In another embodiment, the spring contact element 4616 can be connected directly to the terminal 4618.

Additionally and / or alternatively, one or more spring contact elements 4616 may be attached to pads 46
It can be attached to 12,4614. In this embodiment, the spring contact element is
Capable of contacting pads or terminals on the upper side 4632 of the support substrate 4608,
Alternatively, the spring contact element can be in direct contact with terminal 4618. .

Although the above description has described the invention with reference to specific exemplary embodiments thereof, various modifications and changes can be made to those embodiments without departing from the broader spirit and scope of the invention. Clearly, it is possible. Therefore, the specification and drawings are to be regarded as illustrative of the invention and not as limiting.

[Brief description of the drawings]

FIG. 1 is a design methodology for designing products and test dies according to one embodiment of the present invention.

FIG. 2 is a block diagram of an integrated product and test circuit design according to one embodiment of the present invention.

FIG. 3 is a block diagram of a product die that is created after partitioning of the integrated design of FIG.

FIG. 4 is a block diagram of a test die generated after partitioning of the integrated design of FIG.

FIG. 5 is a block diagram of one embodiment of a test circuit in a test die.

FIG. 6 is a design methodology for product and test circuit design according to another embodiment of the present invention.

FIG. 7 is one embodiment of a process for determining the partitioning of product and test circuits.

FIG. 8 is a design methodology for product and test circuit design according to yet another embodiment of the present invention.

FIG. 9 is a block diagram of one embodiment of a computer system capable of implementing the processes of FIGS. 1 and 6-8.

FIG. 10 is a logic diagram of one embodiment of a special contact pad coupled to an internal circuit node via a bidirectional buffer.

FIG. 11 is a plan view of one embodiment of an integrated circuit having bonding pads aligned with a grid pattern, special contact pads not aligned with the grid pattern, and special contact pads aligned with the grid pattern.

FIG. 12 is a side sectional view of a special contact pad disposed between two bonding pads having contact balls.

FIG. 13 is a plan view of one embodiment of an integrated circuit having lead-on-center bonding pads, internal circuitry, and special contact pads for testing the internal circuitry.

FIG. 14 is a block diagram of one embodiment of a sequential circuit and a special contact pad for testing the sequential circuit.

FIG. 15 is a circuit diagram of one embodiment of the switch of FIG.

FIG. 16 is a block diagram of one embodiment that uses special contact pads to isolate defective circuit blocks and enable redundant circuit blocks.

FIG. 17 is a block diagram of another embodiment that uses special contact pads to isolate defective circuit blocks and enable redundant circuit blocks.

FIG. 18 is a block diagram of one embodiment that uses special contact pads to enable or provide stimulation to a circuit under test.

FIG. 19 is a block diagram of one embodiment that uses special contact pads to provide control signals to a scanning circuit.

FIG. 20 is a side sectional view of a test assembly for testing a product die.

FIG. 21 is a side cross-sectional view of a test assembly for testing multiple product dies on a test wafer.

FIG. 22 is a side cross-sectional view of a test assembly including a spring contact element attached to a product die.

FIG. 23 is another embodiment of a test assembly in which the spring contact elements, bonding pads, and special contact pads have different heights.

FIG. 24 is a side cross-sectional view of one embodiment of a spring contact element.

FIG. 25 is a perspective view of one embodiment of a contact tip structure and a pyramidal contact shape of the spring contact element of FIG. 24.

FIG. 26 is a perspective view of one embodiment of the pyramid-shaped contact tip structure of FIG. 25.

FIG. 27 is a side cross-sectional view of one embodiment of a test assembly including multiple test dies for testing one product die.

FIG. 28 is a side cross-sectional view of one embodiment of a test assembly including a single test die for testing multiple product dies.

FIG. 29 is a side cross-sectional view of one embodiment of a test assembly including one test die shared by another test die.

FIG. 30 is a side cross-sectional view of another embodiment of a test assembly including one test die shared by another test die.

FIG. 31 is a side cross-sectional view of one embodiment of a test assembly including a test die, a contactor, and a product die.

FIG. 32 is a side cross-sectional view of one embodiment of a test assembly having a test die and a probe card having cantilevered probes for probing special contact pads of a product die.

FIG. 33 is a plan view of the probe card of FIG. 32.

FIG. 34 is a side cross-sectional view of another embodiment of a test assembly having a test die and a probe card having a cantilevered probe for probing bonding and special contact pads of a product die. is there.

FIG. 35 is a plan view of the probe card of FIG. 34.

FIG. 36 is a cross-sectional side view of another embodiment of a test assembly having a membrane probe card having contacts for probing bonding pads and special contact pads of a product die.

FIG. 37 is a plan view of the membrane probe card of FIG. 36 with contact balls aligned with the grid pattern and contact balls not aligned with the grid pattern.

FIG. 38 is a plan view of the membrane probe card of FIG. 36 having contact balls aligned with the peripheral pattern and contact balls not aligned with the peripheral pattern.

FIG. 39 is a side cross-sectional view of another embodiment of a test assembly having a cobra-type probe card assembly having probes for probing bonding pads and special contact pads of a product die.

FIG. 40 is a plan view of the tip of the cobra probe of FIG. 39 having a plurality of tips aligned with the grid pattern and another tip not aligned with the grid pattern.

41 is a plan view of the tip of the cobra probe of FIG. 39 having a plurality of tips aligned with the peripheral pattern and other tips not aligned with the peripheral pattern.

FIG. 42 is a side cross-sectional view of another embodiment of a probe card assembly having a spring contact element for probing bonding pads and special contact pads of a product die.

FIG. 43A is a side cross-sectional view of another embodiment of a spring contact element.

FIG. 43B is a perspective view of the spring contact element of FIG. 43A.

FIG. 44A is a perspective view of another embodiment of a spring contact element.

FIG. 44B is a side sectional view of the spring contact element of FIG. 44A.

FIG. 45 is a perspective view of another embodiment of a tip structure for a spring contact element.

FIG. 46 is a side cross-sectional view of one embodiment of a socket for holding a package having special contacts and conventional input, output, and input / output pins. ,

FIG. 47 is a side sectional view of another embodiment of a socket including a test die on a printed circuit board.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/66 G01R 31/28 Q 21/822 H01L 27/04 T 27/04 EKVG (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), JP, KR (72) Inventor Pedersen, David, Buoy 95066, California, United States, Sterling Lane, Scotts Valley 6 (72) Inventor Witten, Ralph, G 95132, California, United States, San Jose, Sierra Road, 5220 F-term (reference) 2G011 AA02 AA15 AB01 AB06 AB07 AC14 AE03 AF07 2G132 AA00 AB01 AC11 AC12 AC14 AG02 AK11 AK29 AL00 AL11 4 M106 AA02 AA08 AC02 AC13 BA01 DJ11 DJ15 DJ18 DJ20 DJ21 DJ23 5F038 AV06 AV13 AV15 BE10 DF05 DF11 DT04 DT07 DT08 DT15 EZ09 EZ20 [Continued Summary] Reduce the size of the product and the manufacturing cost of the product die, as well as the products in the product die. It tends to maintain a high test range of the circuit. The test die can then be used to test multiple product dies on one or more wafers.

Claims (54)

[Claims] 1. A test assembly for testing a product circuit of a product die, the test die having a test circuit for testing a product circuit of the product die, the test circuit comprising: (i) a test circuit; And a test die generated by simultaneously designing the product circuit to generate one integrated design, (ii) dividing the test circuit from the product circuit, and (iii) fabricating the test circuit on the test die. A test assembly, comprising: interconnecting means for electrically coupling the test die to a product die; and interconnecting means for electrically coupling the test die to a host controller in communication with the test die. 2. The test assembly according to claim 1, wherein said test die further comprises a plurality of pads coupled to said test circuit. 3. The test assembly according to claim 2, wherein said plurality of pads comprises: a bonding pad; and a special contact pad for receiving a spring contact element. 4. The bonding pad and the special contact pad have different heights from each other,
The test assembly according to claim 3. 5. The test assembly according to claim 1, further comprising a plurality of contact elements for electrically coupling the test circuit to the product circuit. 6. The test assembly according to claim 5, wherein the plurality of contact elements have different heights from each other. 7. The test assembly according to claim 5, wherein said plurality of contact elements comprise spring contact elements. 8. The test assembly according to claim 5, wherein said plurality of contact elements comprise contact balls. 9. The test assembly according to claim 1, wherein the test circuit is configured to test AC parameters of the product circuit. 10. The test assembly according to claim 1, wherein the test circuit is configured to test DC parameters of the product circuit. 11. The test circuit is configured to program the product circuit.
The test assembly according to claim 1. 12. The test assembly according to claim 1, wherein said test die is formed on a semiconductor wafer. 13. The test assembly according to claim 1, wherein the test circuit is configured to test product circuits of two or more product dies. 14. The apparatus of claim 14, further comprising a second test die electrically coupled to the interconnect means.
The test assembly according to claim 1. 15. The test assembly according to claim 14, wherein said second test die comprises a test circuit for testing a product circuit of said product die. 16. The test assembly according to claim 15, wherein the second test die comprises a test circuit for testing a product circuit of another product die. 17. The test assembly according to claim 14, further comprising a third test die electrically coupled to and communicating with the first test die and the second test die. 18. A circuit for performing a function commonly used by the first and second test dies to test a product circuit of the first and second product dies. 18. The test assembly according to claim 17, comprising: 19. A method for designing a test die for a product die, comprising: simultaneously designing a product circuit and a test circuit for testing the product circuit to generate one integrated design; Splitting the integrated design into a test die including the test circuit and a product die including the product circuit. 20. The method of claim 19, further comprising separately fabricating the test die and the product die. 21. The method of claim 19, further comprising generating a description of an interconnect between the test circuit and the product circuit. 22. The method of claim 19, further comprising determining a test capability of a host controller communicating with the test die. 23. The method of claim 22, further comprising selecting a first test to be performed by the test circuit and a second test to be performed by the host controller. 24. The method further comprising: determining whether the divided test die and product die satisfy a predetermined constraint, and repeating the dividing step and the determining step until the predetermined constraint is satisfied. Item 19. The method according to Item 19. 25. The method of claim 24, wherein the predetermined constraint comprises a physical size of each of the test die and the product die. 26. The method of claim 24, wherein the predetermined constraint includes a cost of manufacturing each of the test die and the product die. 27. The method of claim 24, wherein the predetermined constraint comprises a selected amount of defect coverage for testing the production circuit. 28. The method of claim 24, wherein the predetermined constraint comprises a speed test accuracy of a signal in the product die monitored by the test circuit. 29. The method of claim 24, wherein said predetermined constraints include parameters in a manufacturing process of each of said test circuit and said product die. 30. The apparatus of claim 30, wherein the predetermined constraint is a signal of a signal in the product die monitored by the test circuit.
25. The method of claim 24, comprising an AC timing parameter. 31. The method of claim 24, wherein the determining step further comprises simulating a split of the test die and the product die. 32. The method of claim 24, further comprising creating a plurality of interconnect points on the test die and the product die, wherein the predetermined constraint includes a number of the interconnect points.
The method described in. 33. The method of claim 19, wherein the dividing step further divides the test circuit into a first test circuit and a second test circuit. 34. The dividing step further comprises: placing the first test circuit on the test die.
34. The method of claim 33, wherein the second test circuit is located on the product die. 35. The method of claim 34, wherein said second test circuit comprises a built-in self test (BIST) circuit. 36. The method of claim 34, wherein said second test circuit comprises a SCAN circuit. 37. The method of claim 19, wherein said test circuit is capable of testing a plurality of product dies each having a product circuit. 38. The method of claim 19, further comprising adjusting the test circuit. 39. The method of claim 38, wherein said adjusting step includes adding additional circuitry to said test circuit. 40. The method of claim 38, wherein said adjusting comprises removing some of said test circuits. 41. The method of claim 19, further comprising adding a built-in self test (BIST) circuit to the product die. 42. Designing a plurality of test circuits and product circuits simultaneously to produce an integrated design;
The test circuit is in communication with the product circuit; and dividing the integrated design into a plurality of test dies and a product die, each of the plurality of test dies being at least one of the plurality of test circuits. 20. The method of claim 19, further comprising the steps of: 43. The method of claim 42, wherein each test circuit comprises a unique circuit. 44. A test die, wherein one of the test circuits includes a circuit commonly used by all of the test circuits, and wherein the dividing step communicates the commonly used circuit with another test die. 43. The method of claim 42, further comprising the step of subdividing into. 45. The method of claim 44, wherein said commonly used test circuit comprises a pattern generator. 46. The method of claim 44, wherein the test die having the commonly used test circuit further communicates with a host controller. 47. The method of claim 42, further comprising fabricating the test die and the product die on separate semiconductor wafers. 48. The method of claim 48, further comprising: determining whether the divided test die and product die satisfy a predetermined constraint, and repeating the dividing step and the determining step until the predetermined constraint is satisfied. 43. The method according to claim 42. 49. A medium readable by a computing device, the medium storing a series of instructions for generating a description of a test die and a description of a product die, wherein the instructions cause the computing device to execute. Generating a description of a test circuit and a product circuit to generate an integrated circuit design, wherein the test circuit is for testing the product circuit; and And a medium readable by a computing device that divides into separate descriptions of product dies. 50. The series of instructions further determines whether the test die and product die descriptions meet predetermined constraints, and re-creates the integrated circuit design until the predetermined constraints are satisfied. 50. The medium of claim 49, causing the computing device to perform the steps of: splitting to generate updated descriptions of the test die and product die. 51. A method for testing a circuit of a product die on a semiconductor wafer, the product die comprising:
Having a bonding pad for electrically coupling to a lead of the integrated circuit package, and further comprising a special contact pad for accessing a product circuit but not electrically coupled to the lead of the integrated circuit package. The method comprising: contacting at least one of said bonding pads using a first probe card; and contacting at least one second bonding pad using a second probe card. Including, testing methods. 52. A method for testing a circuit of a product die on a semiconductor wafer, the product die comprising:
Further comprising bonding pads for electrically coupling to the leads of the integrated circuit package, and special contact pads for accessing product circuits but not electrically coupled to the leads of the integrated circuit package. The method comprising: contacting at least one of the bonding pads using a first test die, the first test die having circuitry for testing the product circuit; Using the method to contact at least one second bonding pad. 53. A method for designing a product die for a test die, comprising designing a product circuit to be tested by a predetermined test circuit, and incorporating the product circuit and the test circuit into one integrated circuit design. Splitting the integrated design into test dies and product dies, the test dies including test circuitry, and the product dies including product circuitry. 54. The method of claim 5, further comprising separately fabricating the product die and the test die.
3. The method according to 3.