KR100522070B1 - Test method and assembly including a test die for testing a semiconductor product die - Google Patents

Abstract

A test apparatus 2000 for testing product circuits 202, 302, 304 of product dies 2011, 300. In one embodiment, the test apparatus includes a test die 2010, 400 and an interconnect substrate 2008 for electrically coupling the test die to a host controller 2002 in communication with the test die. The test die may be designed according to a design methodology for a test die and a product die that includes simultaneously designing the test circuits 202A, 402, 404 and the product circuit into a united design 102. The test circuit can be designed to provide a high fault range for the corresponding product circuit, regardless of the amount of silicon area required by the test circuit. The design methodology then divides the united design into a test die and a product die (104). The test die includes a test circuit and the product die includes a product circuit. The product die may include some test circuitry. The article and test die can then be fabricated on separate semiconductor wafers. By dividing the product circuit and the test circuit into separate dies, the embedded test circuit can be eliminated or minimized on the product die. This reduces the size of the product die and reduces the manufacturing cost of the product die while maintaining a high test coverage of the product circuit within the product die. Test dies can be used to test multiple product dies on one or more wafers.

Description

TEST METHOD AND ASSEMBLY INCLUDING A TEST DIE FOR TESTING A SEMICONDUCTOR PRODUCT DIE}

TECHNICAL FIELD The present invention relates to integrated circuit (IC) semiconductor devices, and more particularly to testing devices.

As integrated circuit designs increase in both complexity and density, design methodologies are challenged to form circuits that use design-for-test (DFT) techniques to improve the testability and quality of the final product. have. Test methodologies are also challenged to provide high quality and low cost test solutions. Test methodologies are also challenged to provide high quality and low cost test solutions.

One conventional design methodology involves the process of initial design of integrated circuits using software design means, simulating the overall functionality of the design or of individual circuits within the design, and then generating test vectors by testing the full functionality of the design. do. Test vectors are typically generated by automated software means (eg, automated test pattern generators, ATPG) that provide specific fault coverage or fault simulation for in-product circuits. The test vector is then provided to an automated test device (ATE) or tester in a computer readable file. ATE is used in manufacturing environments to test die in wafer state or in packaged state. As integrated circuit designs become more complex and operate at higher speeds, more demands are placed on test equipment. This trend will increase the price of ATE and increase the manufacturing cost. In addition, as the integrated circuit design becomes more complex, the time required to test the circuit increases, which also increases manufacturing costs.

During wafer level testing of the die, test signals are provided through input or input / output (I / O) bond pads on the die, and the test results are monitored on the output or I / O bond pads. Preferred dies that pass the wafer level test are individualized and typically packaged by electrically connecting the bond pads to the package by bond wires, solder balls or other contact structures. In order to accommodate bonding wires or solder balls, bond pads are generally very large for circuit elements of integrated circuits. Typical bond pad sizes are 100 μm × 100 μm (4 mils × 4 mils). The bond pads are also typically aligned in a regular pattern such as a row or column (lead-on-center) along the periphery of the die or in a grid pattern but generally through the center of the die.

In order to improve the test coverage of individual circuits, DFT means have been developed to embed test circuits into the design itself. As an example, built-in self-test (BIST) circuits can be inserted into designs for testing individual circuit blocks. BIST is particularly useful for testing circuit blocks that are not easily accessed by the bond pads of a device-under-test (DUT). Automated DFT means (such as provided by Mentor Graphics, Wilsonville, OR) for generating BIST circuits, such as memory BIST for testing a memory block and logic BIST for testing a logic block, are well known. The results of the tests performed by the BIST circuit are either provided directly to the external I / O or indirectly to the external I / O via an interfacial scanning circuit that can be included in the design. Additional embedded embedded test circuits, such as scan chain circuits, can also be added to the design to improve the internal testability of the series of designs therein.

Additional bond pads to support on-chip test circuits, where the die already has bond pad locations around it, provided in the form of a grid or lead-on-center for device functionality. To the desired bond pad alignment results in substantially increasing the size of the die. In response to this, the price of the die tends to rise. In general, larger dies tend to result in more defects, resulting in higher manufacturing costs. In addition, on-chip test circuits can result in a significant increase in test time since many clock cycles are required to load test input data and subsequent output test results from several available bond pads. . On-chip test circuits also do not allow direct external access to internal circuit nodes. Test input data and test results must pass through the SCAN circuit or the BIST circuit before being monitored. This introduces additional circuitry that can hide defects in the circuit to be tested or introduce new defects due to SCAN or BIST circuits.

In addition, many designs are limited in I / O because only a limited number of leads (eg bond wires) may be accommodated within a given packaging. In addition, the same lead positions described above should be used to test the die's I / O functionality. It would also be advantageous if the access point could be deployed with a high degree of positional freedom. The small size, large quantity and arbitrary or optional positioning of the access point will also be advantageous.

For embedded test circuits, the design methodology of one integrated circuit initially designs the integrated circuit using software design means, simulates the overall functionality of the integrated circuit or individual circuits within the design, and allows individual circuits or Generating an embedded test circuit for testing the circuit block, and generating a test vector for functionally testing the device by the ATE.

The amount of embedded test circuitry to add to a particular design has the advantage of increased fault range and potentially reduced test time (as compared to ATE for example), resulting in increased die size and manufacturing defects leading to higher manufacturing costs of the final product. It is typically required to balance the shortcomings of increased likelihood. As one extreme measure, the design may include sophisticated embedded test circuits that test all circuit nodes of all internal circuits, but such designs can be costly because the die size will essentially be a function of the test circuit size. . As another extreme measure, the design may not include embedded test circuitry and may only rely on the test vectors supplied by the ATE to test the design's functionality at wafer level or in packaged form, but this is a fault. Reduced range, lower product quality, and expensive ATE and increased test time can lead to higher manufacturing costs. One way to minimize the cost of using expensive ATE is described in US Pat. No. 5, 497, 079. This patent relates to compressing the general functionality of ATE into one generic functional test chip that can test another semiconductor chip under the control of a host computer. The test chip may be placed on a probe card or may be placed in electrical contact with the chip to be tested via a motherboard. Another approach is described in US patent application Ser. No. 08 / 784,862, filed Jan. 15, 1997, wherein wafer level testing of semiconductor chips is performed by a test chip having a general purpose test circuit.

In both extremes, a typical integrated circuit design strikes a balance between the amount of embedded circuitry and the tests to be executed by the ATE. Embedded circuits are typically limited to about 5-15% of the total die area of the design, and test vectors are generated for the ATE to test the full functionality of the design. However, this balance still requires the use of expensive ATE, but results in less than adequate fault range.

Accordingly, it is an object of the present invention to have a design and test methodology that breaks the direct correlation between fault coverage or testability and test cost or manufacturing cost of the design.

One embodiment of the present invention relates to a test apparatus for testing a product circuit of a product die. In one embodiment, the test apparatus includes a test die and an interconnect substrate for electrically coupling the test die to a host controller in communication with the test die. The test die may be designed according to a design methodology that includes designing a test circuit and a product circuit simultaneously into one integrated design. The test circuit can be designed to provide a high fault range for the corresponding product circuit, regardless of the amount of silicon area the test circuit requires. The integrated design is then divided into test dies and product dies according to the design methodology. The test die includes a test circuit and the product die includes a product circuit. The product die and test die can then be fabricated on separate semiconductor wafers. By dividing the product circuit and the test circuit into separate dies, the embedded test circuit can be erased or minimized on the product die. This helps to reduce the size of the product die and also to reduce the manufacturing cost of the product die while maintaining a high level of test coverage of the product circuit within the product die. Test dies can be used to test multiple product dies on one or more wafers.

Other objects, features and advantages of the present invention will become apparent from the accompanying drawings and the following detailed description.

The detailed description of the invention is described below with reference to a number of specific details in order to fully understand the invention. However, one of ordinary skill in the art may practice the present invention without specific details. In some instances, well-known methods, processes, and components will not be described in order to avoid obscuring the present invention.

1 illustrates one embodiment of a design methodology 100 for designing a product die and a corresponding test die that includes test circuits for providing or monitoring signals from one or more circuits on the product die. will be. 2-4 illustrate product dies and test dies produced by design methodology 100.

As used herein, "product die" and "product device" refer to a single entity of a semiconductor wafer or an integrated circuit formed on an insulating substrate or other suitable substrate. The term is also referred to as device under test (DUT). The term "product circuit" relates to a circuit of a product die, which may consist of active or passive components including integrated semiconductor circuits, integrated microelectromechanical structures or systems (MEMS), or other suitable circuit elements. Additionally, "test die" and "test device" refer to an integrated circuit formed on a semiconductor wafer or an insulating substrate or other suitable substrate. The test die includes circuitry for providing a test signal to or monitoring the signal from the product die. The test die may also be composed of active or passive components including integrated semiconductor circuits, integrated MEMS, or other suitable circuit elements for testing or monitoring product dies. Test dies and product dies are land grid array packages (eg ball grid array (BGA) packages), pin grid array (PGA) packages, control collapsing chip connections (C4) packages, flip-chip packages, and any other surface mount package. The package may later be packaged into any package known in the art, including dual in-line packages (DIPs) and the like.

In step 102, the circuitry for the product die and the test die is designed into an integrated design 200. The design can be implemented in a conventional computer aided design (CAD) using conventional software means to design the product circuits 202, 204, 206 and test circuits 202A, 204A, 206A, for example in VHDL or Verilog HDL format. Can be. The test circuits 202A, 204A, 206A, sometimes referred to collectively as "test benches", can be designed as powerfully as desired. That is, the test circuits 202A, 204A, 206A may be designed to include as many test functions as desired to test each corresponding product circuit 202, 204, 206. The test circuit can be designed to provide a 100% fault range for the corresponding product circuit, or can be designed for a predetermined fault range. Compared to conventional design-for-test (DFT) design methodology, the test circuits 202A, 204A, 206A can be designed regardless of the amount of silicon die area for mounting the test circuit. In one embodiment, the product circuit and the test circuit can each be designed such that the resulting product die and the test die are approximately the same size. In other embodiments, the product die and the test die may have different sizes.

In step 104 the product circuit and the test circuit are each divided into separate product dies and one or more test dies. By dividing the test circuit into separate test dies, the test circuit on the product die can be minimized or eliminated. This can reduce the size of the product die, thereby increasing the testability of the product die, reducing the likelihood of manufacturing defects and generally reducing the manufacturing cost. An external test circuit that supplies a test stimulus can provide an increased number of tests without affecting the size of the product die 300. Since there is no BIST circuitry in the test input or output signal path, there is no on-chip test circuitry that hides the defects or induces other defects, thereby increasing the probability of fault location determination more accurately. Additionally, the speed parameters and timing of signals input and output to circuit blocks or circuit nodes can be measured and monitored more accurately because they do not induce delays generated by intermediate on-chip test circuits.

The product die design is taped out at step 106 and the test die design is taped out at step 108. The resulting product die 300 is then fabricated on a semiconductor wafer (not shown) along with many other identical product dies. Product die 300 includes product circuits 302, 304, 306, which can be any digital, analog, or other circuit, corresponding to product circuits 202, 204, 206, respectively.

The resulting test die 400 is manufactured to include test circuits 402, 404, 406. The test circuits 402, 404, 406 can be any digital, analog, or other test or monitoring circuits, corresponding to the test circuits 202A, 204A, 206A, respectively, from the product circuits 302, 304, 306. Test or monitor the signal separately. By way of example, each test circuit may be a functional circuit (eg, a test pattern generator, sequencer, digital signal processing device, formatter, analog-to-digital converter, digital-to-analog converter, Failure analysis circuits, etc.), and may also include circuits for testing AC parameters (eg internal signal timing, circuit speed, etc.) and DC parameters (eg voltage and current levels, power dissipation, etc.). Can be.

Each test circuit is designed to withstand a particular test of a corresponding product circuit, one embodiment of an exemplary test circuit 500 is shown in FIG. The test circuit 500 includes control logic 502 that controls the overall operation of the test circuit 500. Control logic 502 is an example sequencer. The pattern generator 504, analysis logic 506, one or more parameter measurement units (PMUs, 510), one or more digital power supplies (DPSs, 512) and clock logic 514 may be coupled to the control logic 502. Work in combination. The pattern generator 504 generates one or more test patterns in communication with the product circuits at the product die 300 via input / output (I / O) circuits 508. The pattern generator 504 may include a memory for storing the pattern. The analysis logic 506 analyzes the signal received from the product circuit of the product die 300 via the I / O circuit 508. The analysis logic 506 may include comparison logic to compare the expected result with that received from the I / O circuit 508. The PMU 510 measures the voltage and current levels of the signal received by the I / O circuit 508. The PMU 510 measures leakage current, source current and voltage, sink current and voltage, power dissipation, and the like, for example. DPS 512 provides one or more power supply voltages to the product circuit under test. In another embodiment, the power may be provided from a source other than a test die. Clock logic 514 may be included to provide a clock signal to the product circuit under test. The clock signal is not needed for the asynchronous signal. Test circuit 500 illustrates one embodiment of a test circuit, such as test circuits 402, 404, 406. However, other embodiments can also be used. All circuit blocks shown in FIG. 5 may be included in each test circuit 402, 404, 406, or one or more circuit blocks of any of the circuit blocks shown in FIG. 5 may be multiple test circuits 402, 404. , 406.

1-4, the segmentation step 104 of first determining a logic interconnection point between each product circuit and the corresponding test circuit, and then preparing a logical and physical description of each product die and the test die. Is run on the CAD DFT software. The interconnection points result in specific contact points or pads (test pads) 310, 410. The pad 310 provides a test signal to or provides an output signal from the product circuits 302, 304, 306. As will be described in detail below, the pad 310 is in electrical contact with the pad 410 of the test die 400 by contact structures (eg spring contact elements, probe card probes, etc.) to test circuits 402, 404, 406. ). Pad 410 may also be used to communicate with bond pad 312.

As shown in Figures 3 and 4, the pads 310 and 410 may be physically disposed around a particular circuit under test, or may be placed over the circuit to provide more direct access to a particular circuit node. . In general, pads 310 and 410 may be placed anywhere on each product die and test die that includes an area of product die 300 surrounded by bond pads 312 as shown in FIG. The pads 310, 410 may also be placed in the same predetermined alignment of the bond pads or may be disposed outside of the area surrounded by the bond pads. Bond pads 312 are conventional input, output, or I / O pads that receive a probe tip or a bonding wire or solder ball during wafer sorting. Bond pads 312 are commonly used to operate product die 300 as a whole. Similarly, test die 400 may use bond pad 412 to test the entire functionality of test die 400 (eg, during wafer sorting), or to bond the test die to pins of a semiconductor package. Include.

The size of the product die 300 does not increase with respect to the specified size and number of the pads 310 when the pads 310 are disposed within the area surrounded by the bond pads 312. Additionally, by moving the test circuit to a separate test die, the bond pads already used to communicate with the internal test circuit can be omitted. This may also reduce the size of the product die 300. As another example, the size of the product die 300 may be increased by the addition of the pad 310. In one embodiment, the pad 310 may be smaller than the bond pad 312.

In another embodiment, segmentation step 104 determines that no additional interconnect points are needed to test the product die 300. As an example the dividing step 104 may be used by the bond pad 312 to test the overall functionality of the product circuits 302, 304, 306, and then in the use of the test die 400. 406, it may be determined that it may be reassigned for use (i.e. having dual functionality). In this embodiment, the number of specific contact pads may be zero, or may be a number less than that required in the above embodiments.

After the segmentation step 104, some BIST circuitry, such as the BIST 308, may be maintained at the product die 308. By way of example, the BIST circuit may be advantageously maintained at the product die 300 to test a high speed circuit that may be overloaded by the addition of the pad 310 or may be interfaced with the test die 400. It may be advantageously maintained when there is insufficient space on the product die 300 to include 310.

In other embodiments, design methodology 100 may use existing or predetermined test circuits to create suitable product circuits. By way of example at step 102, the product circuit can be designed to be tested at a desired level of fault range by a predetermined test circuit. Steps 104 through 108 then continue the same. This embodiment is particularly suitable when, for example, a product circuit in a product die can be expected as in a memory circuit. Test circuits for testing such highly predictable structures are well known and can be tested well (ie, generating march patterns, galloping column and row patterns, etc.), and thus existing tests. It can be used while only the product circuit needs to be adjusted to accommodate the circuit. In addition, the test circuit is already formed on an existing test die, and the segmentation step 104 may be defined by (eg, adjusting the product circuit appropriately or adding an interconnection point between the test circuit and the product circuit). You can decide how to lay out the product circuit to maintain the test circuit.

FIG. 6 illustrates another embodiment of a design methodology 600 for designing the product die 300 of FIG. 3 and one or more test dies 400 of FIG.

In step 602 product design data is generated for product circuits 202, 204, and 206, and in step 603 test design data is generated for test circuits 202A, 204A, and 206A. Design data is generated by CAD software design means in response to input from a circuit designer around the circuit. Design data can reside on a computer in VHDL or Verilog HDL format. Test design data may be automatically generated by the CAD DFT software means with or without input from the circuit designer. As discussed above in connection with the design methodology 100, the test design data can be as powerful as the circuit designer desires for the test circuit generated therefrom.

In step 604, the register-transfer-level (RTL) technology of the integrated design, including both product data and design data, is generated and demonstrated by the CAD software. In step 606, logic integration and demonstration of a uniform RTL technique is generated. At this point in the process, the software technology of the integrated product and test circuits is completed.

The test software means 608 has an integrated design output from step 606, and the data for taping out and subsequent fabrication of the product die 300, one or more separate test dies 400, and interconnect technology. To produce. In step 610, software means 608 divides the integrated design into separate product die and test die technologies, and creates a physical layout (eg in silicon). This step is performed while considering physical constraints 612 and user selection 614. Constraints 612 and 614 may be entered into the software means 608 before executing the design methodology 600, or may prompt the user to enter the software means 608 during runtime.

Physical constraints 612 may include, for example, the size of the resulting product die and test die, the number of bond pads or specific contact pads on each die, the size of bond pads or specific contact pads on each die, process constraints or process techniques, and the like. Include. Physical constraints 612 are used by software means 608 to determine the circuit and how many circuits will be split between the product die and the test die. In one example the maximum die size for the product die 300 may be programmed as a parameter for the software means 608 upon execution of step 610. If dividing the product circuit and the test circuit produces too many specific contact pads on the product die 300 such that the size of the product die exceeds the desired maximum die size, the software means 608 may add a small amount of the product circuit to the product circuit. Reshape the test circuit to request an interconnect point, replace part of the test circuit on the test die with a BIST circuit on the product die (ie, such as BIST 308 in FIG. 3), or replace part of the test circuit. You can remove them all. As another example, design constraints can prevent certain contact pads from being created on the product die or the test die. The software means 608 applies test circuitry and product circuitry so that the product die has a dual purpose bond pad, that is, firstly testing the entire functionality of the product die, and secondly testing individual product circuits using the test circuit. It can be divided appropriately. Appropriate circuitry to enable or program this dual functionality can be included in the product die or test die.

As another example, software means 608 may determine that the required test circuitry is best executed in another process technology (eg BiCMOS v. CMOS) to generate multiple test dies from other process technology to support the test circuit. . As another example, the software means 608 may be configured to perform some of the necessary test circuitry best on a test die with analog circuitry, and the remainder of the necessary test circuitry is best performed on a separate test die with digital circuitry. You can decide.

Another constraint that may be considered by the software means 608 is whether one or more test dies are scheduled. As described above by way of example, the product circuit can be designed to be tested at a desired level of fault range by a predetermined test circuit. Certain test circuits are particularly useful when, for example, a product circuit in a product die is predictable, such as in a memory circuit. In this example, the software means 608 determines how to divide the circuitry in order to properly adjust the product circuitry or to maintain a given test circuitry while properly adding interconnection points between the test circuitry and the product circuitry. do. In addition, the test circuit may already be formed on an existing test die, and the software means 608 may be configured by (e.g., adjusting the product circuit appropriately or by adding an interconnection point between the test circuit and the product circuit). Determine how to lay out the product circuit to maintain the desired test circuit.

Software means 608 may also execute step 608 while considering other predefined constraints, such as user selection 614. The user or circuit designer selection 614 includes, for example, the cost of providing a connection between the product die and the test die, the cost of the product die, the cost of the test die, timing priority, test accuracy and fault range, and the test die. The cost of the interconnect between the external host device and the test die that can control or communicate with it. The term "coast" is used herein in a broad sense and includes manufacturability and ease of use.

The cost of providing the interconnect between the product die and the test die is related to the cost associated with the formation of a particular contact pad, the cost of forming the interconnect elements to communicate between the product die and the test die, and the ease of performing wafer sorting and the product die and the test. It also includes the ease associated with testing with a specific number of specific contact pads provided on the die. If the cost of providing the interconnect is low, the circuit designer may instruct the software means 608 to split the circuit regardless of the number of interconnections required between the product die and the test die. However, if the cost of providing the interconnect is high, the circuit designer may instruct the software means 608 to divide the circuit to minimize or limit the number of interconnects.

The financial cost of the resulting product die and test die may also be used by software means 608 to determine how to divide the product circuit and the test circuit. For example, if there is enough space on the product die to include a specific contact pad for testing the product circuit without increasing the size of the product die after splitting, the financial cost of the product die adds the specific contact pad and the test die It does not increase by including a corresponding test circuit. In other words, in this example, the software means 608 can split the product circuit and the test circuit and generate all required interconnection points. However, after splitting, there is no space for adding all desired specific contact pads to the product die (or test die) initially without increasing the die size and thus increasing the financial cost of the product die (or test die). In insufficient cases, software means 608 may reduce the number of interconnects and pads to keep the financial cost of either the product die or the test die below a given user selection.

Timing priority and test accuracy may also be used by software means 608 to determine how to divide the product die and the test die. For example, high speed product circuits can be unnecessarily loaded and delayed by the addition of specific contact pads. In other words, software means 608 may embed part of a test circuit, such as a BIST circuit, into a product die to test the circuit to avoid timing and test accuracy delays.

The fault range of the test of the product circuit can also be used by the software means 608 to determine how to divide the product die and the test die. For example, if a 100% or higher grade fault range is desired by the circuit designer, the test circuit generated in steps 602-606 may be a test die and the required number of interconnect points generated on both the product die and the test die, or Can be separated into specific contacts. However, if a low grade fault range is desired by the circuit designer, some of the test circuit generated in steps 602-606 is not split into test dies. The circuit designer can enter the product circuits as more important to test than others, or input the desired level of test coverage that would be desirable on a product circuit to circuit basis.

The cost of the interconnect net between the test die and the external device can also be used by the software means 608 to determine how to divide the product die and the test die. The external device is, for example, a host controller or other test die. The test die needs to communicate with a host controller or other device to report the test results of the product die. As another embodiment, the software means 608 may generate multiple test dies each having a specific test circuit for one or more product dies. The number of interconnection points, such as bond pad 412 or specific contact pad 410 of FIG. 4 required to support communication between such devices, may be limited (or not limited) by user input.

After dividing the product circuit and the test circuit into product die and test die technology, logic and timing demonstration of the product die is performed in step 616 and logic and timing demonstration of the test die is performed in step 618. Logic and timing demonstration of the combined system of product die and test die working together is performed in step 620. In response to steps 616-620, software means 608 determines whether all physical constraints 612 and user selection 614 have been satisfied at step 622. If the constraints 612 and 614 are satisfied, the product die is taped out at step 624, the test die is taped out at step 628, and a description of the interconnection points between the dies is created. If the constraints 612 and 614 are not satisfied, the software means 608 repeats the process. In other words, the software means 608 returns to step 610 to repartition the product circuit and the test circuit to satisfy the constraints 612 and 614. This process continues until all constraints are satisfied. If the software means 608 determines that all constraints cannot be satisfied, the software means 608 stops and notifies the designer. The designer can then change the design and constraints.

One embodiment of the dividing step 610 is shown in step 710 of FIG. Segmentation step 710 uses conventional weighting techniques to determine the product die and test die layout. By way of example, a weighting function is formed at step 702 in response to a complete system logic description from step 606, physical constraints 612, and user selection 614. Weighting functions describe the relative trade-offs and constraints for a given partition. Many other analytical techniques can be used to find a proper solution to the segmentation problem described by the weighting function. One technique is "simulation annealing," which simulates the physical process of annealing by mathematically elevating the design means to a high temperature system. This allows the system to find solutions quickly with minimal energy or minimum cost. When applied to step 704, the simulation annealing is effected by varying the number of specific contact pads, the amount of test circuit, or any physical constraints or user choice to determine the optimal division of the product circuit and test circuit between the product die and the test die. It can be used to find a suitable solution.

Segmentation of the design at step 704 results in circuit adjustment in the test circuit, product circuit or BIST circuit on the product die. Adjustments include adding, removing or changing test circuits or BIST sessions to properly test the product circuit. Coordination also includes adding additional test circuits to the test nodes introduced by the partition itself. This step is completed automatically or by interaction with the circuit designer.

Once the partition is created in step 704, the solution is tested, evaluated or simulated in step 706 to determine if a proper solution has been created and all constraints 612, 614 have been satisfied. If the weighting function is correctly defined, the tested solution will satisfy all constraints 612 and 614 and will produce a product die with or without BIST circuits, test dies, and interconnect technologies. If the user does not satisfy the solution, the constraint can be adjusted to create a new weighting function and create a new split of circuit, specific contact pads, die size, etc. between the product die and the test die.

FIG. 8 illustrates a variation of the design methodology 600 (or design methodology 100 of FIG. 1) of FIG. 6. In some applications, the resulting test die generated by design methodology 600 or 100 may communicate with a tester or host controller, such as an ATE, general purpose computer or other control logic or system. The tester, for example, starts and stops a test executed by a test die, provides power to the test die, displays the test sequence in the test circuit of the test die, displays the test sequence between multiple test dies, and tests You can list and report the test results received from the die, and so on. The tester may also be used to test the product die as a whole, for example, during wafer sorting where the test die is used to test individual product circuits or nodes, or where a separate probe card controlled by the tester is used to test the product die as a whole. Can be used.

In the design methodology 800, the test design data supplied to the RTL analysis and demonstration step 604 is determined in steps 804-810. In step 808, the test is split between the tester and the test die in response to a description of the test requirements 804 and tester's ability 806 to test the product circuit. If the test is to be executed by a test die (as determined in step 810), the test is provided to step 604 with product circuit design data as part of the test design data. However, if the test is to be run by the tester, the test is stored in the test file 812 for the tester.

The design methodology described in the above embodiments is embodied in software conventions that can be implemented on a general purpose computer or workstation, or on-demand CAD system. One embodiment of a general purpose computer system 900 in which software conventions are stored and executed is shown in FIG. Many other computer system embodiments may also be used.

Computer system 900 is a computer having main memory 902, static memory 904, mass storage device 906, and processor 912 in communication with one or more internal buses 910. 928. Main memory 902 may be, for example, dynamic random access memory (DRAM) or other volatile or nonvolatile memory that stores program code, system code, or software conventions of one or more of various design methodology embodiments. Static memory 904 may be cache memory or used to store program code, system code, or software conventions of one or more of various design methodology embodiments. The mass storage device 906 can be any mass storage device such as a CDROM, floppy disk, hard disk, laser disk, flash memory card, magnetic storage device, or the like. The mass storage device 906 may also store program code, system code or software conventions of one or more of various design methodology embodiments. Processor 912 may be any control logic that integrates data flow in computer system 928. The processor 912 may be, for example, a microprocessor or one or more other digital signal processing devices.

Computer 928 may communicate with one or more peripheral devices 914 on booth 926. The peripheral device includes a display 914 for displaying graphical representations of the logic and circuitry of the product die and test die generated by the design methodology or software conventions of the design methodology, and a keyboard 916 for inputting data into the computer 928. And a cursor control device 918 such as a mouse, track ball or stylus, a signal generation device 920 for providing any other input signal to the computer 928, and a hard copy device such as a printer ( 922 and an acoustic recording and playback device 924.

Specific contact pads

3 and 4, the specific contact or specific contact pad 310 provides test input data to the product circuits 302, 304, and 306, respectively, without testing the functionality of the overall product circuit 300, and There is provided a means for the test circuits 402, 404, 406 to monitor the signals therefrom. Although the rest of this portion is described with reference to the specific contact pad 310 and the bond pad 312, the same technique can be applied to each of the specific contact pad 410 and the bond pad 412 in the same manner.

The specific contact pads 310 also provide a means for testing the circuits when the internal circuits 302-306 are otherwise individually testable or accessible via the bond pads 312. In one example, product circuit 302 may be embedded memory that is not directly accessible through bond pad 312. The address and input data signals may be provided on a plurality of specific contact pads 310 to provide a test pattern to embedded memory, and another group of specific contact pads 310 may receive data reads from the memory. External circuitry that provides test patterns for the embedded memory can provide any number of patterns to increase the fault range.

In other embodiments, product circuit 302 may be programmable circuitry, such as nonvolatile memory or programmable logic. Data can be programmed into internal circuits via specific contact pads 330. By way of example, BIOS information, program code and system software may be programmed or updated in programmable circuit 302 after fabrication of integrated circuit 300.

As shown in the product die 300, the specific contact pad 310 is configured to monitor the response of the internal circuit 306 to test the stimulus provided by the BIST 308 (or on-chip). Test circuit). This may be done without adding additional bond pads 312 or without using existing bond pads 312 to communicate with the BIST 308.

As shown in FIG. 3, a particular contact pad 310 is disposed in an area surrounded by a peripheral bond pad 312. Since the specific contact pad 310 is not disposed at a predetermined peripheral alignment of the bond pad 312, the size of the product die 300 is not increased by the addition of the specific contact pad 310. As another example, the number and location of specific contact pads 310 may increase the size of the product die 300.

The particular contact pad 310 may also be inserted between the bond pads 312, or may be located outside the area surrounded by the bond pads 312. In one embodiment where a particular contact pad 310 is inserted between the bond pads 312, it is beneficial to make the specific contact pad 310 smaller than the bond pad 312 so as not to increase the size of the product die 300. can do.

The particular contact pad 310 can be any size, including a size smaller than the bond pad 312. If a particular contact pad 310 is smaller than the bond pad 312, more specific contact pads may be placed on the product die 300 without increasing the size of the die on the area defined by the peripheral bond pad 312. Can be. A larger number of specific contact pads can increase the number or complexity of tests that can be provided to internal circuitry, thereby increasing the fault coverage and robustness of the test. In one embodiment, the bond pads 312 are about 100 μm × 100 μm (4 mil × 4 mils) and the particular contact pad is about 5 μm to 10 μm per side. In other embodiments, the specific contact pads are no greater than 5 μm per side. In another embodiment, a particular contact pad may be provided with various probe tips of different dimensions, to accommodate different spatial locations on the die (eg, within an area surrounded by bond pads 312 versus bond pads 312), To accommodate bond wires or solder balls, or to accommodate different functions of the circuit under test (i.e., the node driving the output signal requires a larger pad than the pad to provide the input signal, or vice versa). ), And can be manufactured to have different dimensions. The lower limit for the size of a particular contact pad can be limited by the accuracy of the probe to pad alignment and the size of the probe.

The particular contact pads 310 may be formed in approximately squares, rectangles, or any other geometric shape. The specific contact pads 310 may also have a different height than the bond pads 312. Certain contact pads 310 may be fabricated by conventional photolithographic processes that are typically used to form bond pads or other relatively flat conductive landings. In one embodiment, a particular contact pad may be made of one or more metal layers comprising aluminum, copper, gold or other metal or conductive material.

The specific contact pads 310 are not permanently bonded to an integrated circuit package (eg, typical plastic and ceramic chip packages), but rather the pads receive test input information (eg, address, control or data signals) or internal test nodes. Or to monitor the signal. However, the specific contact pads are large enough to accommodate the electrical contact elements (as described in detail below). If a particular contact pad 310 is not bonded to the package, the particular contact pad 310 typically requires a support circuit that is significantly smaller than that required by the bond pad 312. Typical bond pads generally include support circuitry that requires a significant amount of silicon die. Examples of support circuits include electrostatic discharge (ESD) protection structures such as resistors, capacitors, or diodes, latch-up protection circuits such as guard rings, and circuits and signal lines to be driven out of the integrated device, or There are buffers to buffer internal signals received from external signal lines, logic or voltage relay circuits, and noise reduction circuits. The specific contact pads 310 can reduce the amount of support circuitry required. Almost no buffering is required and no ESD protection is required to electrically contact the external probe with a specific contact pad and monitor the signal from it. As an example, I / O buffer 320 may be used between internal test point 324 and specific contact pad 310 as shown in FIG. The I / O buffer may be controlled by the control signal 322. I / O buffer 320 is about 10 to 100 times weaker than the bond pads needed to drive heavy loads in printed circuit board conditions. In addition, little latch-up support circuitry or noise reduction circuitry is needed. As an example, a weak pull-up resistor is needed for each particular contact pad for the noise reduction circuit. Certain contact pads generally require only 1-50% of the support circuit typically required for bond pads.

3 and 4 illustrate that particular contact pads 310 and 410 are disposed in an area surrounded by bond pads 312 and 412 located at the periphery, although the specific contact pads may also be placed within other product die or test die layouts. May be included. Figure 11 shows an integrated circuit 1100 (product die or test die) including bond pads 312 aligned in an LGA pattern for bonding to contact balls (e.g. solder or other metal interconnects) in a C4 or flip-chip arrangement. ) Is shown. It is the specific contact pad 310 that is selectively distributed within or outside the grid pattern. In this embodiment, the specific contact pad 310 may be smaller than the bond pad 312 or the contact ball to make the size of the integrated circuit 1100 larger than the minimum size required for a specified number of bond pads 312. In other embodiments, the particular contact pads 310 may be the same size as the bond pads 312.

12 shows a cross section of a particular contact pad 310 disposed between two bond pads 312. Bond pads 312 include contact balls 1204 formed therein, and are typically spaced at a minimum pitch between centers of about 10 mils or 250 μm. The minimum diameter 1208 of the contact ball 1204 is typically in the range of 1 to 3 mils, and the minimum spacing 1206 between the edges of the contact ball 1204 is typically 7 to 9 mils. The specific contact pads 310 are sized to fit between the bond pads 312 and may have a width 1210 of 9 mils or less. In other embodiments, the particular contact pad 310 may have a width of about 1-5 mils. In another embodiment, the specific contact pad 310 may have a width of 1 mils or less. The particular contact pad 310 may be formed in an approximately rectangular, rectangular or any other geometric shape. Certain contact pads 310 may also have a different height than bond pads 312.

11 and 12 may be LGA packages such as BGA packages, PGA packages, C4 packages or flip-chip packages with pin or contact balls for interfacing with sockets or printed circuit boards (PCBs). The specific contact pad 310 may be an additional pin or pad capable of receiving a test signal or providing a test output signal or other signal to a probe, socket or printed circuit board.

12 also shows a particular contact pad 310 disposed between two bond pads 312 arranged in a peripheral alignment (as shown in FIG. 3). The contact balls 1204 need not be formed on the bond pads 312.

FIG. 13 illustrates an integrated circuit 1300 (product die or test die) including bond pads 312 arranged as rows (or columns) in a lead-on-center pattern. Optionally distributed within or outside the lead-on-center pattern can be used to provide test signals to or monitor signals from the internal circuits 1302 and 1304 of the integrated circuit 1300, as in the embodiments described above. Specific contact pad 310.

3 and 4 show that a product circuit block or internal circuit node can be tested or monitored by a specific contact pad. 14 shows that a sequential product circuit 1402, 1404, 1406 can also be tested by a particular contact pad with or without bond pads. In this embodiment, test input data is provided to a specific contact pad 1412 and embedded memory 1402 from a test circuit on a test die. In another embodiment, input data may be provided from a bond pad. The test data may include an address, a control signal (eg read, scribe, etc.) or a test pattern. Assuming the test data is an address of a location in memory 1402, the data stored at the accessed address can be provided to I / O interface 1404 and monitored by a particular contact pad 1413. The access time (ie, address for data out) of the memory 1402 does not have additional time introduced due to circuit blocks such as the I / O interface 1404 and the I / O driver 1406, so that the specific contact pads 1412 , 1413). Conventional approaches using BIST circuits typically include additional on-chip circuitry to provide an address signal to memory 1402 as an example, whereby external circuitry can be used at one or more bond pads 1416. The results can be monitored. However, this conventional approach cannot monitor the output of the memory 1402 directly (as with certain contact pads 1413), and thus cannot directly measure the actual access time of the memory 1402.

In response to the data read from the memory 1402, the I / O interface 1404 may format the data before providing it to the I / O driver 1406. I / O interface 1404 may receive a control signal on specific contact pad 1414, or an internal circuit node within I / O interface 1404 may be monitored by specific contact pad 1414. Data output to I / O driver 1406 by I / O interface 1404 may be monitored by specific contact pads 1415. I / O driver 1406 may then drive data to bond pad 1416.

Bond pads 1416, because the specific contact pads 1413 and 1415 and bond pads 1416 can be used to monitor the output of each of the memory 1402, I / O interface 1404 and I / O driver 1406. The fault data received at) can be isolated from the circuit causing the fault. In a conventional BIST technique where an address is provided as an example in memory 1402, the source of the error data received at bond pad 1416 is unknown.

The embodiment shown in FIG. 14 includes a specific example of the accessing data in embedded memory 1402, which also applies to introducing and monitoring signals from any other series of circuit blocks.

Certain contact pads can also be used to isolate faults, as well as replace spare circuits with fault circuits. Figure 16 illustrates one embodiment of a test circuit on a test die using a specific contact pad to identify a fault circuit block and to replace a spare circuit with a fault circuit block. This embodiment reuses the example of the accessing data in the embedded memory, but can be extended to a series of circuits in which one of the circuits has a spare circuit.

16 includes a spare I / O interface 1405 that can replace defective I / O interface 1404. The output of memory 1402 is provided to both I / O interfaces 1404 and 1405. The output of the I / O interface 1404 may be monitored by the test die through the specific contact pad 1415, and the output of the spare I / O interface 1405 may be monitored by the test die through the specific contact pad 1417. Can be monitored. If the output of the I / O interface 1404 is expected to indicate that the I / O interface 1404 is operating correctly, then the multiplexer 1408 is placed by a control signal on line 1421 so that the line ( A signal on 1423 may be provided to I / O driver 1406. However, if the output of the I / O interface 1404 is not expected to indicate that the state of the I / O interface 1404 is bad, and the output of the spare I / O interface 1405 is expected, the multiplexer 1408 is expected. Is disposed by a control signal on line 1421 such that a signal on line 1425 can be provided to I / O driver 1406. The signal output by the multiplexer 1408 can be monitored via a particular contact pad 1419.

The control signal on line 1421 may be driven to an appropriate voltage level or logic state by switch 1410. In response to the TOGGLE signal, the voltage V1 or V2 will be selected in response to the monitoring of the signal at the particular contact pads 1417, 1415. The toggle signal may be controlled by the test circuit on the test die through other specific contact pads or bond pads.

FIG. 15 illustrates switch 1500 as an embodiment of switch 1410 of FIG. Other embodiments of the switch 1410 may also be used. The switch 1500 includes a PMOS transistor biased on-state by including a gate coupled to ground, a source coupled to the power supply VDD, and a drain coupled to the signal line 1421. The switch 1500 also includes a fuse element 1504 coupled between the signal line 1421 and ground. The fuse element may be a metal fuse, a resistance fuse or a memory element. If fuse 1504 is shorted in response to a toggle signal, signal line 1421 is pulled towards VDD and signal on line 1425 is output by multiplexer 1408, for example. If fuse 1504 is not shorted, signal line 1421 is pulled towards ground by fuse 1504, and the signal on line 1423 is output by multiplexer 1408, for example. Fuse 1504 may be shorted using a number of well known techniques, including the use of laser pulses or electrical current. In one embodiment, certain contact pads may be used to provide an electrical current that shorts the fuse 1504.

Figure 17 shows another embodiment in the reserve of Figure 16; In FIG. 17, groups of fuses 1702, 1704, and 1706 may be included before and after the I / O interface. If one of the I / O interfaces is found to be faulty, it can be isolated in the appropriate fuse group. As an example, if I / O interface 1404 is faulty and I / O interface 1405 is a normal function, fuse groups 1704 and 1708 will be shorted to insulate I / O interface 1404. Fuse groups 1704 and 1708 may be shorted through specific contact pads (not shown) that provide one or more signals that allow a significant amount of current to flow through fuse groups 1704 and 1708. Other means of shorting the fuses may also be used.

As discussed above in connection with FIG. 3, certain contact pads can be used with on-chip test circuits to test product circuits. 18 illustrates the use of one (or more) specific contact pads 1810 to provide a clock signal, reset signal, enable signal, or other control signal to the BIST 1802. One embodiment is shown. In response, BIST 1802 provides one or more test signals to internal circuitry 1804 or internal circuitry 1806. The results of the internal test can then be monitored at bond pad 1808 (or otherwise at a particular contact pad). As another embodiment, a particular contact pad may also be used to provide an enable signal or a clock signal to any other internal circuit.

Similarly, as shown in FIG. 19, one (or more) of the specific contact pads 1910 may be configured to convert clock signals, reset signals, enable signals, or other control signals to the shift register elements of the SCAN circuit. And may be used to provide to (1906, 1908). The SCAN circuit can be coupled between bond pads 1906 and 1908 (or alternatively one or more specific contact pads) that can receive the SCAN input data SI and provide the SCAN output data SO, respectively.

In one embodiment, one or two pads 912 and 1914 may be specific contact pads. This can provide great design flexibility in the location and use of the SCAN circuit. As an example, this allows multiple SCAN zones or circuits of varying size and complexity to be used to test various other internal circuits or blocks of circuits.

Test Methodology and Test Equipment

The test die generated by one of the design methodologies described above can be used to test or monitor the signal of the product die using various test assemblies.

20 illustrates a cross-sectional view of one embodiment of a test apparatus 2000 for performing a wafer level classification test of a product die 2011 by a test die 2010. Product die 2011 may be product die 300 of FIG. 3, and test die 2010 may be test die 400 of FIG. 4.

The test apparatus 2000 includes an interconnect and support substrate 2008, a test die 2010 and a product die 2012. Interconnect and support substrate 2008 provides electrical interconnection between test die 2010 and host 2002. Substrate 2008 also provides structural support for test die 2010. Substrate 2008 may be one or more printed circuit boards that perform electrical interconnect and support functions. Substrate 2008 may also be attached to a structure (eg, wafer prober or chuck (not shown)) that supports wafer 2012.

The host 2002 is in communication with the test die 2010 via the substrate 2008. The host 2002 may initiate and stop the test, send a signal to list the results of the test and display it to the user, or to send other test data to the test die 2010. have. Any type of host may be used including a general purpose computer, ATE or any other control logic.

The test die 2010 includes a specific contact pad 2006 and a bond pad 2004, on which spring contact elements 2020, 2018 are disposed. Product die 2011 is formed on wafer 2012, which may include other product die 2011. Wafer 2012 may be disposed on a suitable support structure, such as a vacuum chuck (not shown).

The spring contact element 2018 is formed in a given alignment to provide an electrical connection between the bond pad 2004 and the bond pad 2014 when the test die 2010 is pressed towards the product die 2012. The spring contact element 2020 provides an electrical connection between the specific contact pad 2006 and the specific contact pad 2016 when the test die 2010 is pressed towards the product die 2012. In one embodiment, the contact elements 2018 may be arranged in a grid array to contact the bond pads 2014 arranged on the die 2011 in a corresponding grid array pattern. The spring contact elements 2020 may be arranged aligned to a predetermined grid array outside of the grid array pattern, or interspersed within the grid array pattern to make electrical contact with a corresponding specific contact pad 2016 on the die 2011. have. Alternatively, the spring contact element 2018 may be arranged in a peripheral pattern to contact the bond pads 2014 arranged on the die 2011 in a corresponding peripheral pattern. The spring contact element 2020 is arranged aligned in a predetermined peripheral pattern outside of the peripheral pattern, or aligned in an area surrounded by the peripheral pattern to make electrical contact with the corresponding specific contact pad 2016 on the die 2011. Can be. As yet another embodiment, the spring contact elements 2018 can be arranged in a lead-on-center arrangement to align with the corresponding lead-on-center bond pads 2014, and the spring contact elements 2020 can be lead-on- It may be arranged inside or outside of the center arrangement and aligned with the corresponding particular contact pad 2016. As another example, the bond pads 2014 and the specific contact pads 2016 may be arranged in different alignments.

When the test die 2010 is pressed against and in contact with the product die 2011, one or more product circuits may be tested simultaneously or sequentially by the test circuit of the test die 2010. Product die 2011 may be tested as a whole. Wafer 2012 may include a number of product dies 2011, and test die 2010 may be stepped across wafer 2012 to test each product die. In another embodiment shown in FIG. 21, multiple test die 2010 may be used to test multiple product die 2011 on wafer 2012 in parallel to increase test efficiency. The test methodology of FIG. 21 may be extended such that the wafer 2009 of the test die simultaneously tests the wafer 2012 of the corresponding product die.

20 illustrates that test die 2010 communicates with both bond pad 2014 and specific contact pad 2016, including contact elements 2018 and 2020, respectively, but multiple independent test dies may be connected to a specific contact pad ( 2016) or bond pads 2014 may be used for probing. By way of example, a first test die 2010 comprising a bond pad 2018 with a spring contact element 2018 may be initially used to contact the bond pad 2014 of the product die 2011. The first test die may functionally test the product die 2011 as a whole. The second test die 2010 may then be used as comprising a specific contact pad 2006 and a spring contact element 2020. The second test die may be used to test one or more product circuits of the product die 2011 simultaneously or sequentially. As another embodiment, multiple test dies may be used having a mixture of spring contact elements 2018 and 2020. The number and configuration of test dies is determined by one or more of the design methodologies described above.

As another example, spring contact elements 2018 and 2020 may be attached to bond pads 2014 and die contact pads 2016 on die 2011, as shown in FIG. As another example, some of the spring contact elements 2018 or 2020 may be attached to the test die 2010 and some may be attached to the die 2011.

Bond pads 2014 and specific contact pads 2016 may also have different heights. As an example, as shown in FIG. 23, the bond pads 2014 may be smaller than the particular contact pads 2016 (or vice versa). In this embodiment, the probes 2018 and 2020 may extend to other depths (or to other heights). That is, the probe 2020 may extend lower than the probe 2018 to contact the specific contact pad 2016. In another embodiment, the bond pads 2004 and the specific contact pads 2006 of the test die 2010 may be at different heights.

24 is a side cross-sectional view of a spring contact element 2400 which is one embodiment of the spring contact elements 2018, 2020 of FIGS. 20-23. The spring contact element 2400 includes a base 2402, an extended elastic member 2404, an extended contact tip structure 2406 and a pyramidal contact feature 2408. Many other embodiments of spring contact elements are herein incorporated by reference, and are commonly owned US patent application Ser. No. 08/526, 246 filed September 21, 1995, US patent application filed November 15, 1995. 08/558, 332, US Patent Application No. 08/789, 147, filed Jan. 24, 1997, US Patent Application No. 08/819, 464, filed March 17, 1997, and November 1998. And US Pat. Appl. No. 09/189, 761 to dated application.

Structure 2406 may be any shape. 25 is an embodiment of a structure that includes a relatively wide end for contacting member 2404 and a relatively narrow end for supporting pyramidal contact feature 2408.

FIG. 26 illustrates one embodiment of a pyramidal contact feature 2408. Other shapes can also be used. Feature 2408 is advantageously smaller than the tungsten probe tip typical of a cantilevered probe of flip-chip probe card technology and the contact ball of C4. The tip of pyramidal contact feature 2408 may have a length 2414 and a width 2416 of about 1-5 μm. In other embodiments, the length 2414 and the width 2416 may be numerical values of less than or equal to μm. The small size of the contact 2408 allows certain contact pads to be smaller than the bond pads. As noted above, if a particular contact pad is smaller than the bond pad, the particular contact pad can be added to an integrated circuit such as product circuit 2011 without increasing die size. Additionally, certain small contact pads can be placed between the bond pads of the solder balls.

43A and 43B show another embodiment of the spring contact element described in US Patent Application Nos. 09/189, 761 in a side view and a perspective view, respectively. The spring contact element 4300 is coupled to the substrate 4306 and includes an extended elastic member 4304, a tip structure 4308, and a blade 4302. Blade 4302 is used to make electrical contact to bond pads or specific contact pads. Blade 4302 is beneficial for use to provide good electrical connection to contacted bonds or specific contact pads because blade 4302 can cut, slice, or penetrate the top surface of the pad. Blade 4302 may be disposed substantially horizontally on tip structure 43A, or any other orientation is possible.

44A and 44B are perspective and cross-sectional views of another embodiment using a blade on the tip structure of a spring contact element. Blade 4400 is a blade having several heights disposed on tip structure 4406. Blade 4400 has a main blade 4402 facing the front edge of tip structure 4406 and a rear blade 4404 facing rear of tip structure 4406.

45 is a perspective view of another blade structure formed on tip structure 4500. The blade of FIG. 45 is formed to have a substantially rectangular base 4502 and a substantially triangular shape 4504.

FIG. 27 illustrates a test apparatus 2700, which is another embodiment for conducting a wafer level classification test of a product die 2011. In this embodiment, two (or more) test dies 2010 may be used to test different product circuits of a single product die 2011 simultaneously or sequentially. When multiple test dies are used to test a single product die, the physical mapping or location of bond pads 2014 and specific contact pads 2016 may be used to test die tests or to monitor product circuitry of product dies 2011. Become the main determinant. Each test die must be in contact with all the contacts required to conduct a test by the test die.

Multiple test dies of the apparatus 2700 may be generated by the design methodology described above. As an example, the test circuits required to test the product circuits of the product die 2011 are best run in different process technologies (eg BiCMOS vs. CMOS), thus supporting the test circuits from different process technologies. It can be determined (by the software means 608 of FIG. 6, for example) that it can generate different test dies. As another example, the software means 608 may determine that some of the required test circuitry is best performed on the analog circuitry on the first test die, and other test circuitry is best performed on the digital circuitry on the second test die. .

28 shows another test apparatus 2800 in which two (or more) product dies 2011 are tested by a single test die 2010. In this embodiment, a single test die can include tests that can be run (both simultaneously or non-simultaneously) on both product dies. As one embodiment, test die 2010 may include one test circuit having multiple interconnect points or pads for providing a duplicate signal to multiple product die 2011. As another example, test die 2010 may include multiple replication test circuits for contacting multiple product dies. Alternatively, each product die 2011 may include a unique circuit that can be tested by a single test die 2010.

The test apparatus 2900 of FIG. 29 shows one embodiment of a stair approach to testing multiple product die 2011 with multiple test dies 2010. As shown in FIG. 29, each product die 2010 may be tested by a separate test die 2010. The test die 2902 is in communication with a host 2002 and is a second level of stairs supporting or controlling multiple test dies 2010. By way of example, test die 2902 may be a common resource that includes circuitry typically used by all test dies 2010. As an example it may be beneficial to move the common circuit to the test die 2902 to reduce the size of the test die 2010. By way of example, an automated pattern generator (APG) circuit or other test vector generation or storage circuitry may be moved to the test die 2902 and may be shared by each of the multiple test dies 2011. The test die 2010 may then simply include a formatter, driver, and timing generator for the pattern provided by the test die 2902. The APG circuit does not need to be duplicated in each of the test dies 2010 next.

The test die 2902 can simultaneously support all the test dies 2010 by simultaneously providing a common test pattern to each of the test dies 2010, or the test die 2902 can perform an adjustment function and then test or The pattern can optionally be provided (eg, continuously) to one or more test dies 2011.

The design methodology described above can determine when it is beneficial to divide the test circuit into one or more test dies. By way of example, where a relatively large circuit (eg APG) can be shared by one or more test dies, the circuit can move to the common test die 2902 to reduce the die size of each test die 2010.

30 also shows a test apparatus 3000 that includes a common test die 2902. In this embodiment, each test die 2010 is provided to a corresponding product die 2011 and provides a different test to each product die. However, test die 2902 can be used to provide a common test or test pattern to test die 3002 simultaneously or in coordinated form for use by each of product die 2011.

The embodiments shown in FIGS. 21-28 directly electrically connect (via contact structures 2018, 2020) one or more test dies and one or more product dies designed according to the design methodology described above. FIG. 31 shows a test apparatus 3100 for conducting a wafer level classification test of a product die 3111 by a test die 3104. As shown in FIG. The test die 3104 is indirectly electrically connected to the product die 3110 through the contactor 3108 and the interconnect substrate 3106. Contactor 3108 is a form factor, inc., Livermore, CA. And any type of probe card, such as an epoxy ring probe card, membrane probe card, or any type of probe card device such as provided by Wentworth Laboratories, Brookfield, Connecticut.

Test die 3104 may be one or more test die, such as test die 400 of FIG. 4 generated by the design methodology described above. Product die 3111 may also be one or more product die, such as product die 300 of FIG. 3 generated by the design methodology described above. Product die 3111 is formed on wafer 3110, which may include other product die 3111. Wafer 3110 may be disposed on a suitable support structure, such as a vacuum chuck (not shown). Product die 3111 also includes bond pads 3114 and specific contact pads 3116 to receive contact elements 3112. The contact element 3112 may comprise a cantilever probe needle, a contact ball of a membrane probe card, the spring contact element described above, or any other electrical contact element.

Interconnect substrate 3106 provides electrical interconnection between test die 3104 and contactor 3108. As shown in FIG. 31, a test die 3104 may be disposed on the top surface 3120 of the substrate 3106. Alternatively, the test die 3104 may be disposed on the bottom surface 3122 of the substrate 3106. As another embodiment, the test die 3104 may be placed directly on the contactor 3108.

The interconnect substrate 3106 may include sufficient routing, and the contactor 3108 may provide a sufficient number of contact elements 3112 to electrically connect the test die 3104 to one or more product die 3111. It may include. As an example an entire wafer of a product die may be tested simultaneously by one or more test dies.

In one embodiment, the test die 3106 may have specific contact pads and bond pads mounted on the substrate 3104 and bonded out to the substrate 3106, or may first be suitable semiconductor packages (eg surface mount, DIP). Or LGA, C4 or flip-chip package) and then electrically connected to the substrate 3106.

Substrate 3106 also provides structural support for test die 3104 and contactor 3108. Substrate 3106 may be one or more printed circuit boards that perform electrical interconnect and support functions, and may be attached to a structure (eg, wafer prober or chuck (not shown)) that supports wafer 3110. Can be.

Host 3102 is in communication with test die 3104. The host 3102 may send a signal to start and stop the test, to list the results of the test and display it to the user, or to send other test data to the test die 3104. Any type of host may be used that includes a personal computer, an ATE, or any other control logic.

32 illustrates a test device 3200, which is one embodiment of a test device 3100 in which a contactor 3108 includes a probe card 3120. The test device 3200 includes a test head 3204 and a probe card device 3213. The probe card device 3213 includes an interconnect substrate 3106 (eg a test rod substrate), a test die 3104 and a probe card 3210. The test die 3104 may be disposed on the bottom surface of the substrate 3106 or on the probe card 3210 itself.

The probe card 3210 is a cantilevered or needle probe card comprising a cantilevered probe 3220 that provides a signal to and receives a signal from the product die 3111. Probe 3220 may be constructed from any suitable conductive material, including tungsten. As shown in the top view of the probe card 3210 in FIG. 33, the probe 3220 is connected to a contact pin or point 3304 in contact with the test circuit on the test die 3104. The probe card 3210 may be secured to the substrate 3106 through one or more securing pins 3302, screws or other securing means.

The probe 3220 is provided to contact the specific contact pad 1316 when the probe device 3213 is urged toward the product die 3111. In another embodiment, a separate probe card can be used to initially test the product circuit by probing the specific contact pad 1316 and then use the product device 3111 to test the entirety of the product device 3111 by probing of the bond pad 1314. Can be.

34 shows another embodiment in which a probe may be included on the same probe card 3410 to probe one or more specific contact pads 3116 and one or more bond pads 3114. In this embodiment, the probe 3220 provides or signals from a specific contact pad 3116 at the same time or at a different time that the probe 3218 provides a signal to or receives a signal from the bond pad 3114. Can be received. The probe 3218 is formed at a predetermined alignment corresponding to the alignment of the bond pads 3114. As shown in the plan view of the probe card 3410 of FIG. 35, the probe 3218 has a relatively rectangular shape that comes into contact with the peripheral bond pads 3114 on the product die 3111. As shown in FIG. The probe 3220 is not generally disposed in the same predetermined alignment of the probe 3218, but rather extends into an area surrounded by the probe 3218 (and bond pads 3114). In another embodiment, the probe 3220 may be outside of the area surrounded by the probe 3218 or may be placed in the same predetermined alignment with the probe 3218 and the bond pads 3114. As yet another embodiment, the probes 3218 may be arranged in a lead-on-center arrangement, or in any other desired arrangement to align with a similar arrangement of bond pads 3114 on the product die 3111. In addition, the probe 3220 may be arranged within or outside the placement of the probe 3218 to align with the corresponding particular contact pad 3116. As yet another embodiment, bond pads 3114 and specific contact pads 3116 may be arranged in any other alignment.

Probe card 3410 includes one or more contact pins 3502 that provide electrical connections between substrate 3106 and probes 3218 and 3220. Test die 3104 may be disposed on probe card 3410 (as shown in FIG. 33) or wired to pin 3502 and outside of probe card 3410 (as on substrate 3106). Or external to the electrical connections wired directly to the interconnection points 3304.

32 to 35, the bond pads 3114 and the specific contact pads 3116 have different heights. As an example, the bond pads 3114 may be larger than the particular contact pads 3116 (or vice versa). In this embodiment, the probes 3218 and 3220 may extend to different depths. That is, the probe 3220 may extend lower than the probe 3218 to make contact with the specific contact pad 3116.

36 illustrates a test device 3600 that is another embodiment of a test device 3100. The test device 3600 includes a test head 3204 and a probe card device 3613. The probe card device 3613 includes an interconnect substrate 3106, a test die 3104 and a membrane probe card 3610. Membrane probe card 3610 includes contact balls 3618 and 3620 that provide a signal to or receive signals from each of bond pad 3114 and specific contact pad 3116 when pressed to contact product die 3111. do. Contact balls or probes 3618 and 3620 may be constructed from any suitable conductive material, including solder.

As shown in the top view of the probe card 3610 of FIG. 37, contact balls 3618 may be arranged in a grid array to contact bond pads 3114 arranged in a corresponding grid array pattern. The contact balls 3620 can be aligned with a predetermined grid array outside the grid array pattern or distributed within the grid array pattern as shown in FIG. 37 to match the corresponding specific contact pads 3116 to the product die 3110. have. Alternatively, as shown in FIG. 38, contact balls 3618 may be arranged in the peripheral pattern to contact the bond pads 3114 arranged in the corresponding peripheral pattern. The contact balls 3620 may be arranged in a predetermined peripheral pattern outside of the peripheral pattern, or arranged in the peripheral pattern as shown in FIG. 38 and aligned with the specific contact pad 3116. In yet another embodiment, the contact balls 3618 can be arranged in a lead-on-center arrangement to align with the lead-on-center bond pads on the product die 3110, and the contact balls 3620 are corresponding specific contacts. It can be arranged inside or outside the lead-on-center arrangement to align with the pad.

As another example, the contact ball 3620 may be replaced with the spring contact element described above. In this embodiment, the specific contact pads 3116 may optionally be located within the grid array of bond pads 3114 as shown in FIG. 11, and the die size of the product die 3110 by additional specific contact pads. 12 may be smaller than the size of the bond pad 3114 as shown in FIG. As another example, bond pads 3114 and specific contact pads 3116 may be arranged in any other alignment.

The test die 3104 is electrically connected to one or more probes 3620 through the substrate 3106. The test die 3104 may also be electrically connected to one or more probes 3618 through the substrate 3106. Alternatively, the test die 3104 may be placed directly on the probe card 3610 or in any other location of the test apparatus 3600.

36-38 illustrate that a single membrane probe card can be used to communicate with a particular contact pad 3116 and a bond pad 3114, but as another example, a separate membrane probe card can be used for a particular contact pad 3116. And bond pads 3114 may be used for probing. That is, one or more probe cards may only be used to initially contact a particular contact pad 3116 with one or more contact balls 3618 and to test one or more product circuits of the product die 3111. Bond pads 3114 can then be used to subsequently contact one or more contact balls 3220 to test the product die 3111 as a whole. In another embodiment, multiple probe cards can be used with a mixture of contact balls 3618 and 3620.

In other embodiments, the bond pads 3114 and the specific contact pads 3116 may be at different heights. As an example, the bond pads 3114 may be larger than the particular contact pads 3116 (or vice versa). In this embodiment, the contact balls 3218 and 3220 have different heights. That is, the contact ball 3220 may extend lower than the contact ball 3218 to make contact with a specific contact pad 3116. Alternatively, other probe elements, such as spring contact elements, can be used to probe the shorter specific contact pads 3116.

Figure 39 illustrates a test apparatus 3900, which is another embodiment of a test apparatus 3100 that includes a test head 3204 and a COBRA style probe card apparatus 3913. COBRA style probe card devices are available from Wentworth Laboratories in Brookfield, Connecticut. The probe card device 3913 includes an interconnect substrate 3106, a (wired or ceramic) space transformer 3908, and a head device 3907. Head device 3907 includes top plate 3907, spacer 3910, bottom plate 3911, test die 3104, and COBRA style probes 3918 and 3920. Probes 3918 and 3920, when pressed against product die 3111, provide signals to and receive signals from bond pads 3114 and specific contact pads 3116, respectively.

The test die 3104 is electrically connected to one or more probes 3920 and also electrically connected to one or more probes 3918. The test die 3104 is provided on the bottom surface of the upper die 3909, on the top surface 3902 of the bottom plate 3911, on the bottom surface 3904 of the bottom plate 3911, and as shown in FIG. 39. 3106, or any other location of the test device 3900.

The probe 3918 is generally formed in the grid array to contact the bond pads 3914 arranged in the corresponding grid array pattern. The probes 3920 are aligned and arranged in a predetermined grid array outside the grid array pattern, or distributedly arranged in the grid array pattern as shown in FIG. 40 to contact a specific contact pad 1816. Alternatively, as shown in FIG. 41, the probe 3918 may be arranged in a peripheral pattern to contact the bond pads 3114 arranged on the product die 3111 in a corresponding peripheral pattern. The probe 3920 may be aligned to a predetermined peripheral pattern outside or within the peripheral pattern as shown in FIG. 41 to probe a particular contact pad 3116. In yet another embodiment, the probe 3918 may be arranged in a lead-on-center arrangement and aligned with a lead-on-center bond pad on the product die 3111, and the probe 3920 may be in a lead-on-center arrangement It may be aligned within or outside with the corresponding particular contact pad. As another example, the bond pads 3114 and the specific contact pads 3116 may be arranged in any other alignment.

39-41 illustrate the use of a single probe card device to communicate with a specific contact pad 3116 and a bond pad 3114, but as an alternative embodiment, separate probe cards may be used for the specific contact pad 3116. ) And bond pads 3114 may be used for probing. That is, one or more probe cards may only be used to initially contact a particular contact pad 3116 to one or more probes 3920 and to test the associated product circuit of the product die 3111. One or more additional probe cards may then be used to subsequently contact the bond pads 3114 to one or more probes 3918 to test the product die 3111 as a whole. As another embodiment, the multiple probe card device may be used having a mixture of probes 3918 and 3920.

In other embodiments, the bond pads 3114 and the particular contact pads 3116 may be at different heights. As an example, the bond pads 3114 may be larger than the particular contact pads 3116 (or vice versa). In this embodiment, the probes 3918 and 3920 may extend to different depths (or may have different heights). That is, the probe 3920 may extend lower than the probe 3918 to make contact with the specific contact pad 3116.

Figure 42 illustrates a test apparatus 4200, which is another embodiment of a test apparatus 3100 that includes a test head 3204 and a probe card apparatus 4213, such as those provided by Form Factor, Inc., Livermore, CA. One embodiment of the probe card device 4213 is described in PCT patent WO 96/38858. The probe card device 4213 includes a probe card 4204, an interposer 4206, a space transformer 4210, and spring contact elements 4218 and 4220. The spring contact elements 4218 and 4220, when pressed towards the product die 3111, provide signals to or receive signals from each of the bond pads 3114 and specific contact pads 3116.

The test die 3104 is electrically connected to one or more probes 4220, and may also be electrically connected to one or more probes 4218. Interconnection may be accomplished by probe card 4204, interposer 4206, or space transformer 4210. The test die 3104 is placed at the bottom of the interposer 4206, at the space transformer 4210, at the probe card 4204, or at any other location of the test apparatus 4200, as shown in FIG. Can be.

A spring contact element 4218 is provided at a given alignment to provide a signal to and receive a signal from the corresponding bond pad 3114. In one embodiment, the probes 4218 are arranged in a grid array pattern. The spring contact elements 4220 may be arranged aligned to a predetermined grid array outside the grid array pattern, or may be distributedly arranged within the grid array pattern and aligned to the corresponding specific contact pad 3116. As another embodiment, the spring contact element 4218 may be arranged in a peripheral pattern. The spring contact element 4220 may be arranged in an area surrounded by a predetermined peripheral pattern outside the peripheral pattern, or distributedly arranged in the peripheral pattern and aligned with the corresponding specific contact pad 3116. As yet another embodiment, the spring contact element 4218 can be arranged in a lead-on-center arrangement, and the spring contact element 4220 can be arranged within or outside of the lead-on-center arrangement to correspond with a corresponding specific contact pad. Can be aligned. As yet another embodiment, bond pads 3114 and specific contact pads 3116 may be arranged in any other alignment.

Although FIG. 42 illustrates that a single probe card device can be used to communicate with a specific contact pad 3116 and bond pad 3114, alternative embodiments may employ a separate probe card device (or probe card) for specific contact. Pad 3116 and bond pad 3114 may be used for probing. That is, one or more probe card devices may test one or more product circuits of the product die 3111 by initially contacting only one particular contact pad 3116 with one or more spring contact elements 4220. . One or more additional probe card devices may then be used to contact the bond pads 3114 to one or more spring contact elements 4218 to test the product die 3111 as a whole. As another embodiment, the multiple probe card device may be used having a mixture of spring contact elements 4218 and 4220.

As an alternative embodiment, the bond pads 3114 and the particular contact pads 3116 may have different heights. As an example, the bond pads 3114 may be larger than the particular contact pads 3116 (or vice versa). In this embodiment, the probes 4218 and 4220 may extend to different depths (or different heights). That is, the probe 4220 may extend lower than the probe 4218 to contact the specific contact pad 3116.

As an alternative embodiment, spring contact elements 4218 and 4220 may be attached to bond pads 3114 and specific contact pads 3116 on product die 3111. In this embodiment, the space transformer 4210 may include pads to make contact with the spring contact elements 4218 and 4220. As another example, a portion of the spring contact element 4218 or 4220 may be attached to the space transformer 4210 and a portion of the spring contact element 4210.

The product die produced by the design methodology described above may also be inserted into the socket to be tested by the test die. The product die need not be packaged in a package commonly known for semiconductor integrated circuits, or packaged (eg in a chip-scale configuration). Any generally known socket can be used to support the product die. The test die may be mounted on a printed circuit board and in direct contact with the product die (eg, via spring contact elements, etc.), or indirectly through the product die via contactors, edge connectors, or the like.

46 shows a solder-down (surface mount) LGA socket 4600 for mounting on a printed circuit board 4610 and for making pressure contacts to bond pads 4612 and specific contact pads 4614 of LGA package 4604. It is shown. LGA package 4604 may comprise a product die designed according to the design methodology described above. As used herein, the term "socket" means an electronic component having interconnection elements suitable for making electrical connections to terminals or connection points of other electronic components. The socket shown in Fig. 46 is intended to detachably connect a semiconductor package to a circuit board. Other embodiments of socket 4600 are owned by Applicant and described in US Pat. No. 5,772,451, which is incorporated herein by reference.

The printed circuit board 4610 has a plurality of terminals or pads 4618, and the package 4604 has a plurality of bond pads 4612 and specific contact pads 4614. Socket 4600 provides a means for electrically interconnecting terminal 4618 to pads 4618 and 4612. Test circuits provided on or in communication with printed circuit board 4610 provide signals to or monitor signals from pads 4612 and 4614 through sockets 4600. By way of example, programmable circuitry in package 4604 may be programmed or monitored via spring contact element 4616, specific contact pads 4614 or pads 4612.

The socket 4600 includes, for example, a support substrate 4608 formed of conventional printed circuit board material. The support substrate 4608 includes a spring contact element 4616 formed on its top surface and a pad 4462 formed on its bottom surface. The spring contact element 4616 is for contacting the pads 4612 and 4614 of the package 4604 when the package 4604 is pressed downward by a force applied to the top surface of the package 4604 by the retaining means 4602. will be. In addition to the spring contact elements, other contact elements may be used. The support substrate 4608 also includes an electrical conduit 4624 that provides electrical interconnection between the spring contact element 4616 and the pad 4462. As an alternative embodiment, the spring contact element 4616 can be directly connected to the terminal 4618.

Contact balls (such as conventional solder balls) are disposed on the bottom of the pad 4462. Contact ball 4462 acts as a contact structure disposed on the bottom surface of support substrate 4608 to contact corresponding pad or terminal 4618 on printed circuit board 4610. Other electrical contact structures can also be used.

The socket 4600 also includes a frame 4606 attached to the printed circuit board 4602. Frame 4606 includes a landing 4626 for supporting package 4604. The socket 4600 also includes a frame 4626 and retaining means 4602 disposed on the package 4604. Retention means 4602 maintains package 4604 on landing 4626 such that spring contact element 4616 maintains electrical contact with pads 4612 and 4614. Instead of the retaining means 4602, any suitable mechanical means, such as a spring clip, may be used.

FIG. 47 illustrates another embodiment of a socket 4600 with a test die 4630 disposed on a printed circuit board 4610. Test die 4630 can be designed according to the design methodology described above. Terminal or pad 4618 may be formed on test die 4630 for electrical interfacing with contact ball 4620. As another embodiment, the spring contact element 4616 may be directly connected to the terminal 4618.

Additionally or alternatively, one or more spring contact elements 4616 may be attached to pads 4612 and 4614. In this configuration, the spring contact element can be in contact with the pad or terminal on the top surface 4452 of the support substrate 4608 or in direct contact with the terminal 4618.

While the invention has been described in detail with reference to specific embodiments thereof, various changes and modifications will be possible within the broad spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

The present invention provides a design and test methodology that breaks the direct correlation between fault coverage or testability and test cost or manufacturing cost of the design.

1 is a process diagram of a design methodology for designing a product die and a test die in accordance with an embodiment of the present invention.

2 is a schematic diagram of an integrated product circuit and test circuit design in accordance with an embodiment of the present invention.

3 is a schematic diagram of a product die created after the division of the integrated design of FIG.

4 is a schematic diagram of a test die created after the division of the integrated design of FIG.

5 is a schematic diagram of one embodiment of a test circuit in a test die;

6 is a process diagram of a design methodology for designing product circuits and test circuits in accordance with another embodiment of the present invention.

7 is a process diagram of one embodiment of a process for determining division of a product circuit and a test circuit.

8 is a process diagram of a design methodology for designing a product circuit and a test circuit in accordance with another embodiment of the present invention.

9 is a schematic diagram of one embodiment of a computer system that may be executed as a process in FIGS. 1 and 6-8.

Figure 10 is a logic diagram of one embodiment of a particular contact pad coupled to an internal circuit node via a bidirectional buffer.

Figure 11 is a plan view of one embodiment of an integrated circuit having bond pads aligned to a grid pattern, specific contact pads not aligned to the grid pattern, and specific contact pads aligned to the grid pattern.

12 is a cross-sectional view of a particular contact pad located between two bond pads having contact balls.

Figure 13 is a plan view of one embodiment of an integrated circuit with lead-on-center bond pads, internal circuitry, and specific contact pads for testing the internal circuitry.

14 is a schematic diagram of one embodiment of a sequence circuit block and a specific contact pad for testing the sequence circuit.

Figure 15 is a circuit diagram of one embodiment of the switch of Figure 16;

Figure 16 is a schematic diagram of one embodiment using specific contact pads to isolate fault circuit diagrams and enable preliminary circuit diagrams.

Figure 17 is a schematic of another embodiment using specific contact pads to isolate fault circuit diagrams and enable preliminary circuit diagrams.

Figure 18 is a schematic of one embodiment of using a specific contact pad to enable or simulate the circuit under test.

Figure 19 is a schematic diagram of one embodiment of using a specific contact pad to provide a control signal to a scanning circuit.

20 is a side cross-sectional view of a test apparatus for testing a product die.

Figure 21 is a cross sectional side view of a test apparatus for testing a multi-product die on a wafer under test.

Figure 22 is a side cross-sectional view of another embodiment of a test apparatus including a spring contact element attached to a product die.

Figure 23 is a side cross-sectional view of another embodiment of a test apparatus in which the spring contact element, the bond pad, and the specific contact pad have a variable height.

Figure 24 is a side sectional view of one embodiment of a spring contact element.

Figure 25 is a perspective view of one embodiment of the pyramidal contact features and contact tip structure of the spring contact element of Figure 24;

Figure 26 is a perspective view of one embodiment of the pyramidal contact tip structure of Figure 25;

Figure 27 is a cross-sectional side view of one embodiment of a test apparatus including multiple test dies for testing a single product die.

Figure 28 is a cross-sectional side view of one embodiment of a test apparatus including a single test die for testing multiple product dies.

Figure 29 is a side cross-sectional view of one embodiment of a test apparatus including a test die shared by another test die.

30 is a side cross-sectional view of another embodiment of a test apparatus including a test die shared by another test die.

Figure 31 is a side cross-sectional view of one embodiment of a test device including a test die, a contactor, and a product die.

Figure 32 is a cross-sectional side view of one embodiment of a test apparatus including a test die and a probe card having a cantilevered probe for probing a specific contact pad of a product die.

33 is a plan view of the probe card of FIG.

Figure 34 is a cross-sectional side view of another embodiment of a test apparatus including a test die and a probe having a cantilevered probe for probing a specific contact pad and bond pad of a product die.

35 is a plan view of the probe card of FIG.

Figure 36 is a cross-sectional side view of another embodiment of a test apparatus including a membrane probe card having a bond pad of a product die and a contact for probing a particular contact pad.

FIG. 37 is a top view of the membrane probe card of FIG. 36 having contact balls aligned to the grid pattern and contact balls not aligned to the grid pattern.

FIG. 38 is a plan view of the membrane probe card of FIG. 36 with contact balls aligned in a peripheral pattern and contact balls not aligned in a peripheral pattern.

Figure 39 is a side cross-sectional view of another embodiment of a test apparatus including a cobra-type probe card device having a probe for probing a specific contact pad and a bond pad of a product die.

FIG. 40 is a top view of the cobra-shaped probe tip of FIG. 39 with some tips aligned to the grid pattern and other tips not aligned to the grid pattern. FIG.

FIG. 41 is a top view of the cobra-shaped probe tip of FIG. 39 with some tips aligned to the peripheral pattern and other tips not aligned to the peripheral pattern.

Figure 42 is a cross-sectional side view of another embodiment of a probe card device having a spring contact element for probing a bond pad and a specific contact pad of a product die.

Fig. 43A is a side sectional view of another embodiment of a spring contact element.

Fig. 43B is a perspective view of the spring contact element of Fig. 43A.

44A is a perspective view of another embodiment of a spring contact element.

Figure 44B is a side sectional view of the spring contact element of Figure 44A.

45 is a perspective view of another embodiment of a tip structure for a spring contact element.

Figure 46 is a cross-sectional side view of one embodiment of a socket for holding a package having specific contact points and conventional input, output, and input / output pins.

Figure 47 is a side cross-sectional view of another embodiment of a socket including a test die on a printed circuit board.

Explanation of symbols on the main parts of the drawings

100: design methodology

200: unified design

202A, 204A, 206A: Test Circuit

202, 204, 206: Product Circuit

300: Die Product

400: test die

Claims (44)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete How to design product circuits and test dies, Creating a single integrated circuit design comprising a product circuit for the product die and a test circuit for testing the product circuit, Dividing the integrated circuit design into a product die and a test die, The dividing step, Assigning the product circuit to the product die, Assigning a first portion of the test circuit to the test die, Allocating a second portion of the test circuit to the product die. 18. The method of claim 17 further comprising separately fabricating a test die and a product die. 18. The method of claim 17, wherein the generating comprises creating an interconnect between the product circuit and the test circuit. 20. The method of claim 19, wherein the dividing further comprises creating a first interconnect point for the test die and a second interconnect point for the product die for interconnection between the product circuit assigned to the product die and the test circuit assigned to the test die. Design method that includes more steps. 21. The method of claim 20, wherein the first interconnect point corresponds to a pad on a test die and the second interconnect point corresponds to a pad on a product die. 18. The method of claim 17, wherein partitioning comprises using a weighting function to partition the integrated circuit design. The method of claim 22, wherein the dividing step, Determining whether the divided circuit meets certain criteria; If the divided circuit does not meet the criteria, further comprising repeating the dividing step. 24. The method of claim 23 wherein the determining comprises simulating a divided circuit. 24. The method of claim 23, wherein the determining step further comprises determining whether the divided circuit meets a plurality of criteria. 27. The method of claim 25, wherein the criterion comprises at least one of a maximum size of a product die and a maximum size of a test die. 27. The method of claim 25, wherein the criterion comprises a manufacturing cost of each of the test die and the product die. 27. The method of claim 25, wherein the criteria includes a specific fault range for testing a product circuit. 27. The method of claim 25, wherein the criteria includes speed test accuracy of signals in the product die monitored by the test circuit. 27. The method of claim 25, wherein the criteria include manufacturing process parameters of each of the test die and the product die. 27. The method of claim 25, wherein the criteria includes an AC timing parameter of a signal in the product die. The method of claim 17, wherein the generating step, Determining test performance of the host controller in communication with the test die; Selecting the first test for execution by the test circuit and selecting the second test for execution by the host controller. 18. The method of claim 17, wherein the second portion of the test circuit comprises a built-in self-test (BIST) circuit. 18. The method of claim 17, wherein the second portion of the test circuit comprises a scan (SCAN) circuit. 18. The method of claim 17, wherein the test circuit is capable of testing a plurality of product dies each having a product circuit. 18. The method of claim 17, wherein dividing further comprises dividing an integrated circuit design into a plurality of test dies. The method of claim 36, wherein the dividing step, Assigning a first portion of the test circuit to the first test die; Assigning a third portion of the test circuit to the second test die, Allocating a fourth portion of the test circuit to the third test die. 38. The method of claim 37, wherein the first test die performs a function shared by the second test die and the third test die. 39. The method of claim 38, wherein the shared function comprises generating a test pattern. The method of claim 38, wherein the first test die is in communication with a host controller. 18. The method of claim 17, wherein the first portion of the test circuit includes all test circuits and all test circuits are assigned to the test die. 18. The method of claim 17, further comprising fabricating a test die and a product die on separate semiconductor wafers. 38. The method of claim 37, wherein the first, third, and fourth portions of the test circuit include all test circuits, wherein all test dies are assigned to the first to third test dies. 44. A computer readable storage medium having stored thereon a computer program comprising instructions for implementing each step of the method according to any one of claims 17 to 43.