JP2005049336A - Test method for semiconductor product die, and assembly including test die for test - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide design and test methodology for breaking a linear relation between a defect detecting range or test possibility and a design test or a cost related to production. <P>SOLUTION: The present invention relates to a test assembly for testing a product circuit of a product die, and a product and a test die are prepared on a semiconductor wafer. The product circuit and a test circuit are divided into individual dies to eliminate or minimize the embedded test circuit on the product die 616. This provides a tendency of reducing a size of the product die, of reducing a production cost for the product die, and of maintaining a high-level test range for the product circuit in the product die. Then, the large number of product dies on one or more of wafer(s) can be tested using a test die 618. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to integrated circuit (IC) semiconductor devices, and more particularly to testing such devices.

  As the complexity and density of integrated circuit design increases, design methodologies are designed using design-for-test (DFT) technology to improve the testability and quality of the final product. It is required to produce. Test methodologies are also required to produce high quality, low cost test solutions.

  One conventional design methodology is to first design an integrated circuit using a software design tool, simulate the overall function of the design or individual circuits in the design, and then use the overall function of the design. Some include the process of generating test vectors for testing. The test vectors are typically generated by an automated software tool (eg, an automatic test pattern generator or ATPG) that provides a certain fault coverage or defect simulation for circuits in the product. Such test vectors are then provided to an automatic testing equipment (ATE) or tester, typically in the form of a computer readable file. ATE is used in manufacturing environments for testing dies on wafers and in packaged tests. Integrated circuit designs become more complex and are processed at higher speeds, which demand more from test equipment. This tends to increase the cost of the ATE and therefore tends to increase the manufacturing cost. Furthermore, as integrated circuit design becomes more complex, the time required to test the circuit increases. This also increases manufacturing costs.

  During die wafer level testing, test signals are provided via input or input / output (I / O) bonding pads on the die, and the test results are output on the output or I / O bonding pads. Be monitored. A good die that has passed wafer level testing is singulate, typically by electrically connecting its bonding pads to the package via bonding wires, solder balls, or other contact structures, Packaged. In accordance with the bonding wire or solder ball, the bonding pad is generally very large compared to the circuit elements of the integrated circuit. Typical bonding pad sizes are on the order of 100 μm × 100 μm (4 mils × 4 mils). The bonding pads are also typically arranged in a regular pattern, e.g., in a grid pattern along the periphery of the die, or in rows and columns through approximately the middle of the die (lead-on-center: lead-on-center).

  To improve the test coverage of individual circuits, DFT tools have been developed that incorporate test circuits into the design itself. For example, a built-in self test (BIST) circuit can be inserted into the design to test individual circuit blocks. BIST is particularly useful for testing circuit blocks that are not easily accessible by the bonding pad of the device under test (DUT). Well-known DFT tools (such as those provided by Mentor Graphics, Oregon) for generating BIST circuits (such as memory BIST for testing memory blocks and logic BIST for testing logic blocks) It is. The results of tests performed by the BIST circuit are provided directly to the external I / O or indirectly to the external I / O through a boundary scan circuit that can be included in the design. Additional internal built-in test circuits, such as SCAN chain circuits, can be added to the design to increase the internal testability of internal and sequential designs. .

  To support on-chip test circuitry when a die already provides all of its peripheral, grid, or lead-on-center bonding pad locations for a single device function Adding additional bonding pads with a predetermined bonding pad arrangement greatly increases the die size. Correspondingly, the die cost tends to increase. In general, the larger the die size, the easier it is for defects to result, resulting in higher manufacturing costs. Furthermore, on-chip test circuitry can significantly increase test time. This is because multiple clock cycles may be required to load test input data and then output test results from a few available bond pads. The on-chip test circuit also does not consider direct external access to internal circuit nodes. Test input data and test results can only be monitored after passing through the SCAN circuit or BIST circuit. This requires an additional circuit that can mask the failure of the circuit under test, or a new failure may be caused by the SCAN or BIST circuit.

  Furthermore, many designs limit I / O. This is because a given package scheme can accommodate only a limited number of leads (eg, bonding wires). In addition, these same lead locations must be used to test the die I / O function. Accessing more points in the circuit is advantageous (especially for testing). It is also advantageous to be able to locate the access point with a high degree of positional freedom. It is also advantageous to have a small size of the access point, a large number of the access points, and any or selective positioning of the access points.

  In the case of embedded test circuits, integrated circuit design methodologies first design the integrated circuit using software design tools and simulate the overall function of the integrated circuit or individual circuits in the design. And an embedded test circuit for testing individual circuits or circuit blocks in the design, and a test vector for performing a functional test of the device by the ATE.

  The amount of embedded test circuitry added to a particular design typically results in increased die coverage and possible reduced test time, and die size that increases the manufacturing cost of the final product And the disadvantages of increased manufacturing defects and the possibility of manufacturing defects need to be balanced. In one extreme example, a design can include complex embedded test circuits that test every circuit node of all internal circuits, but such designs are prohibitively expensive. This is because the die size is basically a function of the size of the test circuit. In another example, the design shall not include any embedded test circuitry and test the functionality of the design at the wafer level or in packaged form depending only on the test vectors supplied by the ATE. Is possible. However, this method tends to reduce the defect detection range, reduce product quality, and increase manufacturing costs by using expensive ATE and increasing test time. One method for minimizing the cost of using expensive ATE is known (see, for example, Patent Document 1). This patent document 1 condenses general-purpose functions of ATE into a general-purpose function test chip. The test chip can test other semiconductor chips under the control of the host computer. The test chip can be arranged on the probe card, or can be brought into electrical contact with the test target chip via the mother board. An alternative method is disclosed in US patent application Ser. No. 08 / 784,862, filed Jan. 15, 1997. In this application, a wafer level test of a semiconductor chip is performed by a test chip having a general-purpose test circuit.

Between the two extreme examples above, a typical integrated circuit design will reach an equilibrium between the amount of embedded test circuitry and the tests that will be performed by the ATE. Typically, the embedded test circuit is limited to about 5-15% of the total die area of the design, and test vectors are generated for the ATE to test the overall functionality of the design. However, the defect detection range obtained as a result of this equilibrium is less than the optimum defect detection range, and it is still necessary to use an expensive ATE.
U.S. Pat.No. 5,497,079

  It is desirable to obtain a design and test methodology that breaks the linear relationship between defect detection range or testability and the cost of testing or manufacturing the design.

  One embodiment of the invention relates to a test assembly for testing a product circuit of a product die. In one embodiment, the test assembly includes a test die and an interconnect substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die can be designed according to a design methodology that includes simultaneously designing the test circuit and the product circuit in a unified design. The test circuit can be designed to provide a high degree of defect detection coverage for the corresponding product circuit, almost independent of the amount of silicon area that will be required by the test circuit. The design methodology then divides the integrated design into test dies and product dies. The test die includes a test circuit, and the product die includes a product circuit. The product die and test die are then fabricated on separate semiconductor wafers. By dividing the product circuit and the test circuit into separate dies, the embedded test circuit can be eliminated or minimized from the product die. This tends to reduce the size of the product die and reduce the manufacturing cost of the product die while maintaining a high test range of the product circuitry within the product die. The test die is then used to test a number of product dies on one or more wafers.

  Other objects, features and advantages of the present invention will become apparent from the accompanying drawings and the following detailed description.

BEST MODE FOR CARRYING OUT THE INVENTION

  While the features and advantages of the present invention are illustrated by way of example embodiments, this is in no way intended to limit the scope of the invention to that particular embodiment.

  In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art can practice the invention without such specific details. In some embodiments, well known methods, procedures, and components have not been described in order to avoid obscuring the present invention.

  FIG. 1 is one embodiment of a design methodology 100 for designing product dies and corresponding test dies. The test die includes a test circuit that provides test signals to or monitors signals from one or more circuits on the product die. 2-4 illustrate the product die and test die generated by the design methodology 100. FIG.

  Throughout this specification, the terms “product die” and “product device” mean an example of an integrated circuit formed on a semiconductor wafer or on an insulating substrate or other suitable substrate. Such term also refers to a device under test (DUT). The term “product circuit” means a circuit of a product die, including integrated semiconductor circuits, integrated microelectromechanical structures or systems (MEMS), or other suitable circuit elements. It can be composed of active or passive elements. Furthermore, the terms “test die” and “test device” mean an integrated circuit formed on a semiconductor wafer or on an insulating substrate or other suitable substrate. The test die includes circuitry for providing test signals to the product die and / or monitoring signals from the product die. The test die can also be composed of active or passive elements, including integrated semiconductor circuits, integrated MEMS, or other suitable circuit elements for testing or monitoring the product die. Later, test dies and product dies can be used in land grid array packages (eg, ball grid array (BGA) packages, pin grid array (PGA) packages, control collapse chip connections (controll)). It can be packaged into any commonly known package, including collapse chip connection) packages, flip chip packages, other surface mount packages, dual in-line packages (DIP), etc.).

  At step 102, the circuits for the product die and test die are designed in an integrated design 200. The design can be performed in a conventional computer aided design (CAD) system that designs the product circuit 202,204,206 and test circuit 202A, 204A, 206A (eg, in VHDL or Verilog HDL format) using conventional software tools. Is possible. Test circuits 202A, 204A, 206A may be collectively referred to as “test benches” and are designed to be as robust (ie, robust) as desired. That is, the test circuits 202A, 204A, 206A can be designed to include a desired number of test functions to test the corresponding product circuits 202, 204, 206, respectively. One test circuit can be designed to provide a 100% defect detection range for the corresponding product circuit, or can be designed to provide a different desired defect detection range. . In contrast to the previous Design-For-Test (DFT) design methodology, test circuits 202A, 204A, 206A should be designed as described above regardless of the amount of silicon die area to implement the test circuit. Is possible. In one embodiment, the test circuit and the product circuit can each be designed such that the resulting product die and test die have approximately the same size. In another embodiment, the product die and the test die can be different sizes.

  At step 104, the product circuit and the test circuit are each divided into separate product dies and one or more test dies. By dividing the test circuit into separate test dies, it is possible to minimize or eliminate the test circuit on the product die. This reduces the die size of the product die, thereby reducing the likelihood of manufacturing defects and generally reducing manufacturing costs, while increasing the testability of the product die. An external test circuit that provides test stimuli can increase the number of tests without affecting the size of the product die 300. If the BIST circuit is not included in the test input or output signal path, the possibility of determining the position of the defect more accurately is increased. This is because there are no on-chip test circuits that mask the defects or cause further defects. Furthermore, it becomes possible to more accurately measure and monitor the speed parameter or timing of signals input to or output from the circuit block or circuit node without the delay caused by the intervening on-chip test circuit. .

  The product die design is taped out at step 106 and the test die design is taped out separately at step 108. The resulting product die 300 is then fabricated on a semiconductor wafer (not shown) along with many other identical product dies. The product circuits 302, 304, 306 included in the product die 300 may be any digital circuit, analog circuit, or other circuit corresponding to the product circuits 202, 204, 206, respectively.

  The resulting test die 400 is fabricated as including test circuits 402, 404, and 406. The test circuits 402, 404, and 406 correspond to the test circuits 202A, 204A, and 206A, respectively, and may be any digital circuit, analog circuit, or other test or monitoring circuit that respectively tests and monitors signals from the product circuits 302, 304, and 306. Is possible. For example, each test circuit is a functional circuit for testing the logical operation of a product circuit (eg, test pattern generator, sequencer, digital signal processor (DSP), formatter, analog-digital converter, digital-analog converter, defect) Analysis circuitry, etc.), and circuitry for testing AC parameters (eg, internal signal timing, circuit speed, etc.) and DC parameters (eg, voltage and current levels, power loss, etc.).

  Although each test circuit is designed to support specific testing of the corresponding product circuit, one embodiment of an exemplary test circuit 500 is shown in FIG. The test circuit 500 includes a control logic circuit 502 that controls the overall operation of the test circuit 500. The control logic circuit 502 can be a sequencer, for example. In connection with the control logic 502, a pattern generator 504, analysis logic 506, one or more parameter measurement units (PMU) 510, one or more digital power supplies (DPS) 512, and The clock logic circuit 514 operates. Pattern generator 504 generates one or more test patterns that are sent to product circuitry within product die 300 via input / output (I / O) circuitry 508. The pattern generator 504 can include a memory for storing patterns. The analysis logic circuit 506 analyzes the signal received from the product circuit of the product die 300 via the I / O circuit 508. The analysis logic 506 may include comparison logic that compares the expected result with the signal received from the I / O circuit 508. PMU 510 measures the voltage and current level of the signal received by I / O circuit 508. For example, the PMU 510 can measure leakage current, source current and voltage, sink current and voltage, power loss, and the like. The DPS 512 provides one or more power supply voltages to the product circuit to be tested. In an alternative embodiment, power can be supplied from a source other than the test die. The clock logic circuit 514 can provide a clock signal to a product circuit to be tested. In the case of an asynchronous circuit, a clock signal is unnecessary. Again, test circuit 500 represents one embodiment of a test circuit such as test circuits 402, 404, 406, etc. Other embodiments can also be used. All of the circuit blocks shown in FIG. 5 can be included in each test circuit 402, 404, 406, or any one or more of the circuit blocks in FIG. 5 can be shared by a plurality of test circuits 402, 404, 406. Is possible.

  Reference is again made to FIGS. The partitioning step 104 can be performed with a CAD DFT software tool and first determines the logical interconnection points between each product circuit and its corresponding test circuit, then the product die and test die. Create a logical and physical description of each. The interconnection points result in special contact points or contact pads (test pads) 310,410. The pad 310 provides a test signal to the product circuits 302, 304, and 306 or an output signal from the circuit. As described in detail below, the pad 310 is in electrical contact with the pad 410 of the test die 400 via a single contact structure (eg, a spring contact element, a probe of a probe card, etc.) for communication with the test circuits 402, 404, 406. Is possible.

  As shown in FIGS. 3 and 4, pads 310 and 410 can be physically placed around a particular circuit under test, or on a circuit to provide more direct access to a particular circuit node. It is possible to arrange. In general, the pads 310 and 410 can be disposed at any location on the product die and the test die, including the region surrounded by the bonding pad 312 in the product die 300 as shown in FIG. The pads 310 and 410 can also be arranged in the same predetermined arrangement as the bonding pads, or can be arranged outside the area surrounded by the bonding pads. The bonding pad 312 is a conventional input, output, or I / O pad that accepts the tip of a probe or accepts a bonding wire or solder ball during wafer sorting (wafer quality screening). The bonding pad 312 is conventionally used to operate the product die 300 as a whole. Similarly, the test die 400 can be used to test the overall function of the test die 400 (eg, during wafer sort) or can be used to bond out the test die to the pins of a semiconductor package. Includes possible bonding pads 412.

  When the pad 310 is disposed within the area surrounded by the bonding pad 312, the size of the product die 300 does not increase if the pad 310 has a given size and number. Furthermore, by transferring the test circuit to a separate test die, the bonding pads previously used to communicate with the internal test circuit can be omitted. Thereby, the size of the product die 300 is further reduced. In another embodiment, the addition of pad 310 may increase the size of product die 300. In one embodiment, the size of the pad 310 can be smaller than the bonding pad 312.

  In an alternative embodiment, splitting step 104 can determine that no additional interconnection points are required to test product die 300. For example, the split step 104 can be used by the bonding pad 312 to test the overall functionality of the product circuit 302, 304, 306, and then the bonding pad 312 can be connected to the test circuit 402, 404, and / or 406 when using the test die 400. It can be determined that a reassignment can be made to be used to interface. In this embodiment, the number of special contact pads can be zero, or can be less than that required in the above embodiment.

  After splitting in splitting step 104, several BIST circuits, such as BIST circuit 308, can be retained on product die 300. For example, to test a high speed circuit that would be improperly imposed by the addition of pad 310, or to provide pad 310 for interfacing with test die 400 when there is not enough space on product die 300 The BIST circuit can be advantageously held in the product die 300.

  In another embodiment, the design methodology 100 can use an existing or predetermined test circuit to generate a suitable product circuit. For example, in step 102, the product circuit can be designed to be tested by a predetermined test circuit with a desired level of defect detection range. Next, steps 104 to 108 perform the same processing as described above. This embodiment is particularly suitable when, for example, the product circuit in the product die is predictable like a memory circuit. Test circuits for testing such highly predictable architectures are well-known and well-tested (ie generate march patterns, galloping matrix patterns, etc.) It can only be used if the product circuit has to be adjusted to adapt. Further, the test circuit may have been previously formed on an existing test die, and splitting step 104 determines how to lay out the product circuit to maintain the predetermined test circuit, i.e. It is possible to add an interconnection point between the test circuit and the product circuit.

  FIG. 6 illustrates another embodiment of a design methodology 600 for designing one or more of the product die 300 of FIG. 3 and the test die 400 of FIG.

  In step 602, product design data for the product circuits 202, 204, 206 is generated, and in step 603, test design data for the test circuits 202A, 204A, 206A is generated. The design data is generated by a CAD software design tool in response to an input from a circuit designer regarding the circuit. The design data can exist in the computer in VDHL or Verilog HDL format. The test design data can be automatically generated by a CAD DFT software tool with or without input from a circuit designer. As described above with respect to the design methodology 100, the test design data is such that the test circuit generated by the data is as robust as desired by the circuit designer.

  At step 606, an integrated design register transfer level (RTL) description including both product data and design data is generated and verified by the CAD software. At step 606, a logical synthesis and verification of the integrated RTL description is generated. At this point, the software description of the integrated product and test circuit is complete.

  The test software tool 608 takes the integrated design output from step 606 and tapes out and then creates a description of the product die 300, one or more separate test dies 400, and interconnects. Generate data for At step 610, software tool 608 splits the integrated design into separate product and test die descriptions to generate a physical layout (eg, in silicon). This step is performed taking into account physical constraints 612 and user preferences (ie preferences) 614. This constraint 612,614 may be entered into the software tool 608 prior to execution of the design methodology 600, or the software tool 608 may prompt the user for this input at runtime.

  Physical constraints 612 include, for example, the resulting die size of the product die and test die, the number of bonding pads or special contact pads on each die, the size of the bonding pads and special contact pads on each die , Process constraints, or process technology. The physical constraints 612 can be used by the software tool 608 to determine the circuit and amount to split between the product die and the test die. As an example, the maximum die size of the product die 300 can be programmed as a parameter of the software tool 608 when performing step 610. If the product circuit and test circuit split results in too many special contact pads on the product die 300 and the product die size exceeds the desired die size, the software tool 608 The test circuit is reconfigured so that fewer interconnect points are required for the product circuit, and some of the test circuits on the test die are replaced with BIST circuits on the product die (ie, BIST circuit 308, etc. in FIG. 3). ) And / or some of the test circuits can all be eliminated. In another embodiment, a design constraint may be that special contact pads should not be created on the product die and / or test die. The software tool 608 tests and ensures that the product die has dual-purpose bonding pads (ie, the first purpose is to test all functions of the product die and the second purpose is to test individual product circuits using the test circuit). Divide the product circuit appropriately. Appropriate circuitry to enable or program this dual function can be included in the product die and / or test die.

  In another embodiment, the software tool 608 generates a large number of test dies where the required test circuit is best implemented in a variety of process technologies (eg, BiCMOS vs. CMOS) and thus supports the test circuit from different process technologies. Can be determined. In yet another embodiment, the software tool 608 is best implemented on a test die where some of the required test circuits have analog circuits and other required test circuits have digital circuits. It can be determined that it is best implemented.

  Another constraint that can be considered by the software tool 608 is that one or more of the test die test circuits are predetermined. For example, as described above, the product circuit can be designed to be tested in a predetermined level of defect detection range by a predetermined test circuit. The predetermined test circuit is particularly useful when, for example, the product circuit of the product die is predictable, such as a memory circuit. In this embodiment, software tool 608 divides the circuit to properly adjust the product circuit while maintaining a given test circuit, or to properly add an interconnection point between the test circuit and the product circuit. The mode to be determined is determined. In addition, the test circuit may have been previously formed on an existing test die, and the software tool 608 can be used (for example, to properly adjust the product circuit or an interconnection point between the test circuit and the product circuit). It is possible to determine how the product circuit is laid out to maintain the predetermined test circuit.

  Software tool 608 also performs step 608 taking into account other predetermined constraints such as user preferences 614. User or circuit designer preferences 614 may include, for example, the cost of providing an interconnection between a product die and a test die, product die cost, test die cost, timing priority, test accuracy, defect detection range, and The cost of interconnection between the test die and an external host device that controls or communicates with the test die is included. The term “cost” is used herein in a broad sense and includes manufacturability, ease of use, and the like.

  The cost of providing the interconnection between the product die and the test die includes the costs associated with the formation of special contact pads, the cost of forming the interconnect elements for communication between the product die and the test die, wafer sort And the ease of further testing with a specific number of special contact pads disposed on the product and test dies. If the cost of providing the interconnect is low, the circuit designer should indicate that the software tool 608 can divide the circuit regardless of the number of interconnects required between the product die and the test die Can do. However, if the cost of providing the interconnect is high, the circuit designer can indicate that the software tool 608 should divide the circuit to minimize or limit the number of interconnects .

  The resulting product die and test die monetary costs can also be used by the software tool 608 to determine how the product and test circuits are partitioned. For example, if there is enough space on the product die after the split to place a special contact pad for testing the product circuit without increasing the product die size, add the special contact pad And placing the corresponding test circuit in the test die does not increase the financial cost of the product die. Thus, in this example, the software tool 608 can split the product circuit and the test circuit to generate all of the required interconnection points. However, after splitting, there is sufficient space to add all of the special contact pads initially desired to the product die (or test die) without increasing the die size of the product die and thus the financial cost of the product die. If not, the software tool 608 can reduce the number of interconnects and pads to maintain the monetary cost of the product die and test die below a predetermined user preference.

  Timing priority and test accuracy are also used by the software tool 608 to determine how to split the product die and test die. For example, high-speed product circuits can be unnecessarily imposed and delayed by the addition of special contact pads. For this reason, software tool 608 can incorporate some of the test circuits into the product die as BIST circuits to test the circuits, thereby preventing delays in timing and test accuracy. .

  Defect detection ranges for testing product circuits can also be used by software tool 608 to determine how to divide product dies and test dies. For example, if a 100% or other advanced defect detection range is desired by the circuit designer, the test circuit generated in steps 602 through 606 needs to be generated for both the test die and the product die and test die. It can be divided into as many interconnection points or special contact pads as possible. However, if the circuit designer desires a low defect detection range, some of the test circuits generated by steps 602 through 606 are not divided into test dies. Circuit designers can enter product circuits that are more important to test than others, or a desired level of test range desired for each product circuit. Software tool 608 can use the inputs to determine which test circuit to maintain and reject in the final test die.

  The network interconnection cost between the test die and the external device can also be used by the software tool 608 to determine how to divide the product die and test die. The external device may be, for example, a host controller or other device for reporting product die test results. In another embodiment, the software tool 608 can generate multiple test dies, each with specific test circuitry for one or more product dies. The number of interconnection points, such as bonding pads 410 or special contact pads 412 of FIG. 4, required to support communication between the devices will affect the size of the test die, and therefore, depending on user input It is possible to limit (or not limit).

  After splitting the product circuit and test circuit into product die and test die description, logical verification and timing verification of the product die is performed in step 616, and logical verification and timing verification of the test die is performed in step 618. Is executed. The logical and timing verification of the product die and test die combination system operating together is performed at step 620. In response to steps 616-620, software tool 608 determines in step 622 whether all physical constraints 612 and user preferences 614 are satisfied. If constraints 612, 614 are met, the product die is taped out at step 624 and the test die is taped out at step 628, allowing a description of the interconnection points between the dies to be generated. If the constraints 612, 614 are not met, the software tool 608 repeats the above process. That is, the software tool 608 returns to step 610 to re-divide the product circuit and the test circuit in the second trial to satisfy the constraints 612 and 614. The process continues until all constraints are met. If the software tool 608 determines that all the constraints cannot be satisfied, the software tool 608 stops the process and notifies the designer to that effect. The designer can then change the design or change the constraints.

  One embodiment of the dividing step 610 is shown in step 710 of FIG. The dividing step 710 determines the layout of the product die and test die using conventional weighting techniques. For example, a weighting function is formed at step 702 in response to the complete system logic description from step 606, physical constraints 612, and user preferences 614. The weighting function describes the relative tradeoffs and constraints for a given partition. Many different numerical analysis techniques can be used to find the optimal solution for the partitioning problem described by the weighting function. One such technique is “simulated annealing”, where the design tool simulates the physical annealing process by raising the system mathematically to high temperatures. This makes it possible to find a solution quickly with minimal effort or cost. When applied at step 704, simulated annealing determines the best division of the product circuit and test circuit between the product die and test die so that the number of special contact pads, the amount of test circuit, Or it can be used to find the optimal solution by changing any physical constraints or user preferences.

  The design split in step 704 can make circuit adjustments in the test circuit, product circuit, and / or BIST circuit on the product die. The circuit adjustment includes the addition, removal, or modification of test circuits and / or BIST circuits to optimally test the product circuit. The circuit adjustment can also include the addition of additional test circuits to the test nodes introduced by the partitioning itself. This step can be completed automatically or based on interaction with the circuit designer.

  Once the partition is generated at step 704, the solution is tested, evaluated, and / or simulated at step 706 to determine whether an optimal solution has been generated and whether all of the constraints 612, 614 are satisfied. Is determined. If the weighting function is correctly defined, the tested solution will satisfy all of the constraints 612, 614 and describe product dies, test dies, and interconnections with (or without) BIST circuitry. Will be generated. If the user is not satisfied with the solution, adjust the constraints to create a new weighting function and generate new circuit divisions, special contact pads, die sizes, etc. between the product die and the test die Is possible.

  FIG. 8 shows a design methodology 800 as a variation of the design methodology 600 of FIG. 6 (or the design methodology 100 of FIG. 1). Depending on the application, the resulting test die generated by the design methodology 600 (or 100) can communicate with testers or host controllers such as ATE, general purpose computers, or other control logic or systems. It will be something. The tester, for example, starts and stops a test performed by a test die, supplies power to the test die, indicates a test sequence to the test circuit of the test die, indicates a test sequence between a number of test dies, and is received from the test die It is possible to create an inventory and report on the test results. The tester can also be used to test the product die as a whole, for example during wafer sort, which uses the test die to test individual product circuits or nodes, and a separate probe controlled by the tester. The card can be used to test the product die as a whole. In this way, the test can be selected to be distributed between the tester and the test die.

  In design methodology 800, test design data provided to RTL synthesis and verification step 604 is determined in steps 804-810. At step 808, the test is divided between the tester and the test die according to the test requirement 804 for testing the product circuit and a description 806 regarding the tester's capabilities. If the test is to be performed by a test die (determined in step 810), the test is provided to step 604 as part of the test design data along with the product circuit design data. However, if the test is to be executed by a tester, the test is stored in a test file 812 for the tester.

  The design methodology described in the described embodiments can be implemented in a software routine that can be implemented in a general purpose computer or workstation or a custom CAD system. One embodiment of a general-purpose computer system 900 on which the software routine is stored and executed is shown in FIG. Many other computer system embodiments may be used.

  The computer system 900 includes a computer 928 having a main memory 902, a static memory 904, a mass storage device 906, and a processor 912 that communicate via one or more internal buses 910. Main memory 902 may be, for example, dynamic random access memory (DRAM) or other volatile that stores program code, system code, and / or one or more software routines that are embodiments of various design methodologies. Alternatively, a non-volatile memory can be used. The static memory 904 may be a cache memory and may be used to store program code, system code, and / or one or more software routines that are embodiments of various design methodologies. Is possible. The mass storage device 906 can be any mass storage device such as a CD-ROM, floppy disk, hard disk, laser disk, flash memory card, or magnetic storage device. The mass storage device 906 is also capable of storing program code, system code, and / or one or more software routines that are embodiments of various design methodologies. The processor 912 can be any control logic that regulates the data flow in the computer system 928. For example, the processor 912 can be a microprocessor or one or more other digital signal processing devices.

  Computer 928 can communicate with one or more peripheral devices over bus 926. Data is input to the peripheral device to a computer 928, a display 914 for displaying graphical representations of product die and test die logic circuits and circuit elements generated by the design methodology and / or software routines of the design methodology. Keyboard 916 for recording, cursor control device 918 such as mouse, trackball or stylus, signal generation device 920 for providing other input signals to computer 928, hard copy device 922 such as printer, and audio recording and playback device 924 is included.

Special Contact Pad Referring to FIGS. Special contacts or special contact pads 310 allow test circuits 402, 404, 406 to provide test input data to product circuits 302, 304, 306 or signals from product circuits 302, 304, 306 without requiring testing the functionality of the entire product circuit 300. It provides a means for monitoring. Throughout the remainder of this chapter, the description will be made with reference to special contact pads 310 and bonding pads 312, but the same description applies equally to special contact pads 410 and bonding pads 412. .

  Special contact pads 310 may also be used when internal circuits 302-306 are otherwise not individually testable and / or are not accessible via bonding pad 312. It also provides a means for testing 306. For example, the product circuit 302 can be an embedded memory that cannot be accessed directly via the bonding pad 312. Address and input data are provided via some of the special contact pads 310 to provide a test pattern to the embedded memory, and another group of special contact pads 310 is read from the memory It is possible to receive data. To extend the defect detection range, an external circuit that provides a test pattern for an embedded memory can provide any number of test patterns.

  In another embodiment, the product circuit 302 can be a programmable circuit such as a non-volatile memory or a programmable logic circuit. Data can be programmed into internal circuitry via special contact pads 330. For example, BIOS information, program code, and system software can be programmed or updated in the programmable circuit 302 after the integrated circuit 300 is fabricated.

  As shown on the product die 300, a special contact pad 310 also works with the BIST circuit 308 (or other on-chip test circuit) to monitor the response of the internal circuit 306 to the test stimulus provided by the BIST circuit 308. Is possible. This can be accomplished without the need for adding additional bonding pads 312 or communicating the BIST circuit 308 using existing bonding pads 312.

  As shown in FIG. 3, the special contact pad 310 is disposed in a region surrounded by the surrounding bonding pads 312. Since the special contact pad 310 is not disposed at a predetermined peripheral position of the bonding pad 312, the addition of the special contact pad 310 does not increase the size of the product die 300. In other embodiments, the number and arrangement of special contact pads 310 can increase the size of the product die 300.

  Special contact pads 310 can also be interspersed between the bonding pads 312 or can be located outside the area surrounded by the bonding pads 312. In one embodiment where special contact pads 310 are interspersed between bonding pads 312, it is advantageous to make special contact pads 310 smaller than bonding pads 312 so as not to increase the size of product die 300. It is.

  The special contact pad 310 can be of any size including a smaller size than the bonding pad 312. If the special contact pad 310 is smaller than the bonding pad 312, more special contact pads can be added on the product die 300 without increasing the die size beyond the size defined by the surrounding bonding pad 312. It becomes possible to arrange. Increasing the number of specialized contact pads can increase the number and / or complexity of tests that can be provided to internal circuitry, which can increase the test defect detection range and robustness. It becomes. In one embodiment, the bonding pad 312 can be about 100 μm × 100 μm (4 mils × 4 mils), and a special contact pad can be 5-10 μm on one side. In another embodiment, the special contact pad can be less than 5 μm on one side. In yet another embodiment, to accommodate different spatial locations on the die (eg, “between bonding pads 312” and “area surrounded by bonding pads 312”) or various probe tips, Adapt to different dimensions of bonding wires or solder balls, or adapt to different functions of the circuit under test (eg, the node providing the output signal requires a pad larger than the pad providing the input signal ( It is possible to manufacture with different sizes, as well as vice versa). The lower limit of the size of the special contact pad may be limited by the alignment accuracy between the probe and the pad and the size of the probe.

  The special contact pad 310 can be formed in a generally square shape, rectangular shape, or any other geometric shape. The special contact pad 310 can also have a different height than the bonding pad 312. Special contact pads 310 can be made using conventional photolithography processes commonly used to form bonding pads and other relatively flat conductive lands. In one embodiment, special contact pads can be made from one or more metal layers including aluminum, copper, gold, or other metals or conductive materials.

  Special contact pads 310 are not permanently bonded out to integrated circuit packages (eg, typical plastic and ceramic chip packages) and receive test input information (eg, address signals, control signals, or data signals) Or to monitor internal test nodes or signals. However, the special contact pads are large enough to accept electrical contact elements (as will be described in detail below). Special contact pads 310 generally require support circuitry that is significantly smaller than the support circuitry typically required by bonding pads 312 when not bonded out to the package. A typical bonding pad includes support circuitry that requires a significant amount of silicon die area. Examples of support circuitry include electrostatic discharge (ESD) protection structures such as resistors, capacitors, and / or diodes, latch-up prevention circuits such as guard rings, to drive circuits and signal lines external to integrated devices or Examples include a buffer for buffering an internal signal received from an external signal line, a logic or voltage conversion circuit, and a noise reduction circuit. Special contact pads 310 can reduce the amount of support circuitry required. For external probes that are in electrical contact with a special contact pad and monitor the signal at the contact, little or no ESD protection is required and little or no buffering is required. For example, as shown in FIG. 10, an I / O buffer 320 can be used between an internal test point 324 and a special contact pad 310. The I / O buffer 320 can be controlled by a control signal 322. The I / O buffer 320 can be as weak as 1/10 to 1 / 10th of what is required when the bonding pad must drive heavy loads in a PCB environment. Further, little or no latch-up support circuitry or noise reduction circuitry is required. For example, all that is needed for each special contact pad for a noise reduction circuit is a weak pull-up resistor. In general, the special support pads require only 1-50% of the support circuitry typically required for bonding pads.

  3 and 4 show that special contact pads 310,410 are disposed within the area surrounded by bonding pads 312,412 disposed at the periphery, the special contact pads may be other product dies or It can also be arranged in the layout of the test die. The integrated circuit 1100 (product die or test die) shown in FIG. 11 includes bonding pads 312 aligned with an LGA pattern for bonding to contact balls (eg, solder or other metal interconnects) in a C4 or flip chip configuration. ing. The special contact pads 310 are selectively distributed inside or outside the grid pattern. In this embodiment, the special contact pads 310 are smaller than the bonding pads 312 or contact balls and do not increase the size of the integrated circuit 1100 beyond the minimum size required for a given number of bonding pads 312. It is like that. In an alternative embodiment, the special contact pad 310 can be the same size as the bonding pad 312.

  FIG. 12 is a cross-sectional view of a special contact pad 310 disposed between two bonding pads 312 as viewed from the side. The bonding pads 312 have contact balls 1204 formed thereon and are generally spaced with a minimum spacing 1202 (about 250 μm (about 10 mils)) between their centers. The minimum diameter 1208 of the contact balls 1204 is typically on the order of about 25-76 μm (1-3 mils), and the minimum distance 1206 between the edges of the contact balls 1204 is typically about 178-229 μm (7 ~ 9mil) order. Special contact pads 310 may be sized appropriately between bonding pads 312 and may have a width 1210 that is less than about 229 μm (9 mils). In another embodiment, the special contact pad 310 can have a width of about 25-127 μm (about 1-5 mils). In yet another embodiment, the special contact pad 310 can have a width of less than about 25 μm (1 mil). The special contact pad 310 can be formed in a generally square shape, rectangular shape, or other geometric shape. The special contact pad 310 can also have a different height than the bonding pad 312.

  The embodiment shown in FIGS. 11 and 12 also includes an LGA package, such as a BGA package, a PGA package, a C4 package, or a flip, having pins or contact balls for interfacing with a socket or printed circuit board (PCB). It can be a chip package. Special contact pads 310 can be additional pins or pads that can receive a test signal or provide a test output signal or other signal to a probe, socket, or PCB.

  FIG. 12 also shows a special contact pad 310 disposed between two peripherally aligned bonding pads 312 (as shown in FIG. 3). The contact ball 1204 need not be formed on the bonding pad 312.

  FIG. 13 shows an integrated circuit 1300 (product die or test die) that includes bonding pads 312 arranged in a row (or row) in a lead-on center pattern. Special contact pads 310 are selectively distributed on the inside and outside of the lead-on center pattern to provide test signals to or from the internal circuits 1302, 1304 of the integrated circuit 1300. It can be used to monitor the signal.

  3 and 4 show that product circuit blocks or internal circuit nodes can be tested or monitored with special contact pads. FIG. 14 shows that successive product circuits 1402, 1404, 1406 can also be tested with special contact pads with or without bonding pads. In this embodiment, test input data is provided from a test circuit on the test die to special contact pads 1412 and embedded memory 1402. In an alternative embodiment, the input data can be provided from a bonding pad. The test data can include addresses, control signals (eg, read, write, etc.), and / or test patterns. Assuming that the test data is an address at one location in the memory 1402, the data stored at the accessed address is provided via the I / O interface 1404 and by a special contact pad 1413 It is possible to monitor. The access time of the memory 1402 (ie, address to data out) can be measured more accurately with special contact pads 1412 and 1413. This is because no additional time is introduced due to circuit blocks such as I / O interface 1404 and I / O driver 1406. Conventional approaches using BIST circuitry typically include additional on-chip circuitry to provide address signals (eg, to memory 1402), and then external circuitry results in one or more bonding pads 1416. Can be monitored. However, this conventional approach cannot directly monitor the output of the memory 1402 (as is the case with the special contact pad 1413), and thus can directly measure the actual access time of the memory 1402. It will not be possible.

  Depending on the data read from the memory 1402, the I / O interface 1404 can format the data prior to provision to the I / O driver 1406. The I / O interface 1404 can receive control signals on a special contact pad 1414, that is, the internal circuit nodes in the I / O interface 1404 can be monitored by the special contact pad 1414. is there. Data output to the I / O driver 1406 by the I / O interface 1404 can be monitored via a special contact pad 1415. The I / O driver 1406 can then drive data to the bonding pad 1416.

  Special contact pads 1413, 1415 and bonding pads 1416 provide a memory 1402, an I / O interface 1404, and an It can be used to monitor the output of each of the I / O drivers 1406. In the conventional BIST technique where the address is provided to the memory 1402, for example, the source of illegal data received at the bonding pad 1416 is unknown.

  The embodiment shown in FIG. 14 includes a specific example of accessing data in the embedded memory 1402, but the example also applies to the introduction and monitoring of signals for any other series of circuit blocks. It is.

  Special contact pads can also be used not only to isolate defects, but also to enable redundant circuits that are used to replace defective circuits. FIG. 16 illustrates one embodiment of a test circuit on a test die that uses special contact pads to enable a redundant circuit to identify and replace a defective circuit block. Yes. This embodiment also uses the example for accessing data in embedded memory, but one of the series of circuits can be extended to the series of circuits with redundant circuits.

  FIG. 16 includes a redundant I / O interface 1405 that can be replaced with a defective I / O interface 1404. The output of memory 1402 is provided to both I / O interfaces 1404, 1405. The output of the I / O interface 1404 can be monitored by a test die via a special contact pad 1415, and the output of the redundant I / O interface 1405 should be monitored by a test die via a special contact pad 1417 Can do. Provide the signal on line 1423 to the I / O driver 1406 if the output of the I / O interface 1404 indicates that the output of the I / O interface 1404 is operating as expected Multiplexer 1408 is configured with a control signal on line 1421 so that it can be done. However, the output of the I / O interface 1404 indicates against the expectation that the I / O interface 1404 is not operating correctly, and the output of the redundant I / O interface 1405 is as expected. In some cases, multiplexer 1408 is configured with a control signal on line 1423 so that the signal on line 1425 can be provided to I / O driver 1406. The signal output by the multiplexer 1408 can be monitored via a special contact pad 1419.

  The control signal on line 1423 can be driven to an appropriate voltage level or logic state by switch 1410. Depending on the TOGGLE signal, the voltage V3 or V2 will be selected in response to monitoring the signal at the special contact pads 1417, 1415. The TOGGLE signal can be controlled by a test circuit on the test die via another special contact pad or bonding pad.

  FIG. 15 shows a switch 1500 that is one embodiment of the switch 1410 of FIG. Other embodiments of the switch 1410 can also be used. The PMOS transistor included in the switch 1500 is energized to an on state by having its gate coupled to ground, its source coupled to the power supply VDD, and its drain coupled to the signal line 1421. Switch 1500 also includes a fuse element 1504 coupled between signal line 1421 and ground. The fuse element 1504 can be a metal fuse, a resistive fuse, or a memory element. When the fuse element 1504 is blown in response to the TOGGLE signal, the signal line 1421 is pulled to VDD, and the signal on the line 1425 is output by the multiplexer 1408, for example. If the fuse element 1504 is not blown, the signal line 1421 is pulled to ground by the fuse element 1504 and the signal on the line 1423 is output, for example, by the multiplexer 1408. The fuse element 1504 can be cut using a number of well-known techniques including the use of laser pulses or current. As an example, a special contact pad can be used to provide a current that cuts through the fuse element 1504.

  FIG. 17 shows an alternative embodiment of the redundancy mechanism of FIG. In FIG. 17, it is possible to arrange a plurality of fuse groups 1702, 1704, 1706, 1708 before and after the I / O interface. When one of the I / O interfaces is identified as having a defect, the defective I / O interface can be isolated by a suitable fuse group. For example, if the I / O interface 1404 is defective and the I / O interface 1405 is operating correctly, the fuse group 1704, 1708 may be cut to isolate the I / O interface 1404. Is possible. The fuse group 1704, 1708 can be cut through a special contact pad (not shown) that provides one or more signals that carry high currents to the fuse group 1704, 1708. It is also possible to use alternative means for blowing the fuse.

  As described above with respect to FIG. 3, special contact pads can be used with the on-chip test circuit to test the product circuit. FIG. 18 illustrates an embodiment in which one (or more) special contact pads 1810 are used to provide a clock signal, reset signal, enable signal, or other control signal to the BIST circuit 1802. ing. In response, BIST circuit 1802 provides one or more test signals to internal circuit 1804 and / or internal circuit 1806. The results of the internal test are then monitored at bonding pad 1808 (or alternatively other special contact pads). In another embodiment, a special contact pad may be used to provide an enable signal or clock signal to any other internal circuit.

  Similarly, as shown in FIG. 19, one (or more) special contact pads 1910 are used to transfer clock signals, reset signals, enable signals, or other control signals to the shift register elements of the SCAN circuit. 1906 and 1908 can be provided. The SCAN circuit is coupled between bonding pads 1906, 1908 (or alternatively one or more special contact pads) capable of receiving SCAN input data SI and providing SCAN output data SO. It is possible to make it.

  In alternative embodiments, one or both of the pads 1212 can be special contact pads. This improves the design flexibility in the location and use of the SCAN circuit. For example, this makes it possible to test a variety of different internal circuits or circuit blocks using multiple SCAN regions or circuits of different sizes and complexity.

Test Methodology and Test Assembly A test die generated by one of the multiple design methodologies described above can be used to test or monitor product die signals using various test assemblies.

  FIG. 20 is a side cross-sectional view of one embodiment of a test assembly 2000 for performing a wafer level sort test on a product die 2011 with a test die 2010. FIG. The product die 2011 can be the product die 300 of FIG. 3, and the test die 2010 can be the test die 400 of FIG.

  Test assembly 2000 includes an interconnect and support substrate 2008, a test die 2010, and a product number 2012. Interconnect and support board 2008 provides electrical interconnection between test die 2010 and host 2002. The substrate 2008 also provides structural support for the test die 2010. The substrate 2008 may be one or more printed circuit boards (PCBs) that perform electrical interconnection and support functions. The substrate 2008 can be attached to a structure (for example, a wafer prober or chuck not shown) that supports the wafer 2012.

  The host 2002 communicates with the test die 2010 via the substrate 2008. Host 2002 can send signals for starting and stopping tests, cataloging test results and displaying them to the user, or sending other test data to test die 2010. Any type of host can be used, including a general purpose computer, ATE, or any other control logic.

  The test die 2010 includes special contact pads 2006 and bonding pads 2004. On those pads, spring contact elements 2020, 2018 are arranged. The product die 2011 is formed on a wafer 2012 that can contain other product dies 2011. The wafer 2012 can be placed on a suitable support structure such as a vacuum chuck (not shown).

  The spring contact element 2018 is formed in a predetermined arrangement to provide an electrical connection between the bonding pad 2004 and the bonding pad 2014 when the test die 2010 is biased toward the product die 2012. Spring contact element 2020 provides an electrical connection between special contact pad 2004 and special contact pad 2016 when test die 2010 is biased toward product die 2012. In one embodiment, the contact elements 2018 may be arranged in a corresponding grid array pattern to contact bonding pads 2014 arranged on the die 2011 in a grid array pattern. The spring contact element 2020 is aligned within a predetermined grid array pattern to make electrical contact with a corresponding special contact pad 2016 on the die 2011, aligned outside the grid array pattern, or the grid It is possible to arrange them in the array pattern. Alternatively, the spring contact elements 2018 can be arranged in a peripheral pattern so as to contact the bonding pads 2014 arranged on the die 2011 in a corresponding peripheral pattern. The spring contact element 2020 is aligned within a predetermined peripheral pattern, aligned outside the peripheral pattern, or by the peripheral pattern so as to make electrical contact with a corresponding special contact pad 2016 on the die 2011 It is possible to arrange and arrange within the enclosed area. In yet another embodiment, the spring contact elements 2018 can be arranged in a lead-on center arrangement to align with the corresponding lead-on center bonding pads 2014, and the spring contact elements 2020 have a corresponding special contact. It can be placed inside or outside the lead-on center array to align with the pad 2016. In yet another embodiment, the bonding pads 2014 and special contact pads 2016 can be arranged in any other arrangement.

  When test die 2010 is biased toward product die 2011 and contacts product die 2011, one or more of the product circuits can be tested simultaneously or sequentially by test die 2010 test circuitry. Become. Product die 2011 can also be tested as a whole. Wafer 2012 can include a number of product dies 2011, and test die 2010 can be stepped across wafer 2012 to test each product die. In the alternative embodiment shown in FIG. 21, multiple test dies 2010 are used in parallel to test multiple product dies 2011 on wafer 2012, thereby increasing test throughput. The test methodology shown in FIG. 21 can be extended so that the test die wafer 2009 simultaneously tests the corresponding product die wafer 2012.

  FIG. 20 shows that test die 2010 is equipped with contact elements 2018 and 2020 to communicate with bonding pad 2014 and special contact pad 2016, respectively, but using a number of independent test dies, It is also possible to perform probing of the contact pads 2016 and / or the bonding pads 2014. For example, a first test die 2010 including a bonding pad 2004 with attached spring contact elements 2018 can be used first to make contact with the bonding pad 2014 of the product die 2011. The first test die can functionally test the product die 2011 as a whole. Subsequently, a second test die 2010 including a special contact pad 2006 and a spring contact element 2020 can be used. The second test die 2010 can be used to test one or more of the product circuits of the product die 2011 simultaneously or sequentially. In another embodiment, it is possible to use multiple test dies with a mix of spring contact elements 2018, 2020. The number of test dies and the configuration of the test dies are determined by one or more of the design methodologies described above.

  In an alternative embodiment, spring contact elements 2018, 2020 can be attached to bonding pads 2014 and special contact pads 2016 on die 2011 as shown in FIG. In yet another embodiment, some of the spring contact elements 2018, 2020 can be attached to the test die 2010 and some of the spring contact elements 2018, 2020 can be attached to the die 2011.

  Also, the bonding pad 2016 and the special contact pad 2016 can have different heights. For example, as shown in FIG. 23, the bonding pad 2014 can be higher than the special contact pad 2016 (or vice versa). In this embodiment, the probes 2018, 2020 extend to different depths (or have different heights). That is, the probe 2020 extends to a position lower than the probe 2018 in order to contact the special contact pad 2016. In yet another embodiment, the bonding pad 2004 and the special contact pad 2006 of the test die 2010 can have different heights.

  FIG. 24 is a cross-sectional view of the spring contact element 2400, which is one embodiment of the spring contact elements 2018 and 2020 of FIGS. The spring contact element 2400 includes a base 2402, an elongated elastic member 2404, an elongated contact tip structure 2406, and a pyramidal contact structure 2408. Applicant's co-pending US patent application No. 08 / 526,246 (filed on September 21, 1995), Applicant's co-pending US patent application No. 08 / 558,332 (filed on November 15, 1995) Applicant's co-pending US patent application No. 08 / 789,147 (filed Jan. 24, 1997), Applicant's co-pending US patent application No. 08 / 819,464 (March 17, 1997) Many other embodiments of spring contact elements, including those disclosed in Applicant's co-pending US patent application Ser. No. 08 / 189,761 (filed Nov. 10, 1998). Is possible.

  The structure 2406 can be any shape. FIG. 25 illustrates one embodiment of structure 2406, a relatively wide end for contacting member 2404 and a relatively narrow end for supporting pyramidal contact structure 2408. FIG. have.

  FIG. 26 illustrates one embodiment of a pyramidal contact structure 2408. Other shapes can be used. The structure 2408 can advantageously be significantly smaller than the typical tungsten probe tip of a cantilever probe and the C4 contact ball of flip chip probe card technology. The tip of the pyramidal contact structure 2408 can have a length dimension 2414 and a width dimension 2416 of approximately 1-5 μm. In an alternative embodiment, the length dimension 2414 and the width dimension 2416 can be sub-micron dimensions. Since the size of the contact structure 2408 is small, the special contact pad can be made smaller than the bonding pad. As described above, when the special contact pad is smaller than the bonding pad, the special contact pad can be added to the integrated circuit such as the product die 2011 without increasing the die size. Furthermore, small special contact pads can be placed between the solder ball bonding pads.

  43A and 43B illustrate another spring contact element embodiment disclosed in US patent application Ser. No. 09 / 189,761. Spring contact element 4300 is coupled to substrate 4306 and includes an elongated elastic member 4304, a tip structure 4308, and a blade 4302. The blade 4302 is used to make an electrical connection with a bonding pad or special contact pad. Blade 4302 can be advantageously used to provide a good electrical connection to a contact bonding pad or special contact pad when the top surface of the pad is cut, sliced or penetrated It is. The blade 4302 can be disposed on the tip structure 4308 in a substantially horizontal direction, or in any other direction.

  44A and 44B are a perspective view and a side view showing another embodiment using a blade on the tip structure of the spring contact element. Blade 4400 is a blade having a plurality of heights disposed on tip structure 4406. The blade 4400 has a main blade 4402 that faces the front edge of the tip structure 4406 and a rear blade 4404 that faces the rear of the tip structure 4406.

  FIG. 45 is a perspective view showing another blade structure formed on the tip structure 4500. The blade of FIG. 45 is formed to have a generally rectangular base 4502 and a generally triangular portion 4504.

  FIG. 27 shows a test assembly 2700, another embodiment for performing a wafer level sort test for product die 2011. In this embodiment, two (or more) test dies 2010 can be used to test multiple different product circuits of a single product die 2011 simultaneously or sequentially. When testing a single product die using multiple test dies, the physical mapping or location of bonding pad 2014 and special contact pad 2016 determines which test die tests which product circuit of product die 2011 or It will be decided whether to monitor. Each test die must touch all of the pads that need to be tested by the test die.

  The plurality of test dies of assembly 2700 can be generated by the design methodology described above. For example, it is determined (eg, by software tool 608 in FIG. 6) that the test circuitry required to test the product circuit of product die 2011 is best implemented in a number of different process technologies (eg, BiCMOS and CMOS). It is possible to create different test dies to support test circuits with different process technologies. In another embodiment, software tool 608 provides that some of the required test circuits are best implemented in an analog circuit on the first test die, and a different required test circuit is the second. It can be determined that it is best implemented in digital circuitry on the test die.

  FIG. 28 shows another test assembly 2800 in which two (or more) product dies 2011 are tested by a single test die 2010. In this embodiment, a single test die 2010 may include multiple tests that can be performed on both product dies (simultaneously or non-simultaneously). In one embodiment, test die 2010 may include a single test circuit having multiple interconnect points or pads for providing replicated signals to multiple product dies 2011. In an alternative embodiment, test die 2010 may include multiple replicated test circuits for contacting multiple product dies. Alternatively, each product die 2011 can include a unique circuit that can be tested by a single test die 2010.

  The test assembly 2900 of FIG. 29 illustrates one embodiment of a hierarchical approach for testing a plurality of product dies 2011 with a plurality of test dies 2010. As shown in FIG. 29, each product die 2011 can be tested by a separate test die 2010. Test die 2902 is a second hierarchical level that communicates with host 2002 to support or control multiple test dies 2010. For example, the test die 2902 can be a shared resource that includes circuitry commonly used by all of the test dies 2010. It may be advantageous to transfer this common circuit to the test die 2902 to reduce the size of the test die 2010, for example. For example, an automatic pattern generator (APG) circuit or other test vector generation or storage circuit can be transferred to test die 2902 and shared by each of a plurality of test dies 2010. The test die 2010 can then simply include a formatter, driver, and timing generator for the pattern provided by the test die 2902. This eliminates the need to duplicate the APG circuit on each test die 2010.

  Test die 2902 can simultaneously support all test dies 2010 by simultaneously providing a common test pattern to each of test dies 2010, and test die 2902 can be connected to one or more of test dies 2011. On the other hand, it is possible to perform integration functions and selectively (eg continuously) to provide tests or patterns.

  The design methodology described above can determine when it is advantageous to split the test circuit into one or more test dies. For example, if a relatively large circuit (such as APG) can be shared by two or more test dies, the circuit can be transferred to a shared test die 2902 to reduce the die size of each test die 2010.

  FIG. 30 shows a test assembly 3000 that includes a shared test die 2902. In this embodiment, each test die 2010 is dedicated to each corresponding product die 2011 and provides a different test for each product die. However, test die 2902 can be used simultaneously or in an integrated manner to provide test die 3002 with a shared test or test pattern for use by each of product dies 2011.

  The embodiment shown in FIGS. 21-28 directly connects (via contact structures 2018, 2020) one or more test dies and one or more product dies designed in accordance with the design methodology described above. Is to be electrically connected. FIG. 31 shows a test assembly 3100 that performs a wafer level sort test of product die 3111 with test die 3104. Test die 3104 is indirectly electrically connected to product die 3110 via contacts 3108 and interconnect substrate 3106. Contact 3108 may be an epoxy ring probe card, a membrane probe card, or any other type of probe card assembly, such as those provided by FormFactor, Inc. (Livermore, CA) and Wentworth Laboratories (Bookfield, CT) It can be any type of probe card.

  Test die 3104 may be one or more test dies such as test die 400 of FIG. 4 generated by the design methodology described above. Product die 3111 may be one or more product dies, such as product die 300 of FIG. 3, also generated by the design methodology described above. Product die 3111 is formed on a wafer 3110 that can include other product dies 3111. The wafer 3110 can be placed on a suitable support structure such as a vacuum chunk (not shown). Product die 3111 also includes a bonding pad 3114 for receiving contact element 3112 and a special contact pad 3116. Contact element 3112 can include a cantilevered probe needle, a membrane probe card contact ball, a spring contact element as described above, or any other electrical contact element.

  Interconnect substrate 3106 provides an electrical interconnection between test die 3104 and contact 3108. As shown in FIG. 31, test die 3104 can be placed on top 3120 of substrate 3106. Alternatively, the test die 3104 can be placed on the lower portion 3122 of the substrate 3106. In yet another embodiment, the test die 3104 can be placed directly on the contact 3108.

  In order to electrically connect the test die 3104 to two or more product dies 3111, the interconnect substrate 3106 can include sufficient routing, and the contact 3108 includes a sufficient number of contact elements 3112. It is possible to include. For example, the entire product die wafer can be tested simultaneously by one or more test dies.

  In one embodiment, test die 3104 can be mounted on substrate 3106 and its bonding pads and special contact pads can be bonded out to substrate 3106, or first packaged in a suitable semiconductor package and then the substrate. Electrical connection to 3106 is possible.

  The substrate 3106 also provides structural support for the test die 3104 and contacts 3108. The substrate 3106 can be one or more PCBs that perform electrical interconnection and support functions and is attached to a structure (eg, a wafer prober or chuck not shown) that supports the wafer 3110. Is possible.

  Host 3102 communicates with test die 3104. The host 3102 sends a signal to start and stop the test, create a catalog of test results, display to the user, or send other test data to the test die 3104. Any type of host can be used, such as a personal computer, ATE, or any other control logic.

  FIG. 32 shows a test assembly 3200 that is one embodiment of the test assembly 3100, where the contact 3108 includes a probe card 3120. Test assembly 3200 includes a test head 3204 and a probe card assembly 3210. Probe card assembly 3213 includes an interconnect substrate 3106 (eg, a test load substrate), a test die 3104, and a probe card 3210. The test die 3104 can be placed on the underside of the substrate 3106 or on the probe card 3210 itself.

  The probe card 3210 is a cantilever or needle probe card that includes a cantilever probe 3220 that provides transmission and reception of signals to and from the product die 3111. Probe 3220 can be composed of any suitable conductive material including tungsten. As shown in the top view of probe card 3220 in FIG. 33, probe 3220 is connected to a contact pin or point 3304 that contacts a test circuit on test die 3104. Probe card 3210 can be secured to substrate 3106 via one or more securing pins 3302, screws, or other securing means.

  The probe 3220 is arranged to contact a special contact pad 3116 when the probe assembly 3213 is biased toward the product die 3111. In an alternative embodiment, a separate probe card is used to first test the product circuit by probing a special contact pad 3116 and then test the product die 3111 as a whole by probing the bonding pad 3114. Can be used.

  FIG. 34 shows another possible probing for probing one or more special contact pads 3116 and one or more bonding pads 3114 on the same probe card 3410. The embodiment of is shown. In this embodiment, the probe 3220 can send and receive signals to and from the special contact pad 3116 as many times as the probe 3218 sends and receives signals to and from the bonding pad 3114. It is. The probe 3118 is formed with a predetermined alignment corresponding to the alignment of the bonding pad 3114. As shown in the plan view of the probe card 3410 in FIG. 35, the probe 3118 forms a relatively rectangular shape that will contact the surrounding bonding pads 3114 on the product die 3111. In general, the probe 3120 is not arranged in the same predetermined alignment as the probe 3118 but extends into a region surrounded by the probe 3118 (and the bonding pad 3114). In alternative embodiments, the probe 1320 can be external to the region surrounded by the probe 3118 or can be placed in the same predetermined alignment as the probe 3118 and the bonding pad 3114. In another embodiment, the probe 3118 can be configured with a lead-on center arrangement or other predetermined arrangement to align with a similar arrangement of bonding pads 3114 on the product die 3111, and the probe 3120 Can be configured inside or outside the array of probes 3118 to align with corresponding special contact pads 3116. In yet another embodiment, the bonding pads 3114 and special contact pads 3116 can be configured in any other alignment.

  Probe card 3410 includes one or more contact pins 3502 that provide an electrical connection between substrate 3104 and probes 3218 and 3220. The test die 3104 can be placed on the probe card 3410 (as shown in FIG. 33) or can be placed outside the probe card 3410 (eg, on the substrate 3106), in this case The electrical connection is wired to pin 3502 or directly connected to interconnection point 3304.

  In the embodiment shown in FIGS. 32 through 35, the bonding pad 3114 and the special contact pad 3116 can have different heights. For example, the bonding pad 3114 can be higher (or lower) than the special contact pad 3116. In this embodiment, the probes 3118, 3120 can extend to different depths. That is, the probe 3120 can extend to a position lower than the probe 3118 so as to come into contact with the special contact pad 3116.

  FIG. 36 illustrates a test assembly 3600 that illustrates another embodiment of the test assembly 3100. The test assembly 3600 includes a test head 3204 and a probe card assembly 3613. Probe card assembly 3613 includes an interconnect substrate 3106, a test die 3104, and a membrane probe card 3610. Membrane probe card 3610 includes contact balls 3618 and 3620 that provide transmission and reception of signals between bonding pad 3114 and special contact pad 3116 when biased into contact with product die 3111. Contact balls or probes 3618, 3620 can be constructed from any suitable conductive material including solder.

  As shown in the plan view of the probe card 3610 of FIG. 37, the contact balls 3618 can be arranged in a grid array so as to contact the bonding pads 3114 arranged in the corresponding grid array pattern. The contact balls 3620 can be arranged in a predetermined grid array or can be interspersed in a grid array pattern as shown in FIG. 37 to match the special contact pads 3116 on the product die 3111. Is possible. Alternatively, as shown in FIG. 38, the contact balls 3618 can be arranged in a peripheral pattern to contact the bonding pads 3114 arranged in a corresponding peripheral pattern. The contact balls 3620 can be arranged outside of the peripheral pattern in a predetermined peripheral pattern or arranged in the peripheral pattern and aligned with the corresponding special contact pads 3116 as shown in FIG. In yet another embodiment, the contact balls 3618 can be arranged in a lead-on center arrangement to align with the lead-on center bonding pads on the product die 3110, and the contact balls 3620 have corresponding special contact pads. Can be placed inside or outside the read-on center array.

  In another embodiment, the contact ball 3620 can be replaced with the spring contact element described above. In this embodiment, special contact pads 3116 can be selectively placed in a grid array of bonding pads 3114 as shown in FIG. 11, and the addition of the special contact pads can result in a die of product die 3110. In order not to increase the size, it is possible to make it smaller than the size of the bonding pad 3114 as shown in FIG. In yet another embodiment, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

  Test die 3104 is electrically connected to one or more probes 3620 through substrate 3106. Test die 3104 is also electrically connected to one or more probes 3618 through substrate 3106. Alternatively, the test die 3104 can be placed directly on the probe card 3610 or can be placed at any other location in the test assembly 3600.

  Although FIGS. 36-38 illustrate that a single membrane probe card can be used to communicate with special contact pads 3116 and bonding pads 3114, in alternative embodiments, separate It is possible to probe special contact pads 3116 and bonding pads 3114 using a membrane probe card. That is, using one or more probe cards, only one or more special contact pads 3116 are first contacted with one or more contact balls 3618 and one or more of the product die 3111 It is possible to test the product circuit. Subsequently, one or more additional probe cards can be used to sequentially test the product die 3111 as a whole by bringing the bonding pad 3114 into contact with one or more contact balls 3220. is there. In yet another embodiment, multiple probe cards having a mix of contact balls 3618, 3620 can be used.

  In alternative embodiments, the bonding pad 3114 and the special contact pad 3116 can be of different heights. For example, the bonding pad 3114 can be higher (or lower) than the contact pad 3116. In this embodiment, the contact balls 3218, 3220 can have different heights. That is, the contact ball 3220 can extend to a position lower than the contact ball 3218 to make contact with the special contact pad 1516. Alternatively, other probe elements such as spring contact elements can be used to probe the shorter specialized contact pad 3116.

  FIG. 39 shows a test assembly 3900 that is another embodiment of a test assembly 3100 that includes a test head 3204 and a cobra-type probe card assembly 3913. The cobra type probe card assembly is available from Wentworth Laboratories (Brookfield CT.). The probe card assembly 3913 includes an interconnect substrate 3106, a space transducer (wired or ceramic) 3908, and a head assembly 3907. The head assembly 3907 includes an upper plate 3909, a spacer 3910, a lower plate 3911, a test die 3104, and cobra probes 3918 and 3920. When biased toward the product die 3111, the probes 3918 and 3920 provide transmission and reception of signals between the bonding pad 3114 and the special contact pad 3116, respectively.

  Test die 3104 is electrically connected to one or more probes 3920 and also electrically connected to one or more probes 3918. The test die 3104 can be placed on the underside of the upper die 3909, on the upper side 3902 of the lower plate 3911, on the interconnect substrate 3106, or at any other location on the test assembly 3900 as shown in FIG. is there.

  Probes 3918 are typically formed in a grid array and contact bonding pads 3914 arranged in a corresponding grid array pattern. Probes 3920 can be aligned to a predetermined grid array and connected to special contact pads 1816 outside the grid array pattern or dispersed within the grid array pattern as shown in FIG. Alternatively, as shown in FIG. 41, the probes 3918 are arranged in a peripheral pattern so that the probes 3918 contact bonding pads 3114 arranged on the product die 3111 in a corresponding peripheral pattern. Is possible. The probe 3920 can be probed with a predetermined peripheral pattern, outside the peripheral pattern, or aligned within the peripheral pattern as shown in FIG. In yet another embodiment, the probes 3918 can be arranged in a lead-on center array and aligned with the lead-on center bonding pads on the product die 3111, and the probe 3920 can be internal to the lead-on center array or It can be aligned externally and aligned with a corresponding special contact pad. In yet another embodiment, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

  Although FIGS. 39-41 illustrate that a single probe card assembly can be used to communicate with special contact pads 3116 and bonding pads 3114, in an alternative embodiment, separate It is possible to probe special contact pads 3116 and bonding pads 3114 using the probe card. That is, using one or more probe cards, first test only the special contact pad 3116 with one or more probes 3920 to test the associated product circuit of the product die 3111. Is possible. Subsequently, one or more additional probe cards can be used to sequentially test the product die 3111 with the bonding pad 3114 sequentially contacting one or more probes 3918. . In yet another embodiment, multiple probe card assemblies having a mix of probes 3918, 3920 can be used.

  In an alternative embodiment, the bonding pad 3114 and the special contact pad 3116 can be of different heights. For example, the bonding pad 3114 can be higher (or lower) than the contact pad 3116. In this embodiment, the probes 3918, 3920 can extend to different depths (or have different heights). That is, the probe 3920 can extend to a position lower than the probe 3918 to make contact with the special contact pad 3116.

  FIG. 42 shows a test assembly 4200, another embodiment of a test assembly 3100, including a test head 3204 and a probe card assembly 4213 (eg, provided by FormFactor, Inc. (Livermore, Calif.)). One embodiment of the probe card assembly 4213 is disclosed in PCT International Application No. WO96 / 38858. Probe card assembly 4213 includes a probe card 4204, an interposer 4206, a space transducer 4210, and spring contact elements 4218, 4220. When biased toward the product die 3111, the spring contact elements 4218, 4220 provide transmission and reception of signals to and from the bonding pad 3114 and special contact pad 3116, respectively.

  Test die 3104 is electrically connected to one or more probes 4220 and electrically connected to one or more probes 4218. The interconnection is made by a probe card 4204, intervening means 4206, or space converter 4210. The test die 3104 can be placed underneath the intervening means 4206 as shown in FIG. 42 and can be placed on the space transducer 4210, on the probe card 4204, or any other location on the test assembly 4200. It is possible.

  Spring contact elements 4218 are provided in a predetermined arrangement to provide transmission and reception of signals to and from the corresponding bonding pads 3114. In one embodiment, the probes 4218 are arranged in a grid array pattern. The spring contact elements 4220 can be aligned with the corresponding special contact pads 3116 in alignment with a predetermined grid array and distributed outside or within the grid array pattern. In another embodiment, the spring contact elements 4218 can be arranged in a peripheral pattern. The spring contact elements 4220 can be aligned with corresponding special contact pads 3116 in an area surrounded by a predetermined peripheral pattern, outside the peripheral pattern, or distributed in the peripheral pattern. . In yet another embodiment, the spring contact elements 4218 can be arranged in a lead-on center arrangement, and the spring contact elements 4220 can be arranged inside or outside the lead-on center arrangement to align with corresponding special contact pads. is there. In yet another embodiment, the bonding pads 3114 and special contact pads 3116 can be arranged in any other alignment.

  Although FIG. 42 illustrates that a single probe card assembly can be used to communicate with special contact pads 3116 and bonding pads 3114, in an alternative embodiment, a separate probe card The assembly (or probe card) can be used to probe special contact pads 3116 and bonding pads 3114. That is, using one or more probe card assemblies, only one or two of the product dies 3111 are initially contacted with only one special contact pad 3116 with one or more spring contact elements 4220. It is possible to test the above product circuit. Subsequently, one or more additional probe card assemblies can be used to contact the bonding pad 3114 with one or more spring contact elements 4218 to test the product die 3111 as a whole. It is. In yet another embodiment, multiple probe card assemblies having a mixture of spring contact elements 4218, 4220 can be used.

  In an alternative embodiment, the bonding pad 3114 and the special contact pad 3116 can be of different heights. For example, the bonding pad 3114 can be higher (or lower) than the special contact pad 3116. In this embodiment, the probes 4218, 4220 can extend to different depths (or have different heights). That is, the probe 4220 can extend to a position lower than the probe 4218 to make contact with the special contact pad 3116.

  In an alternative embodiment, the spring contact elements 4218, 4220 can be attached to bonding pads 3114 and special contact pads 3116 on the product die 3111. In this embodiment, the space converter 4210 can include a pad for making contact with the spring contact elements 4218, 4220. In yet another embodiment, some of the spring contact elements 4218 or 4220 can be attached to the space transducer 4210 and another some of the spring contact elements 4218 or 4220 can be attached to the product die 3111.

  Product dies generated by the design methodology described above can also be inserted into sockets and tested with test dies. The product die can be packaged into any known package for a semiconductor integrated circuit and may not be packaged (eg, a chip-scale configuration). Any common known socket can be used to support the product die. The test die can be attached to the printed circuit board and can be in direct contact with the product die (eg, via a spring contact element, etc.) or can be contacted to the product die via a contactor, edge connector, etc. Indirect contact is also possible.

  FIG. 46 shows a solder-down (surface mount) for mounting to a printed circuit board (PCB) 4610 and for crimping the bonding pads 4612 and special contact pads 4614 of the LGA package 4604. ) Shows an embodiment of an LGA socket 4600. The LGA package 4604 can include a product die designed according to the design methodology described above. As used herein, the term “socket” means an electrical component having an interconnection element suitable for making an electrical connection with a terminal or connection point of another electrical component. Yes. The socket shown in FIG. 46 is intended to allow a semiconductor package to be detachably connected to a circuit board. Another embodiment of a socket 4600 is disclosed in commonly assigned US Pat. No. 7,772,451.

  The PCB 4610 has a plurality of terminals or pads 4618, and the package 4604 has a plurality of bonding pads 4612 and special contact pads 4614. Socket 4600 provides a means for electrically interconnecting terminals 4618 to pads 4612 and 4614. A test circuit provided on the PCB 4610 or in a state of being able to communicate with the PCB 4610 can provide a signal to the pads 4612 and 4614 via the socket 4600 or monitor a signal from the pads 4612 and 4614. It is. For example, programmable circuitry within package 4604 can be programmed or monitored via spring contact element 4616, special contact pad 4614, and / or pad 4612.

  The socket 4600 includes a support substrate 4608 formed, for example, from a conventional PCB material. The support substrate 4608 includes a spring contact element 4616 formed on the top surface and a pad 4622 formed on the bottom surface. The spring contact element 4616 is for the package 4604 to contact the pads 4612 and 4614 of the package 4604 when biased downward by the force applied to the upper side of the package 4604 by the holding means 4602. In addition to the spring contact element, other contact elements can also be used. Support substrate 4608 also includes conductive means 4624 that provides an electrical interconnection between spring contact element 4616 and pad 4622. In an alternative embodiment, spring contact element 4616 can be connected directly to terminal 4618.

  A contact ball (such as a conventional solder ball) is disposed on the bottom surface of the pad 4622. The contact ball 4622 functions as a contact structure disposed on the bottom surface of the support substrate 4608 so as to contact a corresponding pad or terminal 4618 on the PCB 4610. Other electrical contact structures can also be used.

  Socket 4600 also includes a frame 4606 attached to PCB 4602. The frame 4606 includes lands 4626 for supporting the package 4604. Socket 4600 also includes retaining means 4602 disposed on frame 4626 and package 4604. The retaining means 4602 retains the package 4604 on the lands 4626 so that the spring contact element 4616 remains in electrical contact with the pads 4612 and 4614. Any other suitable mechanical means can be used for the holding means 4602, for example a spring clip.

  FIG. 47 illustrates another embodiment of a socket 4600 in which a test die 4630 is disposed on a PCB 4610. The test die 4630 can be designed according to the design methodology described above. Terminals or pads 4618 can be formed on the test die 4630 to provide an electrical interface with the contact ball 4620. In another embodiment, the spring contact element 4616 can be connected directly to the terminal 4618.

  Additionally and / or alternatively, one or more spring contact elements 4616 can be attached to the pads 4612 and 4614. In this embodiment, the spring contact element can be in contact with a pad or terminal on the upper side 4632 of the support substrate 4608, or the spring contact element can be in direct contact with the terminal 4618. .

  Although the invention has been described above with reference to specific exemplary embodiments thereof, various modifications and changes can be made to the embodiments without departing from the broad spirit and scope of the invention. It is clear. Accordingly, the specification and drawings are to be regarded as illustrative of the invention and not as restrictive.

1 is a design methodology for designing products and test dies according to one embodiment of the present invention. 1 is a block diagram of an integrated product and test circuit design according to one embodiment of the present invention. FIG. FIG. 3 is a block diagram of a product die generated after splitting the integrated design of FIG. FIG. 3 is a block diagram of a test die generated after splitting the integrated design of FIG. 1 is a block diagram of an embodiment of a test circuit in a test die. FIG. 6 is a design methodology for the design of products and test circuits according to another embodiment of the invention. 2 is one embodiment of a process for determining product and test circuit partitioning. 6 is a design methodology for designing products and test circuits according to yet another embodiment of the present invention. FIG. 9 is a block diagram of one embodiment of a computer system capable of implementing the processes of FIGS. 1 and 6-8. FIG. 4 is a logic diagram of one embodiment of a special contact pad coupled to an internal circuit node via a bidirectional buffer. FIG. 5 is a plan view of an embodiment of an integrated circuit having bonding pads aligned to a grid pattern, special contact pads not aligned to the grid pattern, and special contact pads aligned to the grid pattern. It is sectional drawing which looked at the special contact pad arrange | positioned between two bonding pads which have a contact ball from the side. 1 is a plan view of one embodiment of an integrated circuit having a lead on center bonding pad, an internal circuit, and a special contact pad for testing the internal circuit. FIG. FIG. 2 is a block diagram of one embodiment of a sequential circuit and a special contact pad for testing the sequential circuit. FIG. 17 is a circuit diagram of an embodiment of the switch of FIG. 16. FIG. 6 is a block diagram of one embodiment using special contact pads to isolate defective circuit blocks and enable redundant circuit blocks. FIG. 6 is a block diagram of another embodiment that uses special contact pads to isolate defective circuit blocks and enable redundant circuit blocks. FIG. 6 is a block diagram of one embodiment using a special contact pad to enable a test circuit or provide a stimulus. FIG. 6 is a block diagram of one embodiment using a special contact pad to provide control signals to the scanning circuit. FIG. 3 is a cross-sectional view of a test assembly for testing a product die as viewed from the side. It is sectional drawing which looked at the test assembly for testing many product die on a test wafer from the side. FIG. 3 is a side view of a test assembly including a spring contact element attached to a product die. FIG. 4 is another embodiment of a test assembly in which the spring contact elements, bonding pads, and special contact pads have different heights. It is sectional drawing which looked at one Embodiment of the spring contact element from the side. FIG. 25 is a perspective view of an embodiment of a contact tip structure and pyramidal contact shape of the spring contact element of FIG. 24. FIG. 26 is a perspective view of an embodiment of the pyramidal contact tip structure of FIG. 25. 1 is a side cross-sectional view of one embodiment of a test assembly including multiple test dies for testing a single product die. FIG. 1 is a side cross-sectional view of one embodiment of a test assembly that includes a single test die for testing multiple product dies. FIG. FIG. 4 is a side cross-sectional view of one embodiment of a test assembly including one test die shared by other test dies. FIG. 5 is a side cross-sectional view of another embodiment of a test assembly including one test die shared by other test dies. 1 is a side cross-sectional view of one embodiment of a test assembly that includes a test die, a contactor, and a product die. FIG. 1 is a side cross-sectional view of one embodiment of a test assembly having a probe card with a test die and a cantilever probe for probing a special contact pad of a product die. FIG. It is a top view of the probe card of FIG. FIG. 4 is a side cross-sectional view of another embodiment of a test assembly having a test die and a probe card having a cantilevered probe for probing a product die bonding pad and a special contact pad. It is a top view of the probe card of FIG. FIG. 5 is a side cross-sectional view of another embodiment of a test assembly having a membrane probe card with contacts for probing a product die bonding pad and special contact pads. FIG. 37 is a plan view of the membrane probe card of FIG. 36 having contact balls aligned with the grid pattern and contact balls not aligned with the grid pattern. FIG. 37 is a plan view of the membrane probe card of FIG. 36 having contact balls aligned with the peripheral pattern and contact balls not aligned with the peripheral pattern. FIG. 7 is a side cross-sectional view of another embodiment of a test assembly having a cobra probe card assembly having probes for probing product die bonding pads and special contact pads. FIG. 40 is a plan view of the tip of the cobra probe of FIG. 39 having a plurality of tips aligned with the grid pattern and other tips not aligned with the grid pattern. FIG. 40 is a plan view of the tip of the cobra probe of FIG. 39 having a plurality of tips aligned with the peripheral pattern and other tips not aligned with the peripheral pattern. FIG. 5 is a side cross-sectional view of another embodiment of a probe card assembly having spring contact elements for probing product die bonding pads and special contact pads. It is sectional drawing which looked at another embodiment of the spring contact element from the side. FIG. 43B is a perspective view of the spring contact element of FIG. 43A. FIG. 6 is a perspective view of another embodiment of a spring contact element. FIG. 44B is a cross-sectional view of the spring contact element of FIG. 44A viewed from the side. FIG. 6 is a perspective view of another embodiment of a tip structure for a spring contact element. FIG. 3 is a side cross-sectional view of one embodiment of a socket for holding a package having special contacts and conventional input, output, and input / output pins. , FIG. 6 is a side view of another embodiment of a socket including a test die on a printed circuit board.

Claims (49)

A substrate having a surface;
A plurality of first probe elements configured to contact a plurality of first type contact pads disposed at a plurality of first predetermined locations on the integrated circuit and disposed on the substrate; A plurality of first probe elements each having a contact portion disposed at a first distance perpendicular to the surface from the surface of the substrate;
A plurality of second probe elements configured to contact a plurality of second type contact pads disposed at a plurality of second predetermined positions on the integrated circuit and disposed on the substrate A plurality of second probe elements each having a contact portion disposed at a second distance perpendicular to the surface of the substrate from the surface of the substrate;
Each of the first type contact pads extends higher from the surface of the integrated circuit than each of the second type contact pads, and the second distance correspondingly corresponds to the first distance. Probe card characterized by being larger than.   2. The probe card according to claim 1, wherein the first and second probe elements are cantilever probes.   The probe card according to claim 1, wherein the first and second probe elements are contact balls.   The probe card according to claim 1, wherein the first probe elements are arranged in a first predetermined arrangement, and the second probe elements are arranged in a second predetermined arrangement.   The probe card according to claim 4, wherein the first predetermined arrangement is a grid pattern.   The probe card according to claim 4, wherein the first predetermined array has a rectangular pattern.   The probe card according to claim 4, wherein the first and second probe elements are spring contact elements.   The probe card according to claim 7, wherein the spring contact element includes a pyramidal tip contact structure.   The probe card according to claim 4, wherein the first and second probe elements are cobra probes.   The probe card according to claim 1, wherein each of the contact portions of the first probe elements and each of the contact portions of the second probe elements has a blade-type tip contact structure. A substrate having a surface;
A plurality of first probe means for contacting a first type contact pad of an integrated circuit, arranged in a first predetermined pattern on the substrate, each perpendicular to the surface from the surface of the substrate A plurality of first probe means having contact portions disposed at a first distance apart from each other;
A plurality of second probe means in contact with a second type contact pad of the integrated circuit, each being arranged in a second predetermined pattern on the substrate, each from the surface of the substrate to the substrate; A plurality of second probe means having contact portions disposed at a second distance perpendicular to the surface;
Each of the first type contact pads extends higher from the surface of the integrated circuit than each of the second type contact pads, and the second distance correspondingly corresponds to the first distance. Probe card characterized by being larger than.   12. The probe card according to claim 11, wherein the first probe means and the second probe means are cantilever probes.   The probe card according to claim 11, wherein the first probe means and the second probe means are contact balls.   The probe according to claim 11, wherein the first probe means is arranged in a first arrangement, the second probe means is arranged in a second arrangement, and the first arrangement is different from the second arrangement. card.   The probe card according to claim 14, wherein the first array is a grid pattern.   The probe card according to claim 14, wherein the first array has a rectangular pattern.   The probe card according to claim 14, wherein the first probe means and the second probe means are spring contact elements.   The probe card according to claim 17, wherein the spring contact element includes a pyramidal tip contact structure.   The probe card according to claim 11, wherein the first probe means and the second probe means are cobra type probes.   The probe card according to claim 11, wherein the first probe means and the second probe means include needle probes.   The probe card according to claim 11, wherein the first probe means and the second probe means have an elastic structure.   12. The probe card of claim 11, wherein the first type of contact pad is larger than the second type of contact pad.   The probe card according to claim 11, wherein the first type contact pad is larger in the contact area than the second type contact pad.   12. The probe card of claim 11, wherein the first type of contact pad is suitable for bonding to an integrated circuit package, and the second type of contact pad is not suitable for bonding to an integrated circuit package.   12. The probe card of claim 11, wherein the first type of contact pad is bonded to an integrated circuit package, and the second type of contact pad is not bonded to the integrated circuit package.   The probe card according to claim 11, wherein each of the contact portions of the first probe means and each of the contact portions of the second probe means has a blade-type tip contact structure. A method for testing an integrated circuit comprising:
Contacting a plurality of bonding pads disposed on the integrated circuit; the bonding pads are electrically connected to a plurality of input / output drivers on the integrated circuit; and the input / output drivers are connected to the integrated circuit. Electrically connected to the internal circuit formed above,
Contacting a special contact pad disposed on the integrated circuit, and the special contact pad is electrically connected directly to the internal circuit;
Providing test data to the internal circuit via one of the bonding pads and a corresponding one of the input / output drivers; the internal circuit processes the test data to generate response data;
Detecting the response data at one of the bonding pads; and the response data is provided from the internal circuit to the bonding pad to a corresponding one of the input / output drivers;
Monitoring the processing of the test data by the internal circuit at the special contact pad.   28. The method of claim 27, wherein the monitoring includes monitoring a state of a node of the internal circuit.   28. The method of claim 27, wherein the internal circuit comprises a plurality of sub-circuits.   30. The method of claim 29, wherein the monitoring step includes monitoring a signal between the plurality of sub-circuits.   30. The method of claim 29, wherein the plurality of sub-circuits comprise a memory and an input / output interface, and the input / output interface interfaces between the input / output driver and the memory.   32. The method of claim 31, wherein the monitoring step monitors a signal between the memory and the input / output interface.   32. The method of claim 31, wherein the monitoring step monitors signals between the input / output interface and the input / output driver. Further comprising contacting a plurality of said special contact pads, said monitoring step comprising:
A plurality of nodes in the internal circuit;
A plurality of signals between the memory and the input / output interface;
32. The method of claim 31, comprising monitoring a plurality of signals between the input / output interface and the input / output driver. A method for testing an integrated circuit comprising:
Contacting a plurality of bonding pads disposed on the integrated circuit; the bonding pads are electrically connected to a plurality of input / output drivers on the integrated circuit; and the input / output drivers are connected to the integrated circuit. Electrically connected to the internal circuit formed above,
Contacting a special contact pad disposed on the integrated circuit, and the special contact pad is electrically connected directly to the internal circuit;
Providing test data directly to the internal circuit via the special contact pad; the internal circuit processes the test data to generate response data;
Detecting the response data at one of the bonding pads, and the response data being brought from the internal circuit to the bonding pad to a corresponding one of the input / output drivers.   36. The method of claim 35, further comprising contacting a plurality of the special contact pads.   37. The method of claim 36, further comprising monitoring the processing of the test data by the internal circuit at at least one of the plurality of special contact pads. The internal circuit includes a memory and an input / output interface;
The test data includes an address of a location in the memory;
The processing includes providing data stored at the location on one of the input / output bonding pads via a corresponding one of the input / output interface and the input / output driver. Item 36. The method according to Item 35. A method of testing an integrated circuit, the integrated circuit comprising an internal circuit, a plurality of bonding pads that provide electrical connection to elements external to the integrated circuit, and between the internal circuit and the plurality of bonding pads. Including multiple input / output drivers that provide electrical connection of
Contacting a plurality of special contact pads disposed on the integrated circuit; and the special contact pads are directly electrically connected to a first sub-circuit constituting the integrated circuit;
Providing test data on the integrated circuit; and the internal circuit processes the test data to generate response data;
In the special contact pad, based on the monitoring of the processing of the test data by the internal circuit and determining whether the first sub-circuit is functioning as expected And consist of
A method of operating a redundant sub-circuit when the first sub-circuit is not functioning as expected, and that the redundant sub-circuit replaces the first sub-circuit of the internal circuit.   40. The method of claim 39, wherein the step of operating the redundant sub-circuit comprises switching a multiplexer of the internal circuit.   40. The method of claim 39, wherein the step of activating the redundant sub-circuit comprises disconnecting the first sub-circuit from the internal circuit.   The step of disconnecting the first sub-circuit from the internal circuit includes the step of disconnecting at least one fuse that internally connects the first sub-circuit to at least one of the other sub-circuits constituting the internal circuit. 42. The method of claim 41.   40. The method of claim 39, wherein the step of activating the redundant subcircuit includes providing a control signal via a special contact pad on the integrated circuit.   40. The method of claim 39, wherein providing the test data to the internal circuit comprises providing the test data via at least one of the bonding pads.   40. The method of claim 39, wherein providing the test data to the internal circuit comprises providing the test data via a special contact pad that is directly electrically connected to the internal circuit.   46. The method of claim 45, further wherein the step of providing test data to the internal circuit comprises providing the test data via a plurality of other special contact pads that are electrically connected directly to the internal circuit. The contacting step comprises contacting a plurality of the special contact pads;
40. The method of claim 39, wherein the step of monitoring further comprises the step of monitoring at at least two of the plurality of special contact pads. The internal circuit further includes a memory;
40. The method of claim 39, wherein each of the first subcircuit and the redundant subcircuit comprises an input / output interface that provides an interface between the memory and the input / output driver. The monitoring step further comprises:
Monitoring data input from the memory to the first sub-circuit;
49. monitoring data output from the first sub-circuit to the input / output driver.

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