JP2002530735A5 - - Google Patents

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Publication number
JP2002530735A5
JP2002530735A5 JP2000582883A JP2000582883A JP2002530735A5 JP 2002530735 A5 JP2002530735 A5 JP 2002530735A5 JP 2000582883 A JP2000582883 A JP 2000582883A JP 2000582883 A JP2000582883 A JP 2000582883A JP 2002530735 A5 JP2002530735 A5 JP 2002530735A5
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JP
Japan
Prior art keywords
job
signal
queue
processing
execution
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JP2000582883A
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English (en)
Japanese (ja)
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JP4608099B2 (ja
JP2002530735A (ja
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Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Priority claimed from SE9901145A external-priority patent/SE9901145D0/xx
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Publication of JP2002530735A publication Critical patent/JP2002530735A/ja
Publication of JP2002530735A5 publication Critical patent/JP2002530735A5/ja
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Publication of JP4608099B2 publication Critical patent/JP4608099B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2000582883A 1998-11-16 1999-11-12 ジョブ信号を処理する多数の処理ユニットを有する処理システムにおけるジョブ信号処理方法および処理システム Expired - Fee Related JP4608099B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
SE9803901-9 1998-11-16
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9901145-4 1999-03-29
SE9901145A SE9901145D0 (sv) 1998-11-16 1999-03-29 A processing system and method
PCT/SE1999/002061 WO2000029940A1 (en) 1998-11-16 1999-11-12 Multiple job signals per processing unit in a multiprocessing system

Publications (3)

Publication Number Publication Date
JP2002530735A JP2002530735A (ja) 2002-09-17
JP2002530735A5 true JP2002530735A5 (https=) 2010-10-14
JP4608099B2 JP4608099B2 (ja) 2011-01-05

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ID=26663434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000582883A Expired - Fee Related JP4608099B2 (ja) 1998-11-16 1999-11-12 ジョブ信号を処理する多数の処理ユニットを有する処理システムにおけるジョブ信号処理方法および処理システム

Country Status (9)

Country Link
US (1) US6714961B1 (https=)
EP (1) EP1131701B1 (https=)
JP (1) JP4608099B2 (https=)
AU (1) AU1437000A (https=)
BR (1) BR9915383A (https=)
CA (1) CA2350924C (https=)
DE (1) DE69941998D1 (https=)
SE (1) SE9901145D0 (https=)
WO (1) WO2000029940A1 (https=)

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US7152232B2 (en) * 2001-07-16 2006-12-19 Sun Microsystems, Inc. Hardware message buffer for supporting inter-processor communication
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US7814218B1 (en) 2002-10-17 2010-10-12 Astute Networks, Inc. Multi-protocol and multi-format stateful processing
US7596621B1 (en) * 2002-10-17 2009-09-29 Astute Networks, Inc. System and method for managing shared state using multiple programmed processors
US8151278B1 (en) 2002-10-17 2012-04-03 Astute Networks, Inc. System and method for timer management in a stateful protocol processing system
DE102006006582B4 (de) * 2006-02-13 2009-06-10 Jenoptik Laser, Optik, Systeme Gmbh Laser und Verfahren zur Erzeugung gepulster Laserstrahlung
US8156493B2 (en) * 2006-04-12 2012-04-10 The Mathworks, Inc. Exception handling in a concurrent computing process
KR20120017294A (ko) 2010-08-18 2012-02-28 삼성전자주식회사 어플리케이션을 효율적으로 처리하는 스케쥴링 시스템 및 스케쥴링 방법
US9329915B1 (en) * 2012-05-08 2016-05-03 Amazon Technologies, Inc. System and method for testing in a production environment
KR101476789B1 (ko) * 2013-05-06 2014-12-26 (주)넥셀 프로세싱 장치 및 방법
US9455887B1 (en) 2013-08-14 2016-09-27 Amazon Technologies, Inc. Distributed performance evaluation framework
CN104516773B (zh) * 2013-09-29 2018-04-20 国际商业机器公司 用于物理机的数据分配方法和数据分配装置
US9465653B2 (en) * 2013-12-11 2016-10-11 Dropbox, Inc. Automated invalidation of job output data in a job-processing system
US10372492B2 (en) 2013-12-11 2019-08-06 Dropbox, Inc. Job-processing systems and methods with inferred dependencies between jobs
US10133771B2 (en) 2015-05-13 2018-11-20 International Business Machines Corporation Opportunistic wait-triggered elastic commit

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SE454921B (sv) 1986-10-03 1988-06-06 Ellemtel Utvecklings Ab Sett och anordning for att i en pa forhand avgjord ordningsfoljd exekvera tva instuktionssekvenser
US5781753A (en) 1989-02-24 1998-07-14 Advanced Micro Devices, Inc. Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions
US5072364A (en) * 1989-05-24 1991-12-10 Tandem Computers Incorporated Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
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