JP2002518827A - Mosトランジスタを含む半導体デバイスの製造方法 - Google Patents

Mosトランジスタを含む半導体デバイスの製造方法

Info

Publication number
JP2002518827A
JP2002518827A JP2000553989A JP2000553989A JP2002518827A JP 2002518827 A JP2002518827 A JP 2002518827A JP 2000553989 A JP2000553989 A JP 2000553989A JP 2000553989 A JP2000553989 A JP 2000553989A JP 2002518827 A JP2002518827 A JP 2002518827A
Authority
JP
Japan
Prior art keywords
ion implantation
insulating film
gate electrode
semiconductor body
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000553989A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002518827A5 (https=
Inventor
ジュリアン、シュミッツ
ピエール、エイチ.ウォーリー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of JP2002518827A publication Critical patent/JP2002518827A/ja
Publication of JP2002518827A5 publication Critical patent/JP2002518827A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/40Ion implantation into wafers, substrates or parts of devices into insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/20Diffusion for doping of insulating layers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2000553989A 1998-06-11 1999-06-03 Mosトランジスタを含む半導体デバイスの製造方法 Pending JP2002518827A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP98201958 1998-06-11
EP98201958.0 1998-06-11
PCT/IB1999/001003 WO1999065070A2 (en) 1998-06-11 1999-06-03 Method of manufacturing a semiconductor device comprising a mos transistor

Publications (2)

Publication Number Publication Date
JP2002518827A true JP2002518827A (ja) 2002-06-25
JP2002518827A5 JP2002518827A5 (https=) 2006-06-08

Family

ID=8233800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000553989A Pending JP2002518827A (ja) 1998-06-11 1999-06-03 Mosトランジスタを含む半導体デバイスの製造方法

Country Status (4)

Country Link
US (1) US6303453B1 (https=)
EP (1) EP1036409A2 (https=)
JP (1) JP2002518827A (https=)
WO (1) WO1999065070A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW506080B (en) * 2001-02-16 2002-10-11 United Microelectronics Corp Manufacture method of deep sub-micro complementary metal oxide semiconductor with ultrashallow junction
EP1808885A1 (en) * 2002-06-26 2007-07-18 Semequip, Inc. A semiconductor device and method of fabricating a semiconductor device
AU2003261078A1 (en) 2002-06-26 2004-01-19 Semequip Inc. A semiconductor device and method of fabricating a semiconductor device
KR100480921B1 (ko) * 2003-07-24 2005-04-07 주식회사 하이닉스반도체 반도체 소자의 제조방법
WO2007070321A2 (en) 2005-12-09 2007-06-21 Semequip Inc. System and method for the manufacture of semiconductor devices by the implantation of carbon clusters
US7919402B2 (en) 2006-12-06 2011-04-05 Semequip, Inc. Cluster ion implantation for defect engineering
US9472628B2 (en) * 2014-07-14 2016-10-18 International Business Machines Corporation Heterogeneous source drain region and extension region
US11355342B2 (en) * 2019-06-13 2022-06-07 Nanya Technology Corporation Semiconductor device with reduced critical dimensions and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994027325A1 (en) * 1993-05-07 1994-11-24 Vlsi Technology, Inc. Integrated circuit structure and method
DE4415568C2 (de) * 1994-05-03 1996-03-07 Siemens Ag Herstellungsverfahren für MOSFETs mit LDD
US5457060A (en) * 1994-06-20 1995-10-10 Winbond Electronics Corporation Process for manufactuirng MOSFET having relatively shallow junction of doped region
US5518945A (en) * 1995-05-05 1996-05-21 International Business Machines Corporation Method of making a diffused lightly doped drain device with built in etch stop
US5702986A (en) * 1995-12-05 1997-12-30 Micron Technology, Inc. Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges
US5998272A (en) * 1996-11-12 1999-12-07 Advanced Micro Devices, Inc. Silicidation and deep source-drain formation prior to source-drain extension formation
KR100226758B1 (ko) * 1996-12-14 1999-10-15 구본준 씨모스펫 제조방법
US6087234A (en) * 1997-12-19 2000-07-11 Texas Instruments - Acer Incorporated Method of forming a self-aligned silicide MOSFET with an extended ultra-shallow S/D junction

Also Published As

Publication number Publication date
WO1999065070A3 (en) 2000-04-27
WO1999065070A2 (en) 1999-12-16
US6303453B1 (en) 2001-10-16
EP1036409A2 (en) 2000-09-20

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