JP2002368154A - Chip-size package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CSP which is configured easily and has high mounting characteristics and reliability. SOLUTION: In a chip-size package is made of a printed wiring board, and is provided with an interposer where a through-hole penetrating the front and rear surfaces and a conductor pattern electrically connected to the through-hole are formed, and sealing resin which protects a semiconductor chip mounted on the surface of the interposer, a solder resist is applied so as to cover only the conductor pattern which excludes a part electrically connected to the semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip size package using an interposer, and more particularly to a package having improved mountability, mounting reliability and reflow resistance.

[0002]

2. Description of the Related Art A chip size package using an interposer (hereinafter referred to as a CSP).
Is a ball grid array (Ba11 Grid Array or less, B
There is a land grid array (hereinafter referred to as LGA) that does not use solder balls. In each of the electrode structures, the electrodes are arranged in a matrix on the back surface of the interposer, and a quad flat package (QFP: Quad) in which the electrodes are taken out only from the previous four directions.
It can handle a large number of electrodes with an area smaller than that of the Flat Package). Therefore, the increase in the package size due to the increase in the number of pins is not remarkable, and the area ratio between the size of the semiconductor chip and the package size can be reduced.

[0003] In particular, the LGA does not use solder balls for connection to a mounting substrate, but uses a planar electrode called a land, and is therefore advantageous in terms of cost. Furthermore, a single-layer printed circuit board (Print Circ) is used as an interposer in LGA.
A device using a uit board (hereinafter referred to as a PCB) is less expensive than a device using a ceramic, and is hardly broken even when thinned, so that the package can be made thinner.

FIG. 7 is a side sectional view showing an example of an LG
Fig. 9 shows a type A CSP. In this figure, (a) is a side cross section, and (b) is a back surface, respectively, 1 is an interposer made of PCB, 2 is a semiconductor chip mounted on the interposer 1 by die bonding, 3 is a bonding wire, and 4 is a bonding wire. Sealing resin for covering the semiconductor chip, 6a and 6
b is a land, 7 is a die attach material for bonding the semiconductor chip 2, 8 is a solder resist, and 10 is a through hole penetrating the front and back surfaces of the interposer.

[0005] As shown in FIG.
Is mounted on the interposer 1, connects the semiconductor chip 2 and the land 6a by wire bonding, and is configured to be connectable to the land 6b on the back surface of the interposer 1 through a through hole 10 for conducting between the front surface and the back surface of the interposer. I have. In this example, an LGA is configured by arranging electrodes in a matrix. Therefore, the package size can be reduced despite the large number of pins.

Further, as shown in FIG. 1B, the solder resist 8 indicated by oblique lines is applied to the land 6 on the back surface of the interposer 1.
The structure is applied to portions other than b, and is further filled in the through hole 10. In addition, interposer 1
Has a similar configuration, and a solder resist 8 is applied to portions other than the lands 6a.

[0007]

However, since the sealing resin 4 is formed only on the surface on which the semiconductor chip 2 is mounted, the adhesion between the sealing resin 4 and the semiconductor chip 2 or between the sealing resin 4 and the interposer 1 is reduced. Not strong. Therefore, the moisture absorbed by the solder resist 8 and the sealing resin 4 before the mounting is explosively evaporated due to a temperature stress when the solder is mounted on a mounting substrate such as a motherboard, and the sealing resin 4 and the semiconductor chip are removed. 2 and the interface between the sealing resin 4 and the interposer 1 may cause peeling or cracking. The occurrence of peeling and cracking due to the absorbed water amount and thermal stress is classified into levels according to, for example, JEDEC standards. This standard item is called reflow resistance or moisture resistance, and most CSPs are at level 3. You cannot clear the highest level, Level 1.

In the package having the structure as shown in FIG. 7, the conductor pattern other than the land portion on the back surface of the interposer is covered with the solder resist.
b is arranged inside the solder resist 8. That is,
The land 6a has a concave shape, and it is clear that the mountability and mounting reliability on the mounting board are inferior to BGA. Therefore, if the amount of solder is small, the pattern on the mounting board and the land are not sufficiently connected. Conversely, if the amount of solder is increased, a solder bridge is likely to occur. This is because the gap between the mounting substrate and the land 6a depends on the thickness of the solder resist 8 with low precision, which is a major drawback in small electronic components such as CSP and precision electronic components. Would. SUMMARY OF THE INVENTION It is an object of the present invention to provide a CSP that can solve the above-mentioned problems, can be easily configured, and can improve the mountability and the mounting reliability.

[0009]

According to a first aspect of the present invention, there is provided a printed wiring board having a through hole penetrating through the front and back surfaces, and a through hole provided on the front surface and electrically connected to the through hole. In a chip size package including an interposer on which a conductor pattern is formed and a sealing resin for protecting a semiconductor chip mounted on the surface of the interposer, the conductor pattern excluding a portion for making an electrical connection with the semiconductor chip. , A solder resist is applied so as to cover only the surface portion and substantially all side portions.

[0010] With this configuration, the interposer base portion having the highest adhesion to the sealing resin is exposed, and the conductor pattern having the lowest adhesion is covered with a solder resist having higher adhesion, thereby encapsulating. The peel resistance of the resin can be improved.

According to a second aspect of the present invention, in the first aspect, the entire inside of the through hole is filled with a resin.

With this configuration, it is possible to prevent the solder resist and the sealing resin from flowing into the through holes.

According to a third aspect of the present invention, a plating pattern is formed on the resin exposed from the through hole opening on the back surface of the interposer of the second aspect, and a solder resist is not attached to the back surface of the interposer. It is.

With this configuration, the conductor pattern connecting the through hole and the electrode becomes unnecessary, and the solder resist for covering the conductor pattern and the through hole can be omitted. Further, since no solder resist having low thickness accuracy exists on the back surface of the interposer, a protruding land having sufficiently high stress absorption can be formed even with a plating pattern.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to examples and drawings. It is to be noted that the same or corresponding components are denoted by the same reference symbols throughout a plurality of drawings, and overlapping description will be avoided.

FIG. 1 shows an embodiment of the first invention, and FIG.
(A) shows the surface of the interposer, and FIG. 1 (b) shows a partial cross section of the side. In this figure, 1 indicates an interposer, 6a indicates a land, and 8 indicates a solder resist.

As shown in FIG. 1A, the solder resist 8 is applied so as to cover the conductor pattern including the land 6a and the opening of the through hole 10. However,
Although not shown in FIG. 2A, in this example, the semiconductor chip is mounted by die bonding and wire bonding, and therefore, as shown in FIG. The resist has been selectively removed.

The interposer 1 is a PCB similar to that of the conventional example, and is made of, for example, BT resin as a base material. The conductor pattern is formed by etching a copper foil applied on a PCB and patterning the copper foil or by a plating layer. Therefore, the adhesion with the sealing resin 4 made of epoxy resin or the like is determined by the base material of the interposer 1> the solder resist 8>
Strong in order of conductor pattern.

In this embodiment, the conductor pattern having the lowest adhesion to the sealing resin 4 is covered with the solder resist 8, and the base material of the interposer 1 having the highest adhesion is exposed. Will be. By doing so, adhesion to the sealing resin 4 is higher than before, and peeling and cracking can be prevented even if thermal stress is applied during mounting. The solder resist is applied so as to cover not only the surface of the conductor pattern but also substantially all side surfaces in consideration of printing accuracy.

FIG. 2 is a view showing one embodiment of the second invention, and shows an example in which a filling resin 5 is filled in a through hole 10. As shown in FIG. The filling resin 5 is formed, for example, by mixing a solvent with a thermosetting resin to have an appropriate fluidity, filling the through-hole plating with a screen printing method, heating and polishing the surface after heating. In this way, the filling resin 5
Is filled, so that even if a liquid resist is used in the step of forming the solder resist 8, it does not enter the through hole and flow out to the back surface of the interposer 1.
Also, in the resin sealing step of forming the sealing resin 4,
Since the resin does not pass through the through hole to the back surface, there is no burr. Further, as shown in the figure, the land 6a can be formed on the through-hole 10 by plating or the like so as to overlap, so that the conductor pattern portion on the surface of the interposer can be reduced. Especially effective.

Table 1 shows the values of N shown in FIGS. 3 (a) to 3 (c).
A total of 72 interposers, each having 24 solder resist patterns o, 1 to No, and 3 formed on the surface, were prepared, and a pass (Pass) was obtained when moisture absorption / reflow treatment was performed under JEDEC Level-1 conditions. And failed (Fai
l) The number of sheets is recorded. In FIG. 3,
Shaded portions indicate portions where the solder resist is applied.

[0022]

[Table 1]

As shown in this table, no rejected product was found in the interposer (No. 3, 3) according to the present invention, which was similar to the above-mentioned embodiment. In the case where two rejects were generated and solder resist was applied to the entire surface except for the conductor pattern (No.
In the case of 1), only two acceptable products were generated.

FIG. 4 shows an embodiment in which the third invention is applied to an LGA. FIG. 4 (a) shows an interposer surface, FIG. 4 (b) shows a side cross section, and FIG. 4 (c) shows a back surface. Are respectively shown. As shown in the figure, the filling resin 5 described above is filled in all of the through holes 10 formed in the interposer 1.
Lands 6a for stitch bonding on the surface of the interposer, and lands 6 for connecting the mounting substrate on the back surface.
b is formed. This land 6a and land 6b
Is a through hole 10 opening and a through hole filling resin 5
The through hole 10 is a so-called via hole (blind through hole) in which the hole is not visible. This can be obtained by forming the filling resin 5 as described in the embodiment of the second invention, plating the entire front and back surfaces of the PCB, and patterning the same by photolithography.

With such a configuration, the land and the through hole can be directly connected, and the conductor pattern for connecting the land and the through hole, which is required in the conventional example, becomes unnecessary. Particularly on the back surface of the interposer, it is not necessary to prevent the solder from adhering to the conductor pattern and the through-hole, so that a solder resist for covering these is not required. The land 6b made of a plating layer attached to the back surface of the interposer 1 can protrude at least about 0.1 mm from the surface of the base material of the interposer 1. Since a CSP having a small size sufficiently exhibits stress absorption performance, it can be used as an LGA land as it is. In the conventional configuration, if you try to project the land,
Since the exposed solder resist must be exposed to the part filled in the through hole, the solder resist filled in the through hole is removed more than necessary by development, so the sealing resin that has entered the through hole Is exposed on the back surface, causing a problem in appearance, but according to the present example, such a problem cannot occur.

Also, by eliminating the solder resist having low thickness accuracy from the entire back surface of the interposer 1, the problem of the solder bridge caused by the solder resist can be solved. As long as this is done, defects in mounting will also be suppressed.

FIG. 5 is a sectional view showing another embodiment of the third invention. In this figure, reference numeral 4a denotes an underfill for protecting a connection portion, 9 denotes a flip-chip bonding bump, and shows a configuration in which the semiconductor chip 2 is flip-chip bonded onto the interposer 1.

Even with the configuration shown in the drawing, the same effects as those described above can be obtained. That is, the same effect can be obtained by wire bonding, flip chip bonding, or another method regardless of the method of connecting the interposer and the semiconductor chip.

FIG. 6 shows an embodiment in which the third invention is applied to a BGA. FIG. 6 (a) is a side sectional view and FIG.
(B) shows the back surface respectively. In this figure, reference numeral 11 denotes a solder ball adhered on the land 6b.

Even with the configuration shown in the drawing, the same effects as those described above can be obtained. That is, regardless of the electrode structure,
Similar effects can be obtained with LGA or BGA.

[0031]

As described above, in the chip size package of the present invention, since the solder resist on the surface of the interposer is used only for covering the conductor pattern, the adhesiveness with the sealing resin can be improved. Does not cause interface delamination due to thermal stress during mounting.

Further, since the through-hole is filled with resin, there is no possibility that a material having fluidity enters the through-hole. That is,
Either a dry film resist or a liquid resist can be used, and resin sealing can be performed without using a mold.
In addition, an electrode for stitch bonding or flip-chip bonding can be provided directly above the through-hole, so a CSP having fine pitch electrodes with a simple configuration
Can be provided.

Further, since a plating pattern is formed on the resin exposed from the through-hole opening on the back surface of the interposer and no solder resist is applied on the back surface of the interposer, an electrode having sufficient stress absorbing performance can be formed even by plating. The mounting state is less affected by the amount of solder and the like than in the conventional configuration, so that the mountability and the mounting reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the first invention.

FIG. 2 is a plan view and a sectional view showing an embodiment of the second invention.

FIG. 3 is a plan view of a sample used for examining characteristics of the present invention.

FIG. 4 is a plan view and a sectional view showing an embodiment of the third invention.

FIG. 5 is a plan view and a cross-sectional view showing another embodiment of the third invention.

FIG. 6 is a plan view and a cross-sectional view showing still another embodiment of the third invention.

FIG. 7 is a diagram showing a conventional LGA-type CSP.

[Explanation of symbols]

1: interposer, 2: semiconductor chip, 3: bonding wire, 4: sealing resin, 4a: underfill resin, 5: through hole filling resin, 6: land, 6a: wiring, 7: die attach material, 8: solder Resist, 9: Bump for flip chip bonding, 10: Through hole, 11: Solder ball

Claims (3)

[Claims] An interposer comprising a printed wiring board, a through hole passing through the front and back surfaces, and a conductor pattern formed on the front surface and electrically connected to the through hole, and a semiconductor chip mounted on the interposer surface In a chip size package comprising a sealing resin for protecting the semiconductor pattern, a solder resist is applied so as to cover only a surface portion and substantially all side portions of the conductor pattern except for a portion for making an electrical connection with the semiconductor chip. A chip size package characterized by being made. 2. The chip size package according to claim 1, wherein the inside of the through hole is filled with a resin. 3. The chip according to claim 2, wherein a plating pattern is formed on the resin exposed from the through-hole opening on the back surface of the interposer, and a solder resist is not applied on the back surface of the interposer. Size package.