JP2002366431A - 特定用途向け集積回路の埋め込まれたメモリにアクセスする装置 - Google Patents

特定用途向け集積回路の埋め込まれたメモリにアクセスする装置

Info

Publication number
JP2002366431A
JP2002366431A JP2002141410A JP2002141410A JP2002366431A JP 2002366431 A JP2002366431 A JP 2002366431A JP 2002141410 A JP2002141410 A JP 2002141410A JP 2002141410 A JP2002141410 A JP 2002141410A JP 2002366431 A JP2002366431 A JP 2002366431A
Authority
JP
Japan
Prior art keywords
functional block
memory
access
embedded memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002141410A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002366431A5 (enExample
Inventor
Laura Elisabeth Simmons
ローラ・エリザベス・サイモンズ
Chancellor Archie
チャンセラー・アーチー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JP2002366431A publication Critical patent/JP2002366431A/ja
Publication of JP2002366431A5 publication Critical patent/JP2002366431A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
JP2002141410A 2001-05-29 2002-05-16 特定用途向け集積回路の埋め込まれたメモリにアクセスする装置 Withdrawn JP2002366431A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/867,957 2001-05-29
US09/867,957 US6622203B2 (en) 2001-05-29 2001-05-29 Embedded memory access method and system for application specific integrated circuits

Publications (2)

Publication Number Publication Date
JP2002366431A true JP2002366431A (ja) 2002-12-20
JP2002366431A5 JP2002366431A5 (enExample) 2005-09-22

Family

ID=25350795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002141410A Withdrawn JP2002366431A (ja) 2001-05-29 2002-05-16 特定用途向け集積回路の埋め込まれたメモリにアクセスする装置

Country Status (5)

Country Link
US (1) US6622203B2 (enExample)
EP (1) EP1262988A3 (enExample)
JP (1) JP2002366431A (enExample)
KR (1) KR100869938B1 (enExample)
TW (1) TW550565B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4054598B2 (ja) * 2002-04-25 2008-02-27 キヤノン株式会社 メモリ制御回路、ｄｍａ要求ブロック及びメモリアクセスシステム
US7346876B2 (en) * 2002-09-04 2008-03-18 Darien K. Wallace ASIC having dense mask-programmable portion and related system development method
US7202908B2 (en) * 2002-09-04 2007-04-10 Darien K. Wallace Deinterlacer using both low angle and high angle spatial interpolation
US7782398B2 (en) * 2002-09-04 2010-08-24 Chan Thomas M Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions
US7480010B2 (en) * 2002-09-04 2009-01-20 Denace Enterprise Co., L.L.C. Customizable ASIC with substantially non-customizable portion that supplies pixel data to a mask-programmable portion in multiple color space formats
US7516265B2 (en) * 2004-03-12 2009-04-07 Siemens Energy & Automation, Inc. System and method for providing an application with memory access methods
JP2006004079A (ja) * 2004-06-16 2006-01-05 Sony Corp 記憶装置
CN100377104C (zh) * 2005-02-28 2008-03-26 中国科学院计算技术研究所 一种内存访问信息实时捕获装置及访存信息捕获方法
CN117015963A (zh) 2021-01-06 2023-11-07 安法布里卡公司 用于异构和加速计算系统的输入/输出缩放的服务器结构适配器
CN118103824A (zh) * 2021-06-09 2024-05-28 安法布里卡公司 通过网络协议的透明远程存储器访问
WO2023019202A1 (en) 2021-08-11 2023-02-16 Enfabrica Corporation System and method for congestion control using a flow level transmit mechanism
US12248424B2 (en) 2022-08-09 2025-03-11 Enfabrica Corporation System and method for ghost bridging
US12417154B1 (en) 2025-01-22 2025-09-16 Enfabrica Corporation Input/output system interconnect redundancy and failover

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696935A (en) * 1992-07-16 1997-12-09 Intel Corporation Multiported cache and systems
JPH06314231A (ja) * 1993-04-28 1994-11-08 Hitachi Ltd 共用メモリアクセス制御方法
US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
JP4084428B2 (ja) * 1996-02-02 2008-04-30 富士通株式会社 半導体記憶装置
US5815167A (en) * 1996-06-27 1998-09-29 Intel Corporation Method and apparatus for providing concurrent access by a plurality of agents to a shared memory
US5996051A (en) * 1997-04-14 1999-11-30 Advanced Micro Devices, Inc. Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array
US6049856A (en) * 1997-05-27 2000-04-11 Unisys Corporation System for simultaneously accessing two portions of a shared memory
US6430654B1 (en) * 1998-01-21 2002-08-06 Sun Microsystems, Inc. Apparatus and method for distributed non-blocking multi-level cache

Also Published As

Publication number Publication date
EP1262988A3 (en) 2004-09-15
KR100869938B1 (ko) 2008-11-24
KR20020090907A (ko) 2002-12-05
EP1262988A2 (en) 2002-12-04
US20020184452A1 (en) 2002-12-05
US6622203B2 (en) 2003-09-16
TW550565B (en) 2003-09-01

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