JP2002334858A - Apparatus for polishing semiconductor wafer - Google Patents

Apparatus for polishing semiconductor wafer

Info

Publication number
JP2002334858A
JP2002334858A JP2001139468A JP2001139468A JP2002334858A JP 2002334858 A JP2002334858 A JP 2002334858A JP 2001139468 A JP2001139468 A JP 2001139468A JP 2001139468 A JP2001139468 A JP 2001139468A JP 2002334858 A JP2002334858 A JP 2002334858A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor substrate
electrodes
metal film
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001139468A
Other languages
Japanese (ja)
Inventor
Shinzo Uchiyama
信三 内山
Kazuo Takahashi
一雄 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2001139468A priority Critical patent/JP2002334858A/en
Publication of JP2002334858A publication Critical patent/JP2002334858A/en
Pending legal-status Critical Current

Links

Landscapes

  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Constituent Portions Of Griding Lathes, Driving, Sensing And Control (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an apparatus for polishing a semiconductor wafer in which an end-point detector for polishing, capable of simply and surely detecting the presence or absence of a metal film on a surface under polishing of a semiconductor wafer, is provided in a dual-damascene polishing removal process. SOLUTION: A plurality of electrodes 22 are arranged on a polishing head 6, which polishes a semiconductor wafer having a metal film containing copper or aluminum on a surface to be polished, where the distance between neighboring electrodes is longer than the chip width on the wafer. Through-holes 21 are arranged in the polishing pad 5, at positions that correspond to the electrodes 22. Presence or absence of the metal film on the scribe lines of he wafer is detected by an electrical signal processing means 24, by which a voltage is applied between electrodes to measure the resistance value between electrodes, and the end point of the polishing is determined knowing the status of the metal film on all over the wafer surface from the detected result. Since the presence or the absence of the metal film can be detected during the polishing, it is possible to remove the metal film by polishing and to keep adequate metal material in the wiring grooves of the wafer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウエハ等の
基板の研磨装置、特に研磨終点検出装置を備えた研磨装
置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing apparatus for a substrate such as a semiconductor wafer, and more particularly to a polishing apparatus provided with a polishing end point detecting device.

【0002】[0002]

【従来の技術】半導体デバイスの超微細化や多層配線化
が進み、Si、GaAs、InP等の半導体ウエハある
いは表面上に複数の島状の半導体領域が形成された石英
やガラス基板等の基板の外表面を高精度に平坦化するこ
とが求められている。さらに、SOIウエハの出現や3
次元集積化の必要性からも基板の外表面の平坦化が望ま
れている。
2. Description of the Related Art Semiconductor devices such as Si, GaAs, InP and the like or semiconductor substrates such as quartz or glass substrates having a plurality of island-shaped semiconductor regions formed on the surface thereof are becoming increasingly finer and multi-layered. It is required to flatten the outer surface with high precision. Furthermore, the emergence of SOI wafers and 3
From the necessity of three-dimensional integration, flattening of the outer surface of the substrate is desired.

【0003】このような基板の平坦化技術としては、化
学機械研磨(CMP)装置が従来から知られており、半
導体産業に広く利用されている。また、化学機械研磨
(CMP)は、デュアルダマシンプロセス(Dual damas
cene process)において、半導体ウエハ表面の金属層を
研磨除去するときにも応用されている。
As a technique for planarizing such a substrate, a chemical mechanical polishing (CMP) apparatus has been conventionally known, and is widely used in the semiconductor industry. Chemical mechanical polishing (CMP) is a dual damascene process (Dual damas
cene process), it is also applied when polishing and removing a metal layer on a semiconductor wafer surface.

【0004】次に、デュアルダマシンプロセスにおける
研磨について図8を参照して説明する。デュアルダマシ
ンプロセスにおいては、図8の(a)に示すように、半
導体ウエハ101上に絶縁膜102を成膜した後に、こ
の絶縁膜102に配線溝104とコンタクトホール10
3を形成し、そして、図8の(b)に示すように、この
配線溝104とコンタクトホール103に金属材料を埋
め込むように絶縁膜102の上に銅またはアルミニウム
を含む金属膜105を形成する。この金属膜105を形
成した半導体ウエハ101を化学機械研磨し、図8の
(c)に示すように、配線溝104からはみ出した絶縁
膜102上の金属膜105を全て除去する。このような
デュアルダマシンプロセスにおける研磨においては、絶
縁膜102上の金属膜を確実に除去し、かつ配線溝10
4内に金属材料を十分に残すことが重要である。
Next, polishing in a dual damascene process will be described with reference to FIG. In the dual damascene process, as shown in FIG. 8A, after an insulating film 102 is formed on a semiconductor wafer 101, a wiring groove 104 and a contact hole 10 are formed in the insulating film 102.
Then, as shown in FIG. 8B, a metal film 105 containing copper or aluminum is formed on the insulating film 102 so as to bury a metal material in the wiring groove 104 and the contact hole 103. . The semiconductor wafer 101 on which the metal film 105 is formed is chemically and mechanically polished, and as shown in FIG. 8C, all the metal film 105 on the insulating film 102 protruding from the wiring groove 104 is removed. In the polishing in such a dual damascene process, the metal film on the insulating film 102 is surely removed and the wiring groove 10 is removed.
It is important that a sufficient amount of the metal material is left in 4.

【0005】したがって、デュアルダマシンプロセスの
研磨に際しては、半導体ウエハ101の絶縁膜102上
の金属膜105の有無を絶えず測定し、絶縁膜102上
の金属膜105がなくなったときに、研磨を終了するこ
とが重要となる。
Therefore, in the polishing of the dual damascene process, the presence or absence of the metal film 105 on the insulating film 102 of the semiconductor wafer 101 is constantly measured, and the polishing is terminated when the metal film 105 on the insulating film 102 is gone. It becomes important.

【0006】そこで、従来は、レーザーあるいはその他
の光学的デバイスにより半導体ウエハ表面上の層の厚み
を測定し、研磨の終点を検出している。
Therefore, conventionally, the end point of polishing is detected by measuring the thickness of a layer on the surface of a semiconductor wafer by using a laser or other optical device.

【0007】また、内部に電極を埋め込んだ研磨パッド
を使用して、電極とウエハの被研磨面に設けられた終点
検出用の金属コンタクトとの間に流れる電流を測定する
ことにより、研磨中にウエハ表面上の層の厚みを検出す
るという技術も、米国特許第4793895号明細書等
に開示されている。
Further, by using a polishing pad having an electrode embedded therein and measuring a current flowing between the electrode and a metal contact for detecting an end point provided on the surface to be polished of the wafer, the polishing is performed during polishing. A technique for detecting the thickness of a layer on a wafer surface is also disclosed in U.S. Pat. No. 4,793,895.

【0008】この技術を図9を用いて説明すると、ウエ
ハ204の被研磨面に予め終点検出用の金属パターン2
05を設け、このウエハ204を、研磨面に陽電極20
2と陰電極203を埋め込んだ研磨パッド201により
研磨するように構成されており、これらの陽電極202
と陰電極203の間には直流電源206により電圧がか
けられ、研磨中に陽電極202と陰電極203が、ウエ
ハ204の金属パターン205と接触すると、ウエハ2
04の内部を介して電流が流れ、この電流値を例えばオ
シロスコープ207等で測定することにより、ウエハ2
04の被研磨面の層厚を検出している。
This technique will be described with reference to FIG. 9. Referring to FIG.
The positive electrode 20 is provided on the polished surface.
2 and a polishing pad 201 in which a negative electrode 203 is embedded.
A voltage is applied between the negative electrode 203 and the DC power source 206. When the positive electrode 202 and the negative electrode 203 come into contact with the metal pattern 205 of the wafer 204 during polishing, the wafer 2
A current flows through the inside of the wafer 2, for example, by measuring the current value with an oscilloscope 207 or the like.
The layer thickness of the polished surface No. 04 is detected.

【0009】[0009]

【発明が解決しようとする課題】しかしながら、前述し
た従来の研磨終点検出技術においては、以下に述べるよ
うな問題点があった。すなわち、レーザーあるいはその
他の光学的デバイスにより半導体ウエハ表面上の層の厚
みを測定して、研磨の終点を検出する技術では、機構上
の制約によりウエハの一部の情報によってのみ研磨の終
点を検出しており、研磨される全面を信頼性良く制御す
るためには十分な情報を得ることができないという問題
があり、また、ウエハ全面の情報を得ようとすると、機
構が複雑となり、コスト高となる問題点があった。
However, the above-mentioned conventional polishing end point detecting technique has the following problems. In other words, in the technology that measures the thickness of the layer on the semiconductor wafer surface using a laser or other optical device to detect the end point of polishing, the polishing end point is detected only based on partial information of the wafer due to mechanical limitations. Therefore, there is a problem that sufficient information cannot be obtained in order to control the entire surface to be polished with high reliability, and when trying to obtain information on the entire surface of the wafer, the mechanism becomes complicated and cost increases. There was a problem.

【0010】前記米国特許第4793895号明細書に
開示された技術の場合、ウエハと電極を接触させる必要
があり、研磨屑により接触不良になるという問題があ
り、また、終点検出用の金属パターンを予めウエハ上に
設けることが必要であり、そのための特別な工程を必要
とするという問題点があった。
In the case of the technique disclosed in the above-mentioned US Pat. No. 4,793,895, it is necessary to make the wafer and the electrode come into contact with each other, and there is a problem that a contact failure is caused by polishing debris, and a metal pattern for detecting an end point is formed. There is a problem in that it must be provided on a wafer in advance, and a special process for that is required.

【0011】そこで、本発明は、上記従来技術の有する
問題点や未解決な課題に鑑みてなされたものであって、
デュアルダマシンの研磨除去プロセスの際に、ウエハ等
の半導体基板の被研磨面の金属膜の有無の検出を簡易に
かつ確実に行なうことができる研磨終点検出装置を備え
た半導体基板の研磨装置を提供することを目的とするも
のである。
Therefore, the present invention has been made in view of the problems and unsolved problems of the above prior art,
Provided is a semiconductor substrate polishing apparatus provided with a polishing end point detection apparatus that can easily and reliably detect the presence or absence of a metal film on a surface to be polished of a semiconductor substrate such as a wafer during a dual damascene polishing removal process. It is intended to do so.

【0012】[0012]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体基板の研磨装置は、半導体基板を
保持する基板チャックと、少なくとも1以上の研磨液供
給用の小孔を有する研磨ヘッドと、該研磨ヘッドに保持
され前記研磨液供給用の小孔に対応する部位に貫通孔を
有する研磨パッドと、半導体基板を研磨する際に前記研
磨パッドの研磨面を前記基板チャックに保持される半導
体基板の被研磨面に接触させあるいは100μm以下の
距離をおいて対向させるための手段とを備え、被研磨面
に銅またはアルミニウムを含む金属膜を有する半導体基
板を研磨する研磨装置において、前記研磨ヘッドの研磨
パッドを保持する面側に複数の電極を各電極間距離が半
導体基板上のチップ幅より長くなるように配設し、前記
研磨パッドにおける前記電極に対応する部位にそれぞれ
貫通孔を設けるとともに、半導体基板を研磨する際に各
電極間の抵抗値を測定する手段と、測定された電極間抵
抗値が予め設定した値を越えたことを判定する手段を備
え、少なくとも一つの電極間抵抗値が予め設定した値を
越えた時に半導体基板の研磨を終了することを特徴とす
る。
To achieve the above object, a semiconductor substrate polishing apparatus according to the present invention has a substrate chuck for holding a semiconductor substrate and at least one small hole for supplying a polishing liquid. A polishing head, a polishing pad held by the polishing head and having a through hole at a portion corresponding to the small hole for supplying the polishing liquid, and a polishing surface of the polishing pad held by the substrate chuck when polishing a semiconductor substrate. Means for contacting the surface to be polished of the semiconductor substrate to be or opposed at a distance of 100 μm or less, a polishing apparatus for polishing a semiconductor substrate having a metal film containing copper or aluminum on the surface to be polished, A plurality of electrodes are disposed on the surface of the polishing head that holds the polishing pad so that the distance between the electrodes is longer than the chip width on the semiconductor substrate. A means for measuring the resistance value between the electrodes when polishing the semiconductor substrate while providing a through-hole at each of the portions corresponding to the electrodes, and that the measured resistance value between the electrodes exceeds a preset value. Determining means for ending the polishing of the semiconductor substrate when at least one of the interelectrode resistance values exceeds a preset value.

【0013】本発明の半導体基板の研磨装置は、半導体
基板を保持する基板チャックと、少なくとも1以上の研
磨液供給用の小孔を有する研磨ヘッドと、該研磨ヘッド
に保持され前記研磨液供給用の小孔に対応する部位に貫
通孔を有する研磨パッドと、半導体基板を研磨する際に
前記研磨パッドの研磨面を前記基板チャックに保持され
る半導体基板の被研磨面に接触させあるいは100μm
以下の距離をおいて対向させるための手段とを備え、被
研磨面に銅またはアルミニウムを含む金属膜を有する半
導体基板を研磨する研磨装置において、前記研磨ヘッド
の研磨パッドを保持する面側に複数の電極を各電極間距
離が半導体基板上のチップ幅より長くなるように配設
し、前記研磨パッドにおける前記電極に対応する部位に
それぞれ貫通孔を設けるとともに、半導体基板を研磨す
る際に各電極間の抵抗値を測定する手段と、研磨時間を
計測する手段と、測定された電極間抵抗値が予め設定し
た値を越えたことを判定する手段を備え、少なくとも一
つの電極間抵抗値が予め設定した値を越えた時から、そ
れまでに要した時間の1/5以下の時間が経過した時点
で、半導体基板の研磨を終了することを特徴とする。
According to the present invention, there is provided an apparatus for polishing a semiconductor substrate, comprising: a substrate chuck for holding a semiconductor substrate; a polishing head having at least one small hole for supplying a polishing liquid; and a polishing head held by the polishing head for supplying the polishing liquid. A polishing pad having a through-hole at a position corresponding to the small hole, and when polishing the semiconductor substrate, bringing the polishing surface of the polishing pad into contact with the surface to be polished of the semiconductor substrate held by the substrate chuck, or 100 μm
A polishing apparatus for polishing a semiconductor substrate having a metal film containing copper or aluminum on a surface to be polished. Are arranged such that the distance between the electrodes is longer than the chip width on the semiconductor substrate, and a through-hole is provided in each of the portions of the polishing pad corresponding to the electrodes. Means for measuring the resistance value between the electrodes, means for measuring the polishing time, and means for determining that the measured interelectrode resistance value has exceeded a preset value, and at least one interelectrode resistance value is determined in advance. The polishing of the semiconductor substrate is terminated when a time equal to or less than 1/5 of the time required up to the set value is exceeded.

【0014】また、本発明の半導体基板の研磨装置にお
いて、測定する電極間抵抗値は、任意の一対の電極間の
抵抗値である。
Further, in the semiconductor substrate polishing apparatus of the present invention, the measured inter-electrode resistance is the resistance between any pair of electrodes.

【0015】[0015]

【作用】本発明の半導体基板の研磨装置によれば、研磨
ヘッドの研磨パッドを保持する面側に複数の電極を各電
極間距離が半導体基板上のチップ幅より長くなるように
配設し、半導体基板を研磨液を介在させて研磨する際
に、各電極間に電圧をかけて、半導体基板のスクライブ
ライン上の金属膜の有無を検出し、この半導体基板のス
クライブライン上の金属膜の有無を半導体基板上の金属
膜の状態を代表するものとして、少なくとも一つの電極
間抵抗値が所望の設定抵抗値を越えたことを判定するこ
とにより、半導体基板の被研磨面の金属膜の有無を検出
し、その時点を研磨終了時点とする。これにより、半導
体基板の研磨中に被研磨面の金属膜の有無を検出するこ
とができ、さらに金属膜を研磨除去しかつ配線溝内に十
分な金属材料を残すことができる。
According to the semiconductor substrate polishing apparatus of the present invention, a plurality of electrodes are arranged on the surface of the polishing head holding the polishing pad so that the distance between the electrodes is longer than the chip width on the semiconductor substrate. When a semiconductor substrate is polished with a polishing liquid interposed, a voltage is applied between the electrodes to detect the presence or absence of a metal film on the scribe line of the semiconductor substrate, and to detect the presence or absence of a metal film on the scribe line of the semiconductor substrate. Is representative of the state of the metal film on the semiconductor substrate, the presence or absence of the metal film on the polished surface of the semiconductor substrate is determined by determining that at least one inter-electrode resistance exceeds a desired set resistance. Detection is made, and that time is defined as the polishing end time. This makes it possible to detect the presence or absence of the metal film on the surface to be polished during the polishing of the semiconductor substrate, to polish and remove the metal film, and to leave a sufficient metal material in the wiring groove.

【0016】また、少なくとも一つの電極間抵抗値が所
望の設定抵抗値を越えた時点からさらに起算して一定時
間経過した時点を検出して研磨終了時点とすることによ
り、半導体基板の被研磨面の金属膜を確実に研磨除去す
ることができ、また、配線溝内に十分な金属材料を残す
ことができる。
Further, a point in time at which a predetermined time has elapsed from the point in time when at least one interelectrode resistance value has exceeded a desired set resistance value is detected and the polishing end point is determined, whereby the surface to be polished of the semiconductor substrate is detected. Can be reliably removed by polishing, and a sufficient metal material can be left in the wiring groove.

【0017】さらに、電極と半導体基板の被研磨面の間
に研磨液が介在するので、研磨屑などの異物が電極と半
導体基板の間にあっても導通を妨げることがなく、電極
間抵抗値を安定して精度よく測定することが可能とな
り、また、電極が半導体基板に接触しないので、半導体
基板の被研磨面を傷付けることなく金属膜の有無を検出
することが可能となる。
Further, since the polishing liquid is interposed between the electrode and the surface to be polished of the semiconductor substrate, even if foreign matter such as polishing debris is present between the electrode and the semiconductor substrate, conduction is not hindered, and the resistance value between the electrodes is stabilized. As a result, since the electrodes do not contact the semiconductor substrate, the presence or absence of a metal film can be detected without damaging the polished surface of the semiconductor substrate.

【0018】[0018]

【発明の実施の形態】本発明の実施の形態を図面に基づ
いて説明する。
Embodiments of the present invention will be described with reference to the drawings.

【0019】(第1の実施例)図1は、本発明の半導体
基板の研磨装置の第1の実施例を示す概略構成図であ
り、図2は、本発明の半導体基板の研磨装置の第1の実
施例における研磨ヘッドの構成を示す図であって、
(a)は概略的な断面図であり、(b)はその下面図で
ある。
(First Embodiment) FIG. 1 is a schematic diagram showing a first embodiment of a semiconductor substrate polishing apparatus according to the present invention. FIG. 2 is a schematic view showing a semiconductor substrate polishing apparatus according to a first embodiment of the present invention. FIG. 3 is a diagram showing a configuration of a polishing head according to one embodiment,
(A) is a schematic sectional view, (b) is its bottom view.

【0020】図1において、被研磨面に銅またはアルミ
ニウムを含む金属膜を有する半導体基板としての半導体
ウエハ1を保持するウエハチャック2は、容器10内に
収容され、ウエハチャック2を回転駆動する回転駆動手
段3およびウエハチャック2を揺動させる揺動駆動手段
4が設けられている。容器10は、半導体ウエハ1の研
磨に際して研磨ヘッド6側から供給される研磨液をすべ
て受け排出管10aを介して回収するためのものであ
り、容器10の内面は電導体で形成され、感電を防止す
るように電気的に接地してある。これらの部分を研磨ス
テーションAと呼ぶ。なお、半導体ウエハ表面は、複数
のチップ領域に区切られている。
In FIG. 1, a wafer chuck 2 for holding a semiconductor wafer 1 as a semiconductor substrate having a metal film containing copper or aluminum on a surface to be polished is accommodated in a container 10 and is rotated by a rotating drive of the wafer chuck 2. A swing drive unit 4 for swinging the drive unit 3 and the wafer chuck 2 is provided. The container 10 is for receiving all the polishing liquid supplied from the polishing head 6 side during the polishing of the semiconductor wafer 1 and collecting the polishing liquid via the discharge pipe 10a. The inner surface of the container 10 is formed of a conductor, and the electric shock is prevented. It is electrically grounded to prevent it. These parts are called polishing station A. Note that the surface of the semiconductor wafer is divided into a plurality of chip areas.

【0021】この研磨ステーションAの側方には、研磨
パッド5の研磨面をコンディショニングするためのコン
ディショニングステーションBが配置されており、この
コンディショニングステーションBには、研磨パッド5
の研磨面をコンディショニングするコンディショニング
工具11とこのコンディショニング工具11を駆動する
駆動手段12が配設されており、コンディショニング工
具11の表面は、ナイロンブラシまたは樹脂にダイヤモ
ンドを埋め込んだもので形成される。
A conditioning station B for conditioning the polishing surface of the polishing pad 5 is provided beside the polishing station A. The conditioning station B includes a polishing pad 5.
A conditioning tool 11 for conditioning the polishing surface and a driving means 12 for driving the conditioning tool 11 are provided. The surface of the conditioning tool 11 is formed by embedding diamond in a nylon brush or resin.

【0022】ウエハチャック2に保持される半導体ウエ
ハ1に対向するように研磨パッド5を保持する研磨ヘッ
ド6には、研磨ヘッド6を回転駆動する回転駆動手段
7、研磨ヘッド6を上下動させる上下動駆動手段8およ
び研磨ヘッド6を研磨ステーションAとコンディショニ
ングステーションBとの間で移動させるための移動手段
9が設けられている。
The polishing head 6 for holding the polishing pad 5 so as to face the semiconductor wafer 1 held on the wafer chuck 2 includes a rotation driving means 7 for driving the polishing head 6 to rotate, and an up-and-down operation for moving the polishing head 6 up and down. A moving means 9 for moving the dynamic driving means 8 and the polishing head 6 between the polishing station A and the conditioning station B is provided.

【0023】研磨ヘッド6において、その研磨パッド5
を保持する面には、図2の(a)および(b)に示すよ
うに、複数の電極22が格子状に配列され、各電極間の
距離は半導体ウエハ1上のチップサイズより長く形成さ
れる。電極22(a〜i)と半導体ウエハ1上のチップ
1aとの位置関係の一例を図5に図示する(なお、図5
に関しては後述する)。また、研磨ヘッド6の中央部分
には研磨液を供給するための小孔25が少なくとも1個
(図2においては、同一円周上に4個)設けられ、これ
らの小孔25には図示しない研磨液供給手段に連通する
研磨液供給管26が接続され、研磨液は、半導体ウエハ
1の研磨に際して、研磨液供給手段から研磨液供給管2
6を介して小孔25から研磨パッド5の研磨面と半導体
ウエハ1の被研磨面との間に供給される。研磨ヘッド6
に設けられた複数の電極22はそれぞれ電線30を介し
て電気信号処理手段24に接続され、これらの電極22
と電気信号処理手段24を結合する電線30はそれぞれ
シールド線で形成することが望ましい。また、研磨ヘッ
ド6に保持される研磨パッド5には、研磨ヘッド6の研
磨液供給用の小孔25および電極22に対応する部位に
それぞれ貫通孔21が設けられている。
In the polishing head 6, the polishing pad 5
As shown in FIGS. 2A and 2B, a plurality of electrodes 22 are arranged in a grid pattern, and the distance between the electrodes is longer than the chip size on the semiconductor wafer 1. You. An example of the positional relationship between the electrodes 22 (a to i) and the chips 1a on the semiconductor wafer 1 is shown in FIG.
Will be described later). Further, at least one small hole 25 for supplying the polishing liquid is provided in the center portion of the polishing head 6 (four holes on the same circumference in FIG. 2), and these small holes 25 are not shown. A polishing liquid supply pipe 26 communicating with the polishing liquid supply means is connected, and the polishing liquid is supplied from the polishing liquid supply means to the polishing liquid supply pipe 2 when polishing the semiconductor wafer 1.
Through the small holes 25, the semiconductor wafer 1 is supplied between the polishing surface of the polishing pad 5 and the surface to be polished of the semiconductor wafer 1. Polishing head 6
Are connected to the electric signal processing means 24 via electric wires 30, respectively.
It is preferable that each of the electric wires 30 connecting the electric signal processing means 24 and the electric signal processing means 24 is formed of a shield wire. The polishing pad 5 held by the polishing head 6 is provided with through holes 21 at portions corresponding to the small holes 25 for supplying the polishing liquid and the electrodes 22 of the polishing head 6.

【0024】電気信号処理手段24は、半導体ウエハ1
の研磨に際して、任意の電極間に電圧をかけてその電極
間に流れる電流値を測定し、この電圧と電流値から、そ
の電極の周囲の研磨液と半導体ウエハ1の被研磨面の金
属膜の合成抵抗値を検知することができる。なお、この
半導体ウエハ1の研磨に際して、半導体ウエハ1の被研
磨面と研磨パッド5の研磨面との間に供給される研磨液
が、研磨ヘッド6に設けられた複数の電極22と半導体
ウエハ1の被研磨面上の金属膜を電気的に結合する作用
をする。また、電極間抵抗値の検知に際して、前述した
ように、任意の一対の電極間の抵抗値のみを測定するこ
ともできるし、また、任意の一対の電極間抵抗値を順次
測定し結果的に全ての電極間抵抗値を測定するように構
成することもでき、さらに、多数の電極間抵抗値を同時
に測定することができるように構成することもできる。
The electric signal processing means 24 includes a semiconductor wafer 1
At the time of polishing, a voltage is applied between arbitrary electrodes and a current value flowing between the electrodes is measured. From the voltage and the current value, the polishing liquid around the electrode and the metal film on the surface to be polished of the semiconductor wafer 1 are measured. The combined resistance value can be detected. When polishing the semiconductor wafer 1, the polishing liquid supplied between the surface to be polished of the semiconductor wafer 1 and the polishing surface of the polishing pad 5 is applied to the plurality of electrodes 22 provided on the polishing head 6 and the semiconductor wafer 1. To electrically couple the metal film on the surface to be polished. When detecting the interelectrode resistance value, as described above, only the resistance value between any pair of electrodes can be measured, or the resistance value between any pair of electrodes can be sequentially measured, and as a result, All the interelectrode resistance values can be measured, and furthermore, a large number of interelectrode resistance values can be measured simultaneously.

【0025】また、電気信号処理手段24を研磨ヘッド
6に内蔵し、その測定結果を無線や光信号等で研磨ヘッ
ド外に設けた受信・制御手段に発信するように構成する
こともでき、これにより研磨ヘッドからの配線を簡素化
することが可能となる。
Further, the electric signal processing means 24 may be built in the polishing head 6, and the measurement result may be transmitted to a receiving / control means provided outside the polishing head by radio or optical signal. This makes it possible to simplify the wiring from the polishing head.

【0026】研磨ヘッド6と研磨パッド5は研磨液と接
触する部位を絶縁体で覆うことが好ましく、また、低誘
電体であることが望ましい。これにより、測定誤差を小
さくすることができる。
It is preferable that the polishing head 6 and the polishing pad 5 cover an area in contact with the polishing liquid with an insulator, and it is desirable that the polishing head 6 and the polishing pad 5 are made of a low dielectric substance. Thereby, a measurement error can be reduced.

【0027】研磨パッド5の研磨面に研磨液を流すため
の溝を設けることもできるが、この研磨液用の溝は、電
極22に対応する貫通孔21と交差しないように設ける
ことが望ましい。これにより、電極間抵抗値の測定に際
して、実質的な研磨液の抵抗値を増加させ、半導体ウエ
ハ上の金属膜の抵抗値を精度よく計測することができる
という効果がある。
Although a groove for flowing a polishing liquid can be provided on the polishing surface of the polishing pad 5, it is desirable that the groove for the polishing liquid be provided so as not to intersect with the through hole 21 corresponding to the electrode 22. Thereby, when measuring the resistance value between the electrodes, there is an effect that the resistance value of the substantial polishing liquid can be increased and the resistance value of the metal film on the semiconductor wafer can be accurately measured.

【0028】また、研磨パッド5の研磨面が研磨により
劣化しないときは、研磨パッド5は研磨ヘッド6と一体
に形成することも可能である。
When the polishing surface of the polishing pad 5 is not deteriorated by polishing, the polishing pad 5 can be formed integrally with the polishing head 6.

【0029】研磨ヘッド6に設けた複数の電極22は、
研磨パッドの全面に均等に配置することが望ましく、図
2の(a)に示す格子状の配列に代えて、複数の電極2
2を複数の同心円上に均等に配列することも可能であ
る。このように複数の電極22を研磨パッド5の全面に
わたって均等に配列することにより、半導体ウエハ1の
被研磨面の金属膜を広く均等に測定することが可能とな
る。また、電極22は、研磨パッド5の研磨表面から数
μmから数100μm奥まった位置に電極表面を配置す
ることが好ましく、電極22の表面を研磨パッド5の厚
みの中間部分に位置するように配置する。これにより、
電極22が半導体ウエハ1の被研磨面に接触することが
なく、さらに、電極22の表面に空気を滞留しにくくす
る効果もある。また、電極の表面積を数mm2 とするこ
とにより、電極間抵抗値の測定への影響を小さくするこ
とができる。
The plurality of electrodes 22 provided on the polishing head 6
It is desirable that the electrodes are arranged uniformly over the entire surface of the polishing pad. Instead of the grid-like arrangement shown in FIG.
2 can be evenly arranged on a plurality of concentric circles. By uniformly arranging the plurality of electrodes 22 over the entire surface of the polishing pad 5, it becomes possible to measure the metal film on the surface to be polished of the semiconductor wafer 1 widely and uniformly. Further, it is preferable that the electrode 22 is disposed at a position several μm to several hundred μm behind the polishing surface of the polishing pad 5, and the electrode 22 is disposed such that the surface of the electrode 22 is located at an intermediate portion of the thickness of the polishing pad 5. I do. This allows
The electrode 22 does not come into contact with the surface to be polished of the semiconductor wafer 1, and further has the effect of making it difficult for air to stay on the surface of the electrode 22. In addition, by setting the surface area of the electrodes to several mm 2 , the influence on the measurement of the interelectrode resistance can be reduced.

【0030】次に、以上のように構成される本実施例の
研磨装置における半導体ウエハの研磨および研磨終点の
検出について説明する。
Next, polishing of the semiconductor wafer and detection of the polishing end point in the polishing apparatus of the present embodiment configured as described above will be described.

【0031】先ず、研磨に先立って、半導体ウエハ1を
ウエハチャック2にセットする。一方、研磨ヘッド6
は、移動手段9によりコンディショニングステーション
Bへ移動され、上下動駆動手段8により研磨ヘッド6を
下降させて、研磨ヘッド6に保持される研磨パッド5を
コンディショニング工具11に当接させる。そして、回
転駆動手段12によりコンディショニング工具11を回
転させ同時に研磨ヘッド6を回転駆動手段7で回転させ
ることにより、研磨パッド5の研磨面をコンディショニ
ングする。このコンディショニングの頻度は研磨毎に行
なってもよい。
First, the semiconductor wafer 1 is set on the wafer chuck 2 prior to polishing. On the other hand, the polishing head 6
Is moved to the conditioning station B by the moving means 9, the polishing head 6 is lowered by the vertical movement driving means 8, and the polishing pad 5 held by the polishing head 6 is brought into contact with the conditioning tool 11. Then, the conditioning tool 11 is rotated by the rotation driving means 12 and the polishing head 6 is simultaneously rotated by the rotation driving means 7 to condition the polishing surface of the polishing pad 5. This conditioning may be performed for each polishing.

【0032】半導体ウエハの研磨に際して、研磨ヘッド
6は、移動手段9により研磨ステーションAへ移動さ
れ、上下動駆動手段8により研磨ヘッド6を下降させ
て、研磨パッド5を半導体ウエハ1の被研磨面に接触さ
せ、あるいは、研磨パッド5と半導体ウエハ1の被研磨
面とをその間隔距離が100μm以下となるように対向
させ、そして、研磨パッド5は研磨ヘッド6の回転駆動
手段7で回転駆動される。また、半導体ウエハ1を保持
するウエハチャック2は、回転駆動手段3により回転駆
動され、さらに、揺動駆動手段4により揺動される。同
時に、研磨液は、図示しない研磨液供給手段から研磨液
供給管26を経て、研磨ヘッド6の小孔25および研磨
パッド5の貫通孔21を介して、研磨パッド5の研磨面
と半導体ウエハ1の被研磨面との間に供給される。この
ようにして、半導体ウエハ1の被研磨面の研磨が行なわ
れる。
When polishing the semiconductor wafer, the polishing head 6 is moved to the polishing station A by the moving means 9, and the polishing head 6 is lowered by the vertical movement driving means 8, so that the polishing pad 5 is moved to the polishing surface of the semiconductor wafer 1. Or, the polishing pad 5 and the surface to be polished of the semiconductor wafer 1 are opposed to each other so that the distance between them is 100 μm or less, and the polishing pad 5 is rotationally driven by the rotation driving means 7 of the polishing head 6. You. Further, the wafer chuck 2 holding the semiconductor wafer 1 is rotationally driven by the rotation driving means 3 and further oscillated by the oscillating driving means 4. At the same time, the polishing liquid is supplied from a polishing liquid supply means (not shown) to the polishing surface of the polishing pad 5 and the semiconductor wafer 1 through the small holes 25 of the polishing head 6 and the through holes 21 of the polishing pad 5 through the polishing liquid supply pipe 26. And the surface to be polished. Thus, the polished surface of the semiconductor wafer 1 is polished.

【0033】このように半導体ウエハを研磨液を介在さ
せて研磨する際に、電気信号処理手段24は、任意の電
極間に電圧をかけて、その電極間に流れる電流値を測定
し、この電圧と電流値から各電極22の周囲の研磨液と
半導体ウエハ1の被研磨面の金属膜の合成抵抗値を電極
間抵抗値として検知する。このとき、同時に多点の電極
間抵抗値を測定することもでき、また、順次任意の一対
の電極間抵抗値を測定し結果的に全ての電極間抵抗値を
測定することもできる。
When the semiconductor wafer is polished with the polishing liquid interposed therebetween, the electric signal processing means 24 applies a voltage between arbitrary electrodes, measures a current value flowing between the electrodes, and measures the voltage. From the current value, the combined resistance value of the polishing liquid around each electrode 22 and the metal film on the polished surface of the semiconductor wafer 1 is detected as the inter-electrode resistance value. At this time, the resistance value between the electrodes at multiple points can be measured at the same time, and the resistance value between any pair of electrodes can be sequentially measured, and as a result, all the resistance values between the electrodes can be measured.

【0034】ここで、本実施例による電極間抵抗値と半
導体ウエハ上の金属膜の関係について説明する。金属膜
厚と電極間抵抗値には、図3に示すような相関関係があ
り、金属膜が薄肉化されるにしたがって電極間抵抗値は
増加する。また、電極間の面積のうち金属膜の占める金
属膜面積比と電極間抵抗値には、ラインアンドスペース
(L&S)の向きに応じて、図4に示すような相関関係
がある。すなわち、ラインアンドスペース(L&S)の
向きが電極方向である場合(b)には、電極間抵抗値は
金属膜面積比と相関がないが、ラインアンドスペース
(L&S)の向きが電極間結線に直交する場合(a)に
は、電極間抵抗値は、金属膜面積比が大きくなる程、小
さくなる。これらから、金属膜の厚みを電極間抵抗値で
検出するのは難しいが、電極間に金属膜のない領域があ
れば、電極間抵抗で金属膜の厚みを容易に検出できるこ
とが分かる。半導体ウエハ上で、研磨により金属膜が全
くなくなるところは、スクライブラインである。このス
クライブライン間の距離(すなわち、チップ幅)より長
く電極間距離をとることにより、電極間抵抗値を測定す
ることで、半導体ウエハのスクライブライン上の金属膜
の有無を検出することができる。そこで、このスクライ
ブライン上の金属膜の有無を半導体ウエハ上の金属膜の
状態を代表するものと考え、スクライブライン上の金属
膜の有無を検出して研磨終点を判定することができる。
Here, the relationship between the inter-electrode resistance and the metal film on the semiconductor wafer according to the present embodiment will be described. The metal film thickness and the inter-electrode resistance have a correlation as shown in FIG. 3, and the inter-electrode resistance increases as the metal film becomes thinner. Further, the metal film area ratio occupied by the metal film in the area between the electrodes and the interelectrode resistance have a correlation as shown in FIG. 4 according to the direction of the line and space (L & S). That is, when the direction of the line and space (L & S) is the electrode direction (b), the interelectrode resistance does not correlate with the metal film area ratio, but the direction of the line and space (L & S) is In the case of orthogonality (a), the interelectrode resistance decreases as the metal film area ratio increases. From these results, it is difficult to detect the thickness of the metal film by the inter-electrode resistance value, but if there is a region without the metal film between the electrodes, the thickness of the metal film can be easily detected by the inter-electrode resistance. A portion of the semiconductor wafer where the metal film is completely removed by polishing is a scribe line. By taking the inter-electrode distance longer than the distance between the scribe lines (that is, the chip width) and measuring the inter-electrode resistance value, the presence or absence of a metal film on the scribe line of the semiconductor wafer can be detected. Therefore, it is considered that the presence or absence of the metal film on the scribe line is representative of the state of the metal film on the semiconductor wafer, and the end of polishing can be determined by detecting the presence or absence of the metal film on the scribe line.

【0035】これを、電極間距離を半導体ウエハのチッ
プの幅よりも長く形成して格子状に配列された電極と半
導体ウエハのチップの位置関係についてさらに図5を用
いて説明する。図5において、1aは半導体ウエハ1に
形成されるチップであり、1bはチップ1a間のスクラ
イブラインである。22(a〜i)は研磨ヘッド上に格
子状に配列された電極である。電極aで測定する抵抗値
は、電極aの周囲の8個の電極b〜iとの間の抵抗値に
より決まる。例えば、電極a、b、d、f、hが同電位
で、電極c、e、g、iが同電位であって、電極aと電
極cとの間に電位差があり、電極aと電極cの間に金属
膜1cが残っている場合を考えると、この場合、電極a
で測定する抵抗値は他の電極の抵抗値に比べて低くな
り、金属膜1cが残っていると判定することができる。
また、一対の電極間の抵抗値を順次測定することによ
り、一対の電極間にあるスクライブライン1b上の金属
膜1cの有無を、その他の金属膜の影響を無視して、検
出することが可能であり、多数の電極により金属膜の有
無を検出する場合と比べ、測定の分解能を上げることが
できる。
This will be further described with reference to FIG. 5 regarding the positional relationship between the electrodes arranged in a grid and the chips of the semiconductor wafer in which the distance between the electrodes is longer than the width of the chips on the semiconductor wafer. In FIG. 5, 1a is a chip formed on the semiconductor wafer 1, and 1b is a scribe line between the chips 1a. Reference numerals 22 (a to i) denote electrodes arranged in a grid on the polishing head. The resistance measured at the electrode a is determined by the resistance between the eight electrodes b to i around the electrode a. For example, the electrodes a, b, d, f, and h have the same potential, the electrodes c, e, g, and i have the same potential, and there is a potential difference between the electrodes a and c. Considering the case where the metal film 1c remains between the electrodes a in this case,
Is lower than the resistance values of the other electrodes, and it can be determined that the metal film 1c remains.
Further, by sequentially measuring the resistance value between the pair of electrodes, the presence or absence of the metal film 1c on the scribe line 1b between the pair of electrodes can be detected ignoring the influence of the other metal films. Therefore, the resolution of the measurement can be increased as compared with the case where the presence or absence of the metal film is detected by a large number of electrodes.

【0036】以上のように、半導体ウエハの被研磨面の
金属膜の研磨が進むにつれて、電極間距離を半導体ウエ
ハのチップの幅よりも長く形成して格子状に配列された
電極間の抵抗値は、図6に示すように変化する。そこ
で、少なくとも一つの電極間抵抗値が所望の設定抵抗値
を越えた時に、半導体ウエハ上のスクライブライン上に
金属膜がなく、このスクライブライン上の金属膜の有無
を半導体ウエハ上の金属膜の状態を代表するものとし
て、半導体ウエハの被研磨面の金属膜がなくなったと判
定することができ、その時点で研磨を終了する。
As described above, as the polishing of the metal film on the surface to be polished of the semiconductor wafer progresses, the distance between the electrodes is formed to be longer than the width of the chip of the semiconductor wafer, and the resistance between the electrodes arranged in a grid is formed. Changes as shown in FIG. Therefore, when the resistance value between at least one electrode exceeds a desired set resistance value, there is no metal film on the scribe line on the semiconductor wafer, and the presence or absence of the metal film on the scribe line is determined by the presence of the metal film on the semiconductor wafer. As a representative of the state, it can be determined that the metal film on the surface to be polished of the semiconductor wafer has disappeared, and polishing is terminated at that point.

【0037】研磨終了後、半導体ウエハ1を図示しない
手段によりウエハチャック2から取り外して、研磨工程
を終了する。
After the polishing, the semiconductor wafer 1 is removed from the wafer chuck 2 by means not shown, and the polishing process is completed.

【0038】このように、電極間距離をチップの幅より
も長く形成した電極間の抵抗値でスクライブライン上の
金属膜の有無を検出し、少なくとも一つの電極間抵抗値
が所望の設定抵抗値を越えたことを判定することによ
り、半導体ウエハのスクライブライン上の金属膜の有無
を半導体ウエハ上の金属膜の状態を代表するものとし
て、半導体ウエハの被研磨面の金属膜の有無を検出する
ことができ、そして、この時点で研磨を終了することに
より、金属膜を研磨除去しかつ配線溝内に十分な金属材
料を残すことができる。
As described above, the presence or absence of the metal film on the scribe line is detected by the resistance value between the electrodes formed so that the distance between the electrodes is longer than the width of the chip, and at least one resistance value between the electrodes is set to a desired set resistance value. Is determined, the presence or absence of the metal film on the scribe line of the semiconductor wafer is represented as the state of the metal film on the semiconductor wafer, and the presence or absence of the metal film on the polished surface of the semiconductor wafer is detected. By finishing the polishing at this point, the metal film can be removed by polishing and a sufficient metal material can be left in the wiring groove.

【0039】さらに、電極と半導体ウエハの被研磨面の
間に研磨液が介在するので、研磨屑などの異物が電極と
半導体ウエハの間にあっても導通を妨げることがなく、
電極間抵抗値を安定して測定することができる。また、
電極が研磨パッドの貫通孔内に位置しているので、半導
体ウエハに接触することがなく、半導体ウエハの被研磨
面を傷付けることなく電極間抵抗値を検知することが可
能となる。さらに、半導体ウエハの被研磨面の金属膜の
有無を研磨中に検出することができるので、半導体ウエ
ハの金属膜、特に配線溝内の金属材料を除去しすぎると
いうことがない。
Further, since the polishing liquid is interposed between the electrode and the surface to be polished of the semiconductor wafer, even if foreign matter such as polishing debris is present between the electrode and the semiconductor wafer, conduction is not hindered.
The interelectrode resistance can be measured stably. Also,
Since the electrodes are located in the through-holes of the polishing pad, the resistance between the electrodes can be detected without contacting the semiconductor wafer and without damaging the polished surface of the semiconductor wafer. Furthermore, since the presence or absence of the metal film on the surface to be polished of the semiconductor wafer can be detected during polishing, the metal film of the semiconductor wafer, particularly, the metal material in the wiring groove is not excessively removed.

【0040】(第2の実施例)次に、本発明の研磨装置
の第2の実施例について図7を用いて説明する。本実施
例は、研磨終点の判定方法を前述した第1の実施例と異
にするものであり、その他の構成は、前述した実施例と
同様であり、前述した実施例と同様の部材には同一符号
を用い、図1および図2を参照して説明する。
(Second Embodiment) Next, a second embodiment of the polishing apparatus of the present invention will be described with reference to FIG. This embodiment is different from the above-described first embodiment in the method of determining the polishing end point. Other configurations are the same as those of the above-described embodiment. The description will be made with reference to FIGS. 1 and 2 using the same reference numerals.

【0041】前述した第1の実施例では、半導体ウエハ
のスクライブライン上の金属膜の有無を半導体ウエハ上
の金属膜の有無の代表値として、少なくとも一つの電極
間抵抗値が所望の設定抵抗値を越えた時を研磨終了時点
と判定している。しかしながら、条件によっては、これ
が当てはまらないことも考えられる。例えば、半導体ウ
エハのスクライブライン上の金属膜は研磨除去されてい
ると検出されても、半導体ウエハのチップ内に未だ余分
な金属膜が残っている場合も考えられる。そこで、本実
施例では、半導体ウエハの被研磨面の金属膜を確実に除
去することができるようにするものである。
In the first embodiment described above, the presence or absence of a metal film on a scribe line of a semiconductor wafer is used as a representative value of the presence or absence of a metal film on a semiconductor wafer, and at least one inter-electrode resistance value is a desired set resistance value. Is determined to be the polishing end point. However, depending on the conditions, this may not be the case. For example, even if it is detected that the metal film on the scribe line of the semiconductor wafer is polished and removed, there may be a case where an extra metal film still remains in the chip of the semiconductor wafer. Therefore, in this embodiment, the metal film on the surface to be polished of the semiconductor wafer can be surely removed.

【0042】本実施例においては、前述した第1の実施
例で説明した研磨装置に加えて、研磨時間を計測する手
段をさらに具備し、研磨開始時から少なくとも一つの電
極間抵抗値が所望の設定抵抗値を越えるまでに要した時
間Tを計測し、その時点からさらに予め設定された係数
αを研磨経過時間Tに乗じたαT時間経過する時点まで
研磨を続行し、αT時間経過した時点で、半導体ウエハ
1の被研磨面の金属膜がなくなったと判定して研磨を終
了する。ここで、係数αは、研磨液の比抵抗と、研磨パ
ッド5の研磨面と半導体ウエハ1の被研磨面の距離と、
半導体ウエハ1の被研磨面の金属膜の比抵抗を勘案して
予め設定する値であって、0<α<1/5の範囲に設定
する。
In this embodiment, in addition to the polishing apparatus described in the first embodiment, a means for measuring a polishing time is further provided, and at least one inter-electrode resistance value is set to a desired value from the start of polishing. The time T required to exceed the set resistance value is measured, and the polishing is continued from that time until the time elapses αT obtained by multiplying the elapsed time T by a predetermined coefficient α. Then, it is determined that the metal film on the surface to be polished of the semiconductor wafer 1 is gone, and the polishing is terminated. Here, the coefficient α is the specific resistance of the polishing liquid, the distance between the polished surface of the polishing pad 5 and the polished surface of the semiconductor wafer 1,
This is a value set in advance in consideration of the specific resistance of the metal film on the surface to be polished of the semiconductor wafer 1, and is set in the range of 0 <α <1/5.

【0043】本実施例による研磨に際しては、前述した
実施例と同様に、電気信号処理手段24により、任意の
電極間に電圧をかけて、その電極間に流れる電流値を測
定し、この電圧と電流値から各電極の周囲の研磨液と半
導体ウエハの被研磨面の金属膜の合成抵抗値を電極間抵
抗値として検知する。この抵抗値は研磨が進むにつれ図
7に示すように変化する。前述した実施例では、少なく
とも一つの電極間抵抗値が所望の設定抵抗値を越えた時
を研磨終了時点と判定しているが、本実施例では、少な
くとも一つの電極間抵抗値が所望の設定抵抗値を越えた
時点から起算してさらにαT時間経過した時点で、半導
体ウエハの被研磨面の金属膜がなくなったと判定して研
磨を終了する。すなわち、少なくとも一つの電極間抵抗
値が所望の設定抵抗値を越えた時点からこれまでの研磨
に要した時間Tの1/5以下の時間をさらに研磨する。
At the time of polishing according to this embodiment, similarly to the above-described embodiment, a voltage is applied between arbitrary electrodes by the electric signal processing means 24, and a current value flowing between the electrodes is measured. From the current value, the combined resistance value of the polishing liquid around each electrode and the metal film on the polished surface of the semiconductor wafer is detected as the inter-electrode resistance value. This resistance value changes as shown in FIG. 7 as polishing proceeds. In the above-described embodiment, when at least one inter-electrode resistance value exceeds a desired set resistance value, it is determined that polishing is completed, but in the present embodiment, at least one inter-electrode resistance value is a desired setting value. At the time when αT time has elapsed from the time when the resistance value is exceeded, it is determined that the metal film on the surface to be polished of the semiconductor wafer has disappeared, and the polishing is terminated. That is, the polishing is further performed for a time equal to or less than 1 / of the time T required for the polishing from the time when at least one inter-electrode resistance exceeds a desired set resistance.

【0044】このように、本実施例においては、半導体
ウエハのスクライブライン上の金属膜を研磨除去すると
ともに半導体ウエハのチップ内の余分な金属膜をも確実
に研磨除去することが可能となる。
As described above, in this embodiment, the metal film on the scribe line of the semiconductor wafer can be polished and removed, and the excess metal film in the chip of the semiconductor wafer can be surely polished and removed.

【0045】[0045]

【発明の効果】以上説明したように、本発明によれば、
研磨ヘッドの研磨パッドを保持する面側に複数の電極を
各電極間距離が半導体基板上のチップ幅より長くなるよ
うに配設し、半導体基板を研磨液を介在させて研磨する
際に、各電極間に電圧をかけて、半導体基板のスクライ
ブライン上の金属膜の有無を検出し、この半導体基板の
スクライブライン上の金属膜の有無を半導体基板上の金
属膜の状態を代表するものとして、少なくとも一つの電
極間抵抗値が所望の設定抵抗値を越えたことを判定する
ことにより、半導体基板の被研磨面の金属膜の有無を検
出し、その時点を研磨終了時点とする。これにより、半
導体基板の研磨中に被研磨面の金属膜の有無を検出する
ことができ、さらに金属膜を研磨除去しかつ配線溝内に
十分な金属材料を残すことができる。
As described above, according to the present invention,
A plurality of electrodes are arranged on the surface of the polishing head that holds the polishing pad so that the distance between the electrodes is longer than the chip width on the semiconductor substrate, and when polishing the semiconductor substrate with a polishing liquid interposed, By applying a voltage between the electrodes, the presence or absence of a metal film on the scribe line of the semiconductor substrate is detected, and the presence or absence of the metal film on the scribe line of the semiconductor substrate is representative of the state of the metal film on the semiconductor substrate. By judging that at least one inter-electrode resistance value exceeds a desired set resistance value, the presence or absence of a metal film on the surface to be polished of the semiconductor substrate is detected, and that time is regarded as the polishing end time. This makes it possible to detect the presence or absence of the metal film on the surface to be polished during the polishing of the semiconductor substrate, to polish and remove the metal film, and to leave a sufficient metal material in the wiring groove.

【0046】また、少なくとも一つの電極間抵抗値が所
望の設定抵抗値を越えた時点からさらに起算して一定時
間経過した時点を検出して研磨終了時点とすることによ
り、半導体基板の被研磨面の金属膜を確実に研磨除去す
ることができ、また、配線溝内に十分な金属材料を残す
ことができる。
Further, a point in time at which at least one inter-electrode resistance value exceeds a desired set resistance value and a predetermined time has elapsed from the time point is detected and the polishing end point is detected. Can be reliably removed by polishing, and a sufficient metal material can be left in the wiring groove.

【0047】さらに、電極と半導体基板の被研磨面の間
に研磨液が介在するので、研磨屑などの異物が電極と半
導体基板の間にあっても導通を妨げることがなく、電極
間抵抗値を安定して精度よく測定することが可能とな
り、また、電極が半導体基板に接触しないので、半導体
基板の被研磨面を傷付けることなく金属膜の有無を検出
することが可能となる。
Further, since the polishing liquid is interposed between the electrode and the surface to be polished of the semiconductor substrate, even if foreign matter such as polishing debris exists between the electrode and the semiconductor substrate, conduction is not hindered, and the resistance value between the electrodes is stabilized. As a result, since the electrodes do not contact the semiconductor substrate, the presence or absence of a metal film can be detected without damaging the polished surface of the semiconductor substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体基板の研磨装置の第1の実施例
を示す概略構成図である。
FIG. 1 is a schematic configuration diagram showing a first embodiment of a semiconductor substrate polishing apparatus according to the present invention.

【図2】本発明の半導体基板の研磨装置の第1の実施例
における研磨ヘッドの構成を示し、(a)は概略的な断
面図であり、(b)はその下面図である。
FIGS. 2A and 2B show the configuration of a polishing head in a semiconductor substrate polishing apparatus according to a first embodiment of the present invention, wherein FIG. 2A is a schematic cross-sectional view and FIG.

【図3】金属膜厚と電極間抵抗値の相関関係を示す図表
である。
FIG. 3 is a table showing a correlation between a metal film thickness and a resistance value between electrodes.

【図4】金属膜面積比と電極間抵抗値の相関関係を示す
図表である。
FIG. 4 is a table showing a correlation between a metal film area ratio and a resistance value between electrodes.

【図5】電極と半導体ウエハのチップの位置関係を示す
説明図である。
FIG. 5 is an explanatory diagram showing a positional relationship between electrodes and chips on a semiconductor wafer.

【図6】本発明の半導体基板の研磨装置の第1の実施例
における研磨終点の検出手法を説明するための図表であ
る。
FIG. 6 is a table for explaining a method of detecting a polishing end point in the first embodiment of the semiconductor substrate polishing apparatus of the present invention.

【図7】本発明の半導体基板の研磨装置の第2の実施例
における研磨終点の検出手法を説明するための図表であ
る。
FIG. 7 is a chart for explaining a method of detecting a polishing end point in a second embodiment of the semiconductor substrate polishing apparatus of the present invention.

【図8】デュアルダマシンプロセスを説明する工程図で
ある。
FIG. 8 is a process diagram illustrating a dual damascene process.

【図9】従来の研磨装置における研磨終点検出手段を説
明する概略図である。
FIG. 9 is a schematic diagram illustrating a polishing end point detecting means in a conventional polishing apparatus.

【符号の説明】[Explanation of symbols]

1 半導体ウエハ(半導体基板) 1a チップ 1b スクライブライン 1c 金属膜 2 ウエハチャック 3 回転駆動手段 4 揺動駆動手段 5 研磨パッド 6 研磨ヘッド 7 回転駆動手段 8 上下動駆動手段 9 移動手段 10 容器 11 コンディショニング工具 12 駆動手段 21 貫通孔 22 電極 24 電気信号処理手段 25 (研磨液供給用)小孔 26 研磨液供給管 30 電線 REFERENCE SIGNS LIST 1 semiconductor wafer (semiconductor substrate) 1a chip 1b scribe line 1c metal film 2 wafer chuck 3 rotation drive unit 4 swing drive unit 5 polishing pad 6 polishing head 7 rotation drive unit 8 vertical drive unit 9 transfer unit 10 container 11 conditioning tool DESCRIPTION OF SYMBOLS 12 Driving means 21 Through-hole 22 Electrode 24 Electric signal processing means 25 Small hole (for supplying polishing liquid) 26 Polishing liquid supply pipe 30 Electric wire

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) B24B 37/00 B24B 37/00 K 37/04 37/04 K 49/10 49/10 Fターム(参考) 3C034 AA19 BB92 CA02 CB01 DD01 3C058 AA07 AA09 AA19 BA01 BA09 BB02 BC01 BC02 CA01 CB05 DA12 DA17 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI theme coat ゛ (reference) B24B 37/00 B24B 37/00 K 37/04 37/04 K 49/10 49/10 F term (reference) 3C034 AA19 BB92 CA02 CB01 DD01 3C058 AA07 AA09 AA19 BA01 BA09 BB02 BC01 BC02 CA01 CB05 DA12 DA17

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板を保持する基板チャックと、
少なくとも1以上の研磨液供給用の小孔を有する研磨ヘ
ッドと、該研磨ヘッドに保持され前記研磨液供給用の小
孔に対応する部位に貫通孔を有する研磨パッドと、半導
体基板を研磨する際に前記研磨パッドの研磨面を前記基
板チャックに保持される半導体基板の被研磨面に接触さ
せあるいは100μm以下の距離をおいて対向させるた
めの手段とを備え、被研磨面に銅またはアルミニウムを
含む金属膜を有する半導体基板を研磨する研磨装置にお
いて、 前記研磨ヘッドの研磨パッドを保持する面側に複数の電
極を各電極間距離が半導体基板上のチップ幅より長くな
るように配設し、前記研磨パッドにおける前記電極に対
応する部位にそれぞれ貫通孔を設けるとともに、半導体
基板を研磨する際に各電極間の抵抗値を測定する手段
と、測定された電極間抵抗値が予め設定した値を越えた
ことを判定する手段を備え、少なくとも一つの電極間抵
抗値が予め設定した値を越えた時に半導体基板の研磨を
終了することを特徴とする半導体基板の研磨装置。
A substrate chuck for holding a semiconductor substrate;
A polishing head having at least one or more polishing liquid supply holes, a polishing pad held by the polishing head and having a through hole in a portion corresponding to the polishing liquid supply holes, and a method of polishing a semiconductor substrate. Means for contacting the polishing surface of the polishing pad with the surface to be polished of the semiconductor substrate held by the substrate chuck or facing the polishing pad at a distance of 100 μm or less, wherein the surface to be polished contains copper or aluminum. In a polishing apparatus for polishing a semiconductor substrate having a metal film, a plurality of electrodes are disposed on a surface side of the polishing head that holds a polishing pad such that a distance between the electrodes is longer than a chip width on the semiconductor substrate. A means for measuring a resistance value between each electrode when polishing a semiconductor substrate while providing a through hole at a portion corresponding to the electrode in the polishing pad, Means for determining that the interelectrode resistance exceeds a preset value, and terminating polishing of the semiconductor substrate when at least one interelectrode resistance exceeds the preset value. Polishing equipment.
【請求項2】 半導体基板を保持する基板チャックと、
少なくとも1以上の研磨液供給用の小孔を有する研磨ヘ
ッドと、該研磨ヘッドに保持され前記研磨液供給用の小
孔に対応する部位に貫通孔を有する研磨パッドと、半導
体基板を研磨する際に前記研磨パッドの研磨面を前記基
板チャックに保持される半導体基板の被研磨面に接触さ
せあるいは100μm以下の距離をおいて対向させるた
めの手段とを備え、被研磨面に銅またはアルミニウムを
含む金属膜を有する半導体基板を研磨する研磨装置にお
いて、 前記研磨ヘッドの研磨パッドを保持する面側に複数の電
極を各電極間距離が半導体基板上のチップ幅より長くな
るように配設し、前記研磨パッドにおける前記電極に対
応する部位にそれぞれ貫通孔を設けるとともに、半導体
基板を研磨する際に各電極間の抵抗値を測定する手段
と、研磨時間を計測する手段と、測定された電極間抵抗
値が予め設定した値を越えたことを判定する手段を備
え、少なくとも一つの電極間抵抗値が予め設定した値を
越えた時から、それまでに要した時間の1/5以下の時
間が経過した時点で、半導体基板の研磨を終了すること
を特徴とする半導体基板の研磨装置。
2. A substrate chuck for holding a semiconductor substrate,
A polishing head having at least one or more polishing liquid supply holes, a polishing pad held by the polishing head and having a through hole in a portion corresponding to the polishing liquid supply holes, and a method of polishing a semiconductor substrate. Means for contacting the polishing surface of the polishing pad with the surface to be polished of the semiconductor substrate held by the substrate chuck or facing the polishing pad at a distance of 100 μm or less, wherein the surface to be polished contains copper or aluminum. In a polishing apparatus for polishing a semiconductor substrate having a metal film, a plurality of electrodes are disposed on a surface side of the polishing head that holds a polishing pad such that a distance between the electrodes is longer than a chip width on the semiconductor substrate. Means for providing a through hole at a portion corresponding to the electrode in the polishing pad, and measuring a resistance value between the electrodes when polishing the semiconductor substrate; and a polishing time. Means for measuring, and means for determining that the measured inter-electrode resistance value exceeds a preset value, wherein at least one of the inter-electrode resistance values exceeds a preset value, and is required to be used from then on. A polishing apparatus for polishing a semiconductor substrate, wherein the polishing of the semiconductor substrate is terminated when a time equal to or less than 1/5 of the time has elapsed.
【請求項3】 測定する電極間抵抗値は、任意の一対の
電極間の抵抗値であることを特徴とする請求項1または
2記載の半導体基板の研磨装置。
3. The semiconductor substrate polishing apparatus according to claim 1, wherein the measured inter-electrode resistance is a resistance between an arbitrary pair of electrodes.
JP2001139468A 2001-05-10 2001-05-10 Apparatus for polishing semiconductor wafer Pending JP2002334858A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001139468A JP2002334858A (en) 2001-05-10 2001-05-10 Apparatus for polishing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001139468A JP2002334858A (en) 2001-05-10 2001-05-10 Apparatus for polishing semiconductor wafer

Publications (1)

Publication Number Publication Date
JP2002334858A true JP2002334858A (en) 2002-11-22

Family

ID=18986242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001139468A Pending JP2002334858A (en) 2001-05-10 2001-05-10 Apparatus for polishing semiconductor wafer

Country Status (1)

Country Link
JP (1) JP2002334858A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7029365B2 (en) * 2000-02-17 2006-04-18 Applied Materials Inc. Pad assembly for electrochemical mechanical processing
JP2007083357A (en) * 2005-09-22 2007-04-05 Jtekt Corp Device for measuring thickness of grinding fluid, and grinder using the same
US7670468B2 (en) 2000-02-17 2010-03-02 Applied Materials, Inc. Contact assembly and method for electrochemical mechanical processing
JP2011122230A (en) * 2009-12-14 2011-06-23 Disco Abrasive Syst Ltd Polishing device
JP2011206881A (en) * 2010-03-30 2011-10-20 Disco Corp Polishing device
CN114473859A (en) * 2020-11-11 2022-05-13 中国科学院微电子研究所 Wafer polishing apparatus and wafer polishing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7029365B2 (en) * 2000-02-17 2006-04-18 Applied Materials Inc. Pad assembly for electrochemical mechanical processing
US7670468B2 (en) 2000-02-17 2010-03-02 Applied Materials, Inc. Contact assembly and method for electrochemical mechanical processing
JP2007083357A (en) * 2005-09-22 2007-04-05 Jtekt Corp Device for measuring thickness of grinding fluid, and grinder using the same
JP4677315B2 (en) * 2005-09-22 2011-04-27 株式会社ジェイテクト Grinding fluid thickness measuring apparatus and grinding machine using the apparatus
JP2011122230A (en) * 2009-12-14 2011-06-23 Disco Abrasive Syst Ltd Polishing device
JP2011206881A (en) * 2010-03-30 2011-10-20 Disco Corp Polishing device
CN114473859A (en) * 2020-11-11 2022-05-13 中国科学院微电子研究所 Wafer polishing apparatus and wafer polishing method

Similar Documents

Publication Publication Date Title
KR100196590B1 (en) In situ monitoring technique and apparatus for semiconductor and optical device
EP1116552B1 (en) Polishing apparatus with thickness measuring means
KR100780257B1 (en) Polishing method, polishing apparatus, plating method, and plating apparatus
JP2893012B2 (en) Method and apparatus for planarizing a workpiece
US6620336B2 (en) Polishing pad, polishing apparatus and polishing method
US5637031A (en) Electrochemical simulator for chemical-mechanical polishing (CMP)
US20050173259A1 (en) Endpoint system for electro-chemical mechanical polishing
JPH01207929A (en) Method and apparatus for polishing
CN1246125C (en) End point detection system for mechanical polishing applications
US6375540B1 (en) End-point detection system for chemical mechanical posing applications
JP2002334858A (en) Apparatus for polishing semiconductor wafer
US6923710B2 (en) Apparatus and method for chemical mechanical polishing process
US20130218316A1 (en) Endpoint detector for a semiconductor processing station and associated methods
JP2002025959A (en) Grinding apparatus of semiconductor substrate
US20140093987A1 (en) Residue Detection with Spectrographic Sensor
JP4205914B2 (en) Semiconductor device manufacturing method and manufacturing apparatus
JP2001274126A (en) Polishing apparatus
JP3187162B2 (en) Polishing device and semiconductor device
JPH06120182A (en) Apparatus and method of polishing
KR100808829B1 (en) Chemical mechanical polishing system, methods for monitoring a process state of a wafer surface, and end-point detection method
KR100585070B1 (en) Apparatus for detecting end point during chemical-mechanical polishing process
JP3573197B2 (en) Chemical mechanical polishing station with completion point observation device
KR100223870B1 (en) Monitoring method of polishing in the semiconductor process
JP3962121B2 (en) Chemical / mechanical polishing apparatus and method
JPH09306879A (en) Method of chemically/mechanically making work planar