JPH09306879A - Method of chemically/mechanically making work planar - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of chemically/mechanically making a work planar. SOLUTION: The method of making planar a semiconductor substrate having various material layers comprises pressing and holding the semiconductor substrate to a rotary polishing pad on a rotary surface plate 16 with a polishing slurry to make planar the substrate, controlling the polishing slurry temp. within a range of about 10-30C, distributing the temp.-controlled slurry on the rotary polishing pad 19, measuring the polishing pad temp. at specified pad position for polishing the surface of the substrate by an infrared detecting means, and detecting the end point when the rotary polishing pad temp. changes due to the removal of a first substance and contact of the pad 19 with a second substance.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method and apparatus for determining the end point of a chemical-mechanical process for polishing the surface of a semiconductor wafer. More particularly, the present invention relates to a polishing endpoint determination method for removing a first layer material and stopping the removal process when the second layer material is exposed.

[0002]

In the fabrication of semiconductor elements, metal conductor lines are formed on a substrate containing device circuit elements. This metal conductor line serves to interconnect discontinuous devices, thus forming an integrated circuit. These metal conductor lines are, for example, CVD (chemical vapor deposition) of oxides or SOG (Spin On Glass).
s)) Isolation from the next interconnection level by a thin film of insulation applied by the application of layers and subsequent reflow processes. Pores formed through the insulating layer allow electrical access between successive conductive interconnect layers. In such a wiring process, the layer applied to the rough surface is printed by plane printing.
Surface topography with a smooth insulating layer because it is difficult to draw or pattern (lithographically) the image
It is desirable to have (topography).

Recently, chemical-mechanical polishing (CMP) has been developed to provide smooth surface topography.
CMP can also be used to remove different material layers from the surface of a semiconductor wafer. For example, after forming a via hole in a layer of dielectric material, a metallization layer is blanket deposited and then planarized using CMP.
(planar) Manufacture metal studs. Briefly,
The CMP process uses a thin flat wafer of semiconductor material
Includes holding and spinning against a wet polishing surface under controlled chemistry, pressure and temperature conditions. A chemical slurry containing a polishing agent such as alumina or silica is used as the abrasive. In addition, the chemical slurry contains selected chemistries that etch various surfaces of the wafer during processing. The combination of mechanical and chemical removal of material during polishing results in excellent planarization of the surface being polished. In this process, it is important to remove a sufficient amount of material to form a smooth surface without removing excess material below. Therefore, an accurate method of detecting the polishing end point is needed.

Until now, endpoints have been detected by interrupting the CMP process, removing the wafer from the polisher, and physically inspecting the wafer surface by methods that confirm film thickness and / or surface topography. It was If the wafer does not meet the specifications, it must be re-inserted into the polishing machine for further planarization. If excess material is removed, this wafer will fail to meet specifications and fall below standards. This endpoint detection method is time consuming, unreliable and expensive. Therefore, as shown in the following patents, myriad improvements in endpoint detection during CMP have been invented.

William J. et al. 1993 to Cote
No. 5,23, entitled "Method for Detecting Planarization Endpoints During Chemical-Mechanical Polishing," issued Aug. 10, 2010
No. 4,868 discloses a monitor structure surrounded by a moat. This moat allows polishing removal in the monitor structure to proceed faster than in areas not enclosed by the moat. Polishing proceeds until the top of the monitor structure is exposed, resulting in a layer of planarized insulation on the metal pattern that is not surrounded by motes. A visual inspection is used to confirm the exposure of the top of the monitor structure. Alternatively,
The monitoring is performed electrically by detecting the electrical connection between the metal monitor structure and the polishing pad.

Chris C. Yu et al., "Chemical-Mechanical Planarization (CM) of Semiconductor Wafers Using Acoustic Waves for In-Situ Endpoint Detection", Aug. 31, 1993.
U.S. Pat. No. 5,240,552 entitled "P)"
Sound waves are directed at the wafer during CMP and the planarization process is controlled by analysis of the reflected waveform.

William J. 199 for Cote, etc.
U.S. Pat. No. 5,30, entitled "Method and Apparatus for Endpoint Detection for Chemical-Mechanical Polishing", issued May 3, 4th.
No. 8,438 monitors the electric power required to keep a motor rotating a substrate at a predetermined rotation speed.
The end point can be detected because the power required to keep the motor rotating the substrate at a given rotational speed is significantly reduced once the difficulty to polish the layer is eliminated.

Naftali E. 1 for Lustig
U.S. Pat. No. 5,337,0 entitled "In-situ Endpoint Detection Method and Apparatus for Chemical-Mechanical Polishing with Low Amplitude Input Voltage" issued Aug. 9, 994.
No. 15 uses an electrode incorporated in a polishing pad, a high frequency low voltage signal, and a detection means as a method for measuring the thickness of a dielectric layer to be polished.

Daniel A. 1995 on Koos and others
US Pat. No. 5,413,941 entitled “Optical Endpoint Detection Method in Semiconductor Planarization Polishing Process” issued on May 9, 2010, a laser beam is made to impinge on a substrate to be polished and a reflected beam is measured. A method for detecting the end point of polishing by performing the above is disclosed. The intensity of the reflected ray is a measure of the planarity of the polished surface.

Gurtej S. 19 to Sandhu and others
US Pat. No. 5,196,353 entitled “Control Method of Semiconductor (CMP) Process by Measuring Surface Temperature and Developing Thermal Image of Wafer” issued on Mar. 23, 1993 is a polishing process. Disclosed is the use of infrared detection to measure the surface temperature of a semiconductor wafer therein. Sudden changes in the temperature of the wafer surface during the polishing process can be used to detect endpoints.

The present invention uses chemical / mechanical planarization (CMP) with infrared monitoring of the temperature of the polishing pad.
A novel method for in-situ endpoint detection in Sudden changes in the temperature of the polishing pad are a result of changes in friction between the pad and the surface being polished, such as when one layer is removed and another layer contacts the polishing pad. This method provides a new, inexpensive means for detecting endpoints during CMP and is easily implemented in state-of-the-art polishing equipment.

[0012]

SUMMARY OF THE INVENTION One object of the present invention is to provide a new and improved method of chemical / mechanical planarization (CMP) of a substrate surface, which method comprises a planarization process. The end point is detected by monitoring the temperature of the polishing pad with an infrared temperature measuring device.

It is another object of the present invention that the end point is in-situ in a polishing machine without the need to remove the substrate for visual inspection or time consuming and costly professional measurement of thickness / surface topography. It is to provide a new and improved method of chemical / mechanical planarization (CMP) for detection.

Another object of this invention is the change in polishing pad temperature resulting from changes in friction between the pad and the surface being polished, eg, when one layer is removed and another layer contacts the polishing pad. Chemical / mechanical planarization (CM) using infrared monitoring of polishing pad temperature for detection
P) in order to provide a new and improved method for in-situ endpoint detection. In one embodiment of the present invention, the polishing process is from a soft and easily abraded material, such as PE-TEOS (plasma enhanced oxide deposition from tetraethylorthosilicate) to a hard, hard abraded material, such as SOG (Spin). The end point is detected when the temperature of the polishing pad rises as it progresses to (-On-Glass). In a second embodiment of the present invention, the polishing process is made from a material that is difficult to polish, such as tungsten,
The endpoint is detected when the polishing pad temperature decreases as it progresses to a more easily polished material, such as titanium nitride.

[0015]

In a specific embodiment,
An apparatus for practicing the method of the present invention comprises a wafer carrier for chemical / mechanical planarization (CMP) of a semiconductor wafer and a rotary polishing platen; means for controlling the temperature of the chemical / mechanical polishing slurry; Means for distributing the chemical / mechanical polishing slurry onto the polishing pad; monitoring the polishing pad temperature and when the removal of the first substance and the contact of the rotating polishing pad with the second substance cause a temperature change of the rotating polishing pad. And an infrared temperature detection device for detecting the end point.

The objects and other advantages of the present invention will be better understood when the following preferred embodiments are considered with reference to the accompanying drawings.

A method of planarizing (CMP) the surface of a semiconductor substrate using chemical / mechanical polishing and a novel endpoint detection method,
The improved method will be described in more detail. This method involves depositing an insulator surface, such as silicon oxide or silicon nitride, on a semiconductor device and / or conductor interconnect wiring pattern by chemical vapor deposition,
Alternatively, it can be used to planarize an insulator layer, such as glass, deposited by spin-on and reflow deposition means.

[0018]

1 and 2 are schematic diagrams of a chemical / mechanical planarization (CMP) apparatus for use with the method of the present invention. In FIG. 1, a CMP device (generally, 1
(Denoted as 0) is schematically shown as a cross-sectional view. The CMP apparatus 10 includes a wafer carrier 11 for holding a semiconductor wafer 12. Wafer carrier 11 is arrow 1
By the drive motor 14 in the direction indicated by 3.
It is mounted for continuous rotation about axis A1.
The wafer carrier 11 is adjusted so that the force indicated by the arrow 15 is exerted on the semiconductor wafer 12. CMP apparatus 10 includes a polishing platen 16 mounted for continuous rotation about axis A2 by drive motor 18 in the direction indicated by arrow 17. A polishing pad 19 made of a material such as blown polyurethane is attached to the polishing platen.
A polishing slurry containing a polishing fluid, such as silica or alumina polishing particles suspended in a basic or acidic solution, is dispensed from a temperature controlled reservoir 21 via a flow path 20 onto a polishing pad 19. An infrared detection device 22 is attached to detect infrared rays emitted from a region 23 indicated by X. Region 23 traces an annular ring 24 on polishing pad 19 as shown in FIG. 2 due to continuous rotation of polishing pad 19. The location of region 23 is within the portion of polishing pad 19 that wears semiconductor wafer 12 during rotation of polishing pad 19.

2, which is a schematic plan view of the CMP apparatus 10 shown in FIG. 1, shows important elements. The wafer carrier 11 is shown rotating about axis A1 in the direction indicated by arrow 25. The polishing platen 16 has an arrow 26.
It is shown rotating about axis A2 in the direction indicated by. The polishing slurry is stored in a temperature controlled reservoir 2.
1 to the polishing pad 19 through the flow path 20. The infrared detection device (shown in FIG. 1) receives infrared light emitted from region 23 (denoted by X). Region 23 represents a portion of the region of polishing pad 19 within annular ring 24.

3 and 4, which are schematic sectional views, show P
Metallized MO with a composite dielectric overlayer of E-TEOS / SOG / PE-TEOS deposited
3 illustrates chemical / mechanical planarization (CMP) of a semiconductor wafer containing SFET devices. Typical N shown in FIG.
FET (N-type field effect transistor) device
A semiconductor wafer 12 composed of P-type single crystal silicon having a <100>orientation; a thick field oxide region 30 (FOX); a polysilicon gate 31.
Gate oxide 32; source region and drain region 33
And; sidewall spacers 34; LPCVD deposited layers of silicon oxide 35 and silicon nitride 36;
vel) connection plug 37; conductive interconnection pattern 38
A first PE-TEOS layer 39, a SOG layer 40, and a second PE-TEOS layer 41. First PE-TEO
The S layer 39 is made of tetraethyl orthosilicate and has a thickness of about 20.
At a temperature of 0 to 400 ° C., about 2,000 to 5,000
Deposited by plasma-enhanced deposition to a thickness of 0Å. The SOG layer 40 is about 2 to 4 of spin-on-glass.
Application of the layer followed by reflow at a temperature of about 250-450 ° C. results in a thickness of about 4,000-8,000 Å. The second PE-TEOS layer 41 is deposited from tetraethyl orthosilicate at a temperature of about 200-400 ° C. to a thickness of about 2,000-5,000Å by plasma enhanced deposition. Planarization of the surface topography 42 shown in FIG. 3 is accomplished by chemical / mechanical planarization (CMP) in an apparatus such as those generally shown in FIGS.
Performed to produce a substantially planar SOG surface 43 as shown in FIG.

The method of endpoint detection during chemical / mechanical planarization (CMP) of surface topography 42, shown in FIG. 3, will now be described in detail. With respect to FIGS. 1 and 2, included in reservoir 21, for example, the commercially available Cabot SC-1.
[PH 10.0 to 10.3; specific gravity 1.198 ± 0.0
A polishing slurry such as 12 cp; abrasive particles SiO ₂ ; chemical substance KOH] is adjusted within a temperature range of about 10 to 30 ° C. and distributed through the flow path 20 so as to saturate the polishing pad 19. The infrared detection device 22 is the polishing pad 1
The temperature of the area 23 above 9 is measured. Second PE-TEOS
The semiconductor wafer 12 is placed in the polishing apparatus 10 with the layer 41 facing down with respect to the polishing pad 19. The polishing platen motor 18 has its speed set at about 10-70 rpm and the wafer carrier drive motor 14 has about 10-7.
It is set to rotate at a speed of 0 rpm. The wafer carrier 11 has a pressure of 1 between the wafer and the polishing pad.
5 is set to exert a pressure of about 1-10 psi.

A method of using the measured temperature of the polishing pad to detect the endpoint is shown in FIG. 5, which shows infrared detection when using chemical / mechanical polishing to planarize the surface of a semiconductor wafer. 7 shows the behavior of the polishing pad temperature versus time. As the second PE-TEOS layer 41 first begins to be polished, the temperature of the polishing pad, as indicated by 50, is due to friction between the fibers of the pad, the abrasive particles of the polishing slurry, and the PE-TEOS layer. Rises. The temperature of the polishing pad is PE, as indicated by 51.
-Remains at a substantially constant level during polishing of the TEOS layer. The polishing pad is SOG, which is a more difficult substance to polish
Upon contact with the layer 40, the friction between the fibers of the pad, the abrasive particles of the abrasive slurry, and the surface being abraded increases, and the temperature of the polishing pad also increases, as indicated by 53. Finally, the temperature of the polishing pad flattens out at high values, as indicated by 54, which is a result of the high friction between the fibers of the pad, the abrasive particles of the polishing slurry, and the SOG layer 40. . The endpoint (E.P.) is selected as the time at which the polishing pad temperature demonstrates that the second PE-TEOS layer 41 has been removed. SOG obtained
Surface 43 is substantially planar.

The second embodiment of the present invention will be described below. FIGS. 6 and 7, which are schematic cross-sectional views, show chemical / mechanical planarization (CMP) of a semiconductor substrate 12 coated with a silicon oxide layer 60 that includes openings 61 and 62. Openings 61 and 6
2 contacts an active device or metal interconnection level.
Active devices or metal interconnection levels are not shown here as they are not relevant to the present invention. Deposited on the oxide 60 is a composite layer of barrier material including a titanium layer 63 and a titanium nitride layer 64. The formation of such a barrier layer is common in the industry, and titanium targets (titanium
It can be attached by sputtering from the target). These layers are deposited separately by first forming titanium nitride by sputtering from a titanium target in an inert atmosphere (eg argon) and then by sputtering from a titanium target in a nitrogen atmosphere. Or a titanium layer is deposited first, which is exposed to a nitrogen atmosphere to form a titanium nitride layer thereon. The thickness of the barrier layer is about 100 to 500Å for the titanium layer 63 and about 500 to 2,000Å for the titanium nitride layer 64. Approximately 2,000-10,000 by LPCVD using WF ₆ on the titanium nitride layer 64 with a flow of approximately 40-100 sccm at a temperature of approximately 300-500 ° C.
Deposit tungsten 65 to a thickness of Å. Opening 6
It is important to deposit a tungsten layer that is thick enough to completely fill 1 and 62. In this regard, the LPCVD process is effective because it results in tungsten film growth on both vertical and horizontal surfaces.

As schematically illustrated in FIGS. 1 and 2, the semiconductor substrate 12 is placed in a polishing apparatus with the tungsten layer 65 facing downwards with respect to the polishing pad 19. With reference to FIGS. 1 and 2, about 10-30 polishing slurries consisting of Al ₂ O ₃ and chemicals [aqueous solution of ferric nitrate] contained in reservoir 21.
The temperature is adjusted within a temperature range of 0 ° C., and the polishing pad 19 is dispensed so as to be saturated. Infrared detection device 2
2 measures the temperature of the region 23 on the polishing pad 19. The polishing platen motor 18 has its speed set at about 10-70 rpm and the wafer carrier drive motor 14
Is set to rotate at a speed of about 10-70 rpm. The wafer carrier 11 is set to exert a pressure of about 1-10 psi by applying a pressure 15 between the wafer and the polishing pad. Chemical / mechanical polishing (CMP) proceeds until all the tungsten 65 in the openings 61 and 62 is removed except for tungsten.

A method of using the measured temperature of the polishing pad to detect the endpoint in this second embodiment of the invention is shown in FIG. 8, which removes tungsten 65 everywhere except openings 61 and 62. Shows the behavior of infrared detected polishing pad temperature versus time when using chemical / mechanical polishing to do so. When the tungsten 65 is first polished, the fibers of the pad and the abrasive particles of the abrasive slurry,
The friction between the tungsten layer causes the temperature of the polishing pad to rise, as indicated by 70. The temperature of the polishing pad remains at a substantially steady level during polishing of the tungsten layer, as indicated by 71. Titanium nitride layer 6 whose polishing pad is a material that is less difficult to polish
Upon contact with 4, the friction between the fibers of the pad, the abrasive particles of the abrasive slurry, and the surface being abraded is reduced and the temperature of the polishing pad is also reduced, as indicated by 72.
Finally, the temperature of the polishing pad flattens out at low values, as indicated by 73, which is a result of the low friction between the fibers of the pad, the polishing particles of the polishing slurry, and the titanium nitride layer 64. is there. The end point (E.P.) is selected as the time at which the polishing pad temperature demonstrates that the tungsten layer 65 has been removed. Slight overpolishing beyond the end point detected is then easily polished titanium nitride 6
4 and titanium 63 are removed and the resulting planar structure has tungsten connecting studs embedded in oxide, as shown in FIG.

While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be appreciated by those skilled in the art that various changes in form and detail can be made without departing from the spirit and scope of the invention. .

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a polishing apparatus used by the method of the present invention.

FIG. 2 is a plan view of the device described in FIG.

FIG. 3 is a schematic cross-sectional view illustrating planarization of the surface of a composite dielectric layer on a semiconductor substrate.

FIG. 4 is a schematic cross-sectional view illustrating planarization of the surface of a composite dielectric layer on a semiconductor substrate.

FIG. 5 shows infrared detected polishing pad temperature versus time behavior when chemical / mechanical polishing is used to planarize the surface of a composite dielectric layer on a semiconductor substrate, displaying preferred endpoints.

FIG. 6 is a schematic cross-sectional view illustrating the formation of tungsten contact studs embedded in silicon oxide by chemical / mechanical polishing.

FIG. 7 is a schematic cross-sectional view illustrating the formation of tungsten contact studs embedded in silicon oxide by chemical / mechanical polishing.

FIG. 8 shows infrared detected polishing pad temperature versus time behavior and shows preferred endpoints when using chemical / mechanical polishing to form planar tungsten contact studs embedded in silicon oxide. Figure to do.

[Explanation of symbols]

 10. Chemical / mechanical planarization (CMP) equipment 11. Wafer carrier 12. Semiconductor wafer 14. Drive motor 16. Polishing surface plate 18. Drive motor 19. Polishing pad 20. Flow path 21. Temperature controlled reservoir 22. Infrared detection device 23. Infrared emitting region 24. Annular ring 30. Thick field oxide region 31. Polysilicon gate 32. Gate oxide 33. Source area and drain area 35. LPCVD adhesion layer of silicon oxide 36. Silicon nitride 37. Inter-level connection plug 38. Conductive interconnection pattern 39. First PE-TEOS layer 40. SOG layer 41. Second PE-TEOS layer 42. Surface topography

Claims (28)

[Claims] 1. A method for chemical / mechanical planarization (CMP) of a semiconductor substrate comprising layers of various materials, the method comprising the steps of: placing the semiconductor substrate on a rotating platen in the presence of a polishing slurry. Planarizing the semiconductor substrate by pressing and holding it on a rotating polishing pad; controlling the temperature of the polishing slurry within a temperature range of about 10 to 30 ° C .; Distributing above; measuring the temperature of the rotary polishing pad at a specific polishing pad position that abrades the surface of the semiconductor substrate by infrared detection means; removing the first substance, and using the rotary polishing pad Detecting an end point when a change in temperature of the rotating polishing pad occurs due to contact with a second material. 2. The polishing slurry is SiO ₂ or CeO ₂
And the method of claim 1, comprising NH ₃ or KOH. 3. The temperature of the rotary polishing pad is about 10.
The method according to claim 1, which is measured in a temperature range of -80 ° C. 4. The method according to claim 1, wherein the first substance is a hard substance that is difficult to polish, and the second substance is a soft substance that is easy to polish. 5. Removal of the hard and difficult to polish material,
The method of claim 4, wherein the endpoint is detected as a decrease in temperature of the rotary polishing pad due to contact with the soft, easy-to-polish material by the rotary polishing pad. 6. The method according to claim 1, wherein the first substance is a soft substance that is easy to polish, and the second substance is a hard substance that is difficult to polish. 7. Removal of the soft and easy to polish material,
7. The method of claim 6, wherein the end point is detected as an increase in temperature of the rotary polishing pad due to contact with the hard, hard-to-polish material by the rotary polishing pad. 8. A method of forming a planarization layer of a dielectric material on a semiconductor substrate including a structure, comprising the steps of: forming the structure on the semiconductor substrate; and including the structure. Depositing a first layer of dielectric material on a semiconductor substrate; a second layer of dielectric material that is easier to polish than the first layer of dielectric material on the first layer of dielectric material Depositing the semiconductor substrate on the rotating platen in the presence of a polishing slurry and a pressure force between the platen and the polishing pad by holding the semiconductor substrate against the rotating polishing pad. Planarizing the second layer of material; controlling the temperature of the polishing slurry within a temperature range of about 10 to 30 ° C .; distributing the temperature controlled slurry on the rotating polishing pad; The surface of the second layer of dielectric material is abraded. Measuring the temperature of the polishing pad at the worn position by means of infrared detection means; detecting the end point of the planarization process when the temperature of the polishing pad rises due to the removal of the second layer material that is easily polished The method comprising the steps of: 9. The method of claim 8, wherein the structure is an active device. 10. The method of claim 8, wherein the structure is a conductive material in an interconnect pattern. 11. The method of claim 8, wherein the structure comprises both active devices and conductive material in an interconnect pattern. 12. The active device is an NFET or PF.
9. The method of claim 8, which is an ET MOS device. 13. The method of claim 10, wherein the conductive material of the interconnect pattern is aluminum having a thickness of about 4,000 to 10,000Å. 14. The first layer should be a dielectric material that is difficult to polish, the second layer (on top) should be a dielectric material that is easy to polish, and the dielectric material of the second layer should be 9. The method of claim 8, wherein the SOG is applied as about 2-4 layers and then reflowed at a temperature of about 250-450 [deg.] C. resulting in a thickness of about 4,000-8,000 Å. 15. The first layer should be a dielectric material that is difficult to polish, the second layer (on top) should be a dielectric material that is easy to polish, and the dielectric material of the second layer should be 9. The method of claim 8 which is PE-TEOS deposited from tetraethyl orthosilicate to a thickness of about 2,000-5,000Å at a temperature of about 200-400 ° C. 16. The polishing slurry is SiO ₂ or Ce.
O ₂ and includes a NH ₃ or KOH, is controlled within a temperature range of about 10 to 30 ° C., The method of claim 8. 17. The rotating polishing pad comprises about 10-70r.
9. The method according to claim 8, rotating in the range of pm. 18. The method of claim 8 wherein said rotating platen rotates within a range of about 10-70 rpm. 19. The method of claim 8 wherein the applied pressure between the platen and the polishing pad is in the range of about 1-10 psi. 20. The temperature rise of the polishing pad is about 10 to 10.
The method according to claim 8, which is in the range of 30 ° C. 21. A first layer material having a first coefficient of friction deposited on a second layer material having a second coefficient of friction,
A method of forming a planarization layer on a semiconductor substrate, wherein the first coefficient of friction is greater than the second coefficient of friction, comprising the steps of: separating the semiconductor substrate between a polishing slurry, a polishing plate and a polishing plate. Planarizing the semiconductor substrate by holding it against a rotating polishing pad on a rotating platen in the presence of a pressure; a polishing slurry temperature of about 1
Controlling within a temperature range of 0 to 30 ° C .; distributing the temperature-controlled slurry on the rotating polishing pad; temperature of the polishing pad at a position where the surface of the dielectric material of the first layer is abraded. By an infrared detection means; and detecting the end point of the planarization process when the temperature of the polishing pad decreases due to the removal of the material of the first layer. 22. The material of the first layer is about 350-500.
About 2,000 to 1 using LPCVD at a temperature of ℃
22. The method of claim 21, which is tungsten deposited to a thickness of 10,000 Å. 23. The material of the second layer is about 200-700.
Using PVD or CVD at a temperature of about 500 ~ 500 ~
Titanium nitride deposited to a thickness of 2,000Å,
A method according to claim 21. 24. The polishing slurry comprises Al ₂ O ₃ and NH ₃
25. The method of claim 24, which further comprises KOH and is controlled within a temperature range of about 10-30 <0> C. 25. The rotary polishing pad is about 10-70r.
22. The method of claim 21, rotating in the range of pm. 26. The method of claim 21, wherein the turn table rotates within a range of about 10-70 rpm. 27. The method of claim 21, wherein the applied pressure between the platen and the polishing pad is in the range of about 1-10 psi. 28. The temperature drop of the polishing pad is about 10 to 10.
22. The method of claim 21, which is in the range of 30 <0> C.