JP3962121B2 - Chemical / mechanical polishing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus and method for chemically / mechanically polishing (CMP) the surface of a semiconductor substrate. More particularly, the present invention eliminates removing a substrate from a CMP apparatus when polishing a semiconductor substrate that includes topographic features resulting from a deposited and patterned layer to a flat state. The present invention relates to a chemical / mechanical polishing (CMP) apparatus including an in-line type flatness measuring apparatus capable of detecting a flattening completion point.
[0002]
[Prior art]
In the assembly of semiconductor devices, metal conductor lines are used to interconnect many components in the device circuit. The metal conductor lines serve to interconnect separate devices, thereby forming an integrated circuit. The metal conductor line is further insulated from the next connection level by a thin layer of insulating material, and holes formed through the insulating layer form an electrical access between successive conductive connection layers. In such a wiring process, it is difficult to form an image and a pattern in a lithographic manner on a layer adhered to the rough surface, and therefore it is desirable that the insulating layer has a smooth surface topography (shape). Also, if the surface topography is rough, there will be defects in step coverage due to the next deposited layer, the layer crossing the step will be discontinuous, and voids will be formed between the topographic features . Defects in step coverage and void formation between topographic features due to the deposited layers reduce process yield and reduce integrated circuit reliability. As the wiring density of semiconductor circuit chips increases, devices must be connected at multiple wiring levels, and therefore, planarization of the dielectric between levels becomes a critical step in the assembly process.
[0003]
In semiconductor circuit manufacturing, chemical / mechanical polishing (CMP) is a process performed to reveal a smooth surface topography on the insulating layer separating the conductive connection pattern layers. CMP can also be used to remove different material layers from the surface of a semiconductor substrate. For example, following formation of a hole through the insulating material layer, a metallization layer is deposited together, and then a flat metal stud is formed using CMP. In brief, in the CMP process, a thin flat substrate made of a semiconductor material is held under controlled conditions of chemical properties, pressure and temperature, and the substrate is rotated against a wet polishing surface. A chemical slurry containing an abrasive such as alumina or silica is used as the abrasive material. In addition, the chemical slurry includes chemicals selected to etch various surfaces of the substrate during processing. During polishing, a combination of mechanical and chemical effects removes material, resulting in excellent planarization of the polished surface. During the polishing process, it is important to remove a sufficient amount of material to provide a smooth surface without excessively removing the underlying material. Therefore, a method for detecting when the planarization is achieved is needed.
[0004]
U.S. Pat. No. 5,413,941 entitled “Optical Completion Point Detection Method for Semiconductor Flattening Polishing Method”, given to Daniel A. Koos et al. On May 9, 1995, A polishing completion point detecting method is described in which a laser beam is applied to a substrate being polished and the reflected light is measured. The intensity of the reflected light provides a measure of the flatness of the polished surface.
[0005]
Insulating layer chemical / mechanical planarization has also been monitored by measuring the thickness of the insulating layer and correlating the amount of layer removed with the planarization state. This is not a reliable method because the CMP process relies on pattern density that produces rough topography to be planarized. Consider an object whose topography changes in both height (thickness) characteristics and lateral dimension (size) characteristics. The CMP polishing removal rate is greater for features with high height than for features with low height. Further, the flattening of the surface feature is determined by the horizontal dimension when the height of the feature is constant. If the lateral dimension is small, the local polishing removal rate on the small feature is greater than the local polishing rate on the large lateral feature. In addition, the local polishing removal rate on topography features is also affected by the proximity of multiple topography features. For example, a separated feature of a given height is polished faster than a similar feature that surrounds it in close proximity to the array. Obviously, it is insufficient to simply monitor the thickness of the material removed during chemical / mechanical polishing of the semiconductor device structure to confirm planarization. Each level of the semiconductor device structure has a different pattern density, which may vary locally and globally on the semiconductor substrate. Therefore, simply measuring the thickness of material removed during CMP on portions of the substrate is not sufficient to predict planarization.
[0006]
Planarization is achieved without off-line inspection, flatness measurement and polishing layer thickness measurement after removing the product from the CMP apparatus in order to reduce processing costs and increase the throughput of the product in the CMP apparatus. It is desirable to be able to measure the point in time.
[0007]
The present invention relates to a novel method and apparatus for performing chemical / mechanical polishing (CMP) of a semiconductor substrate that includes topographic features arising from deposited and patterned layers. A new and improved CMP apparatus includes an inline substrate cleaning station and an inline optical thickness measurement station. A new and improved method for detecting CMP planarization completion points when planarizing a semiconductor substrate containing topography features to planarize various insulator layers regardless of topography pattern density. Adaptable. The CMP apparatus includes a state-of-the-art chemical / mechanical polishing station, a substrate cleaning station, and a simple optical film thickness measuring device. The completion point of the planarization of the substrate surface is detected by monitoring the ratio of the insulating material removal rate on the pattern feature to the insulating material removal rate on the region where the pattern feature does not exist below.
[0008]
SUMMARY OF THE INVENTION
An object of the present invention is to detect the completion point of the planarization process by monitoring the ratio of the insulating material removal rate on the pattern feature to the insulating material removal rate on the region where the pattern feature does not exist below. It is possible to provide an improved and novel apparatus and method for chemical / mechanical polishing (CMP) of a semiconductor substrate surface to a flat state.
Another object of the present invention is to detect completion points in a CMP process for planarizing an insulating layer deposited on a patterned metallization layer used to connect separate devices on a semiconductor substrate. It is a new and improved apparatus and method.
Still another object of the present invention is to provide an in-line substrate cleaning station, a simple optical film thickness measuring device, an insulating material removal rate on a pattern feature, and an insulating material removal rate on an area where no pattern feature exists below. And providing a new and improved CMP apparatus with means for measuring the ratio.
[0009]
The novel features of the polishing apparatus according to the present invention include a rotatable platen and polishing pad for chemically / mechanically polishing (CMP) an insulating layer deposited on a metallization pattern formed on the surface of a semiconductor substrate, and polishing. A slurry reservoir and means for supplying the slurry to the polishing pad; a rotatable substrate carrier; and applying pressure between the substrate carrier, the rotatable platen, and the polishing pad, and applying a pressure to the surface of the semiconductor substrate. Means for holding the semiconductor substrate in parallel to a rotating polishing pad; means for transporting the semiconductor substrate from the rotatable substrate carrier to an in-line cleaning station having a water spray nozzle and an air spray nozzle; and Means for conveying from an in-line cleaning station to an in-line optical thickness measuring instrument; Means for aligning in the thickness measuring tool, means for measuring the thickness of the insulating layer on the metallized pattern before and after polishing, and thickness of the insulating layer on the semiconductor substrate before and after polishing Measuring means, means for calculating a first polishing removal rate of the insulating layer on the metallized pattern, means for calculating a second polishing removal rate of the insulating layer on the semiconductor substrate, Means for dividing a first polishing removal rate by the second polishing removal rate to calculate a polishing removal rate ratio; and transporting the semiconductor substrate from the in-line optical thickness measurement tool to the rotatable substrate carrier. And means for further performing chemical / mechanical polishing (CMP) until the polishing removal rate ratio is less than about 0.9 to 1.1.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Polishing the surface of a semiconductor substrate using chemical / mechanical polishing (CMP) that achieves improved planarization detection regardless of topography pattern density and does not unduly remove the underlying material The new and improved apparatus and method will now be described in detail.
[0011]
FIG. 1 is a schematic diagram of a combination of a state-of-the-art CMP apparatus 10, an inline substrate cleaning station 11, and an optical film thickness measuring apparatus 12. During the CMP process, the substrate 13 is polished on the polishing pad 14 for a predetermined time, and then the substrate 13 is transferred to an in-line substrate cleaning station 11 with a water spray nozzle 15 and an air spray nozzle 16. . Then, the water spray nozzle 15 is activated to wash away the polishing slurry from the substrate surface, and then the air spray nozzle 16 is activated to dry the substrate surface. The substrate 13 is transported to the optical film thickness measuring device 12 after being cleaned and dried. As is normally performed, the substrate is oriented and positioned at a position defined with respect to the optical film thickness measuring device using the flat portion of the substrate.
[0012]
As shown in FIGS. 2A and 2B, the flattening monitoring structure includes an optical measurement alignment mark having a first region 20 in which a topography generating feature is not present below and a second region 21 in which a topography generating feature is present below. It is. The lateral dimensions of this optical measurement alignment mark are about 100 μm × 100 μm for the first region 20 and about 100 μm × 100 μm for the second region 21. The lateral dimension of the two areas of the alignment mark is measured in its original position on the CMP polisher without the need for undue costly optical positioning by optical thickness detection techniques such as optical or lightwave interference. Selected so that it can be implemented. Next, the lateral dimension of the second region 21 with the topographical generation feature below ensures that planarization on this feature is achieved to ensure planarization in all critical regions of the semiconductor device structure. Is selected. The lateral dimensions of the portion where the topography-generating features are below about 100 μm × 100 μm meet this criterion, but these dimensions can be changed to meet the predetermined needs of the process. . For example, a lateral dimension between about 50 and 1000 μm is suitable for those having topographic features below.
[0013]
The optical measurement alignment mark occurs at a defined position relative to a defined substrate feature, such as a substrate flat or notch on a silicon wafer substrate. Both flat and notched portions of silicon substrates are commonly used in the semiconductor industry. By placing the optical measurement alignment mark at a position determined for the substrate features such as the flat part of the semiconductor substrate, the position of the optical measurement alignment mark is always well defined, and the optical measurement device is compared Therefore, it is possible to easily concentrate on the alignment mark.
[0014]
Referring again to FIGS. 2A and B, FIG. 2A shows a top view of an optical measurement alignment mark comprising a first region 20 having no topographic features and a second region 21 having topographic features 22. Yes. The lateral dimension of the topographic feature 22 is approximately 100 μm × 100 μm. The horizontal dimension of the first region 20 is about 100 μm × 100 μm. The optical measurement alignment mark including the first region 20 and the second region 21 is formed at a position defined with respect to the flat portion 23 on the semiconductor substrate 24. FIG. 2B shows a cross-sectional view of the optical measurement alignment mark shown in FIG. 2A.
[0015]
FIG. 3 schematically illustrates the use of optical alignment marks to monitor planarization during chemical / mechanical polishing of semiconductor device structures. FIG. 3 is a cross section of the monitoring structure before polishing. The first insulator 30 is formed by a method common in the semiconductor industry, such as CVD (chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or PECVD (plasma chemical vapor deposition). A suitable method for forming the first insulator 30 is CVD, in which the temperature is 200 to 450 ° C. and the thickness is about 2,000 to 20,000 angstroms. Alternatively, the first insulator 30 can be adhesively molded by SOG (spin on glass) and reflow techniques that are also common in the semiconductor industry. The topographic feature 31 comprises a metal island having a lateral dimension of about 100 μm × 100 μm and is formed by patterning and then etching a blanket metal layer. The thickness of the metal layer is about 3,000 to 8,000 angstroms. The topography feature 31 is formed at the same time as the connection wiring pattern made of aluminum or aluminum-copper-silicon is formed on the semiconductor substrate. The second insulator 32 is shaped to coincide on the first insulator 30, the topography feature 31, and the connection wiring pattern (not shown because it is not part of the present invention). The second insulator 32 is formed by a method common in the semiconductor industry, such as CVD (chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or PECVD (plasma chemical vapor deposition). A suitable method for forming the second insulator 32 is CVD, in which the temperature is 200 to 450 ° C. and the thickness is about 2,000 to 20,000 angstroms. Alternatively, the second insulator 32 can be formed by SOG (spin-on-glass) and reflow techniques commonly used in the semiconductor industry. Initial insulator thickness measurements are performed in the region 34 above the topography feature 31 and the region 33 without the topography feature. It is also possible to measure the initial insulator thickness using optical interference commonly used in the semiconductor industry.
[0016]
Referring to FIGS. 1 and 3, chemical / mechanical polishing (CMP) of the second insulator 32 is performed with a polishing slurry composed of abrasive particles such as silica or alumina, and a pH of about pH = 9 to pH = 14. The situation is illustrated as being performed over a predetermined time using a chemical etchant. The rotatable platen and polishing pad 14 are rotated at a speed of about 10-100 rpm. The pressure applied between the rotatable substrate carrier, the rotatable platen, and the polishing pad is about 0.00703 to 0.7031 kgf / cm ² (about 0.1 to 10 psi). Following a predetermined time of chemical / mechanical polishing, the semiconductor substrate is transferred from the rotatable substrate carrier to an in-line cleaning station 11 with a water spray nozzle 15 and an air spray nozzle 16. By operating the water spray nozzle 15, the polishing slurry is washed away from the substrate surface, and then the substrate surface is dried by activating the air spray nozzle 16. After the substrate 13 is cleaned and dried, it is transported to the optical film thickness measuring device 12, where the thickness of the insulator in the region 34 above the topography feature 31 and the region 33 without the topography feature is again determined by the optical interference technique. Is measured. For illustrative purposes, the initial topographic surface will be denoted by I and the first polished topographic surface will be denoted by 1. The CMP material removal rate is calculated for both regions 33 and 34 by subtracting the corresponding insulator thickness after CMP from the initial insulator thickness and then dividing the resulting difference by the polishing elapsed time. The CMP polishing removal rate ratio is then calculated by dividing the removal rate in region 34 by the removal rate in region 33. Typically, the removal rate of region 34 is greater than the removal rate of region 33, indicating that planarization is in progress. Further, the polished topography surface is represented by reference numerals 2 and 3, respectively, which indicates that the progress of planarization is further advanced. A new material removal rate is calculated for regions 33 and 34 after each polishing is repeated. The ratio of the CMP polishing removal rate is also calculated after each polishing is repeated. The CMP polishing removal rate ratio typically progresses from a large value to a value approximating 1.00 as planarization progresses. Further chemical / mechanical polishing is performed until such polishing removal rate ratio is below 0.9 to 1.1. Alternatively, the ratio of the second polishing removal rate can be calculated by dividing the removal rate of the region 33 by the removal rate of the region 34, and the ratio of the second polishing removal rate is 1.1-0. Further chemical / mechanical polishing is performed until 9 is exceeded.
[0017]
Although the invention has been illustrated and described in detail with reference to preferred embodiments, those skilled in the art will recognize that various changes in aspects and details can be made without departing from the spirit and scope of the invention. It is self-evident.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a CPM device of the present invention.
FIG. 2 is a schematic top view and cross-sectional view of an optical alignment mark of the present invention.
FIG. 3 is a schematic cross-sectional view showing a flattening progress state in an optical alignment mark when CPM is continuously executed.

Claims (38)

In an apparatus for planarizing a semiconductor substrate,
A rotatable platen and polishing pad for chemically / mechanically polishing (CMP) an insulating layer deposited on a metallization pattern formed on a surface of a semiconductor substrate;
A polishing slurry reservoir and means for supplying the slurry to the polishing pad;
A rotatable substrate carrier, and a surface of the semiconductor substrate in parallel with the rotatable polishing platen and the polishing pad while applying pressure between the rotatable substrate carrier and the rotatable platen and the polishing pad. Means for holding;
Means for transporting the semiconductor substrate from the rotatable substrate carrier to an in-line cleaning station comprising a water spray nozzle and an air spray nozzle;
Means for transporting the semiconductor substrate from the inline cleaning station to an inline optical thickness measuring tool;
Means for positioning the semiconductor substrate within the in-line optical thickness measuring tool;
Means for measuring the thickness of the insulating layer on the metallization pattern before and after polishing;
Means for measuring the thickness of the insulating layer on the semiconductor substrate before and after polishing;
Means for calculating a first polishing removal rate of the insulating layer on the metallization pattern;
Means for calculating a second polishing removal rate of the insulating layer on the semiconductor substrate;
Means for dividing the first polishing removal rate by the second polishing removal rate to calculate a polishing removal rate ratio;
The semiconductor substrate is transported from the in-line optical thickness measuring tool to the rotatable substrate carrier, and further subjected to chemical / mechanical polishing until the polishing removal rate ratio is less than 0.9 to 1.1 ( And an apparatus for performing CMP).   2. The apparatus of claim 1, wherein the rotatable platen and polishing pad rotate at a speed of 10 to 100 rpm.   The apparatus of claim 1, wherein the rotatable substrate carrier rotates at a speed of 10 to 100 rpm. The apparatus of claim 1, wherein the pressure applied between the rotatable substrate carrier, the rotatable platen and the polishing pad is 0.1 to 10 psi.   The apparatus according to claim 1, wherein the polishing slurry comprises a chemical etchant having a pH of 9-14.   2. The apparatus of claim 1, wherein the metallization pattern comprises metal islands having a length and width dimension of 50 to 1,000 [mu] m.   The apparatus of claim 1, wherein the metallized pattern has a thickness of 3,000 to 8,000 angstroms.   The apparatus of claim 1, wherein the insulating layer is silicon oxide.   2. The apparatus according to claim 1, wherein the means for measuring the thickness of the insulating layer on the metallized pattern is an optical interference means.   2. The apparatus according to claim 1, wherein the means for measuring the thickness of the insulating layer on the semiconductor substrate is an optical interference means. In a method of chemically / mechanically polishing a semiconductor substrate (CMP),
Depositing and molding a first insulating layer on the semiconductor substrate;
Forming a metallization pattern on the first insulating layer;
Attaching and forming a second insulating layer on the first insulating layer and the metallization pattern so as to coincide;
Measuring the thickness of the second insulating layer on the metallization pattern;
Measuring the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate;
Chemically / mechanically polishing (CMP) the second insulating layer;
Transporting the semiconductor substrate to an in-line cleaning station with a water spray nozzle and an air spray nozzle;
Removing polishing slurry from the semiconductor substrate with water from the water spray nozzle;
Drying the semiconductor substrate with air from the air spray nozzle;
Transporting the semiconductor substrate to an inline optical thickness measuring tool;
Aligning the semiconductor substrate within the optical thickness measurement tool;
After chemical / mechanical polishing (CMP), again measuring the thickness of the second insulating layer on the metallization pattern;
After chemical / mechanical polishing (CMP), measuring again the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate;
Calculating a first polishing removal rate of the second insulating layer on the metallization pattern;
Calculating a second polishing removal rate of the second insulating layer on the semiconductor substrate;
Dividing the first polishing removal rate by the second polishing removal rate to calculate a polishing removal rate ratio;
Further applying chemical / mechanical polishing (CMP) until the polishing removal rate ratio is less than 0.9-1.1.   12. The method of claim 11, wherein the first insulating layer is silicon oxide.   13. The method of claim 12, wherein the silicon oxide is deposited using a CVD (chemical vapor deposition) method at a temperature of 200 to 450 degrees to a thickness of 2,000 to 20,000 angstroms. Feature method.   12. The method according to claim 11, wherein the metallization pattern comprises metal islands having a length and width dimension of 50 to 1,000 [mu] m. 15. The method of claim 14, wherein the metal island has a thickness of 3,0.
A method characterized in that it is from 00 to 8,000 angstroms.   15. The method of claim 14, wherein the metal island is aluminum.   15. The method of claim 14, wherein the metal island is aluminum-copper-silicon.   12. The method of claim 11, wherein the second insulating layer is silicon oxide.   19. The method of claim 18, wherein the silicon oxide is adhesively molded using a CVD (chemical vapor deposition) method at a temperature of 200 to 450 degrees to a thickness of 2,000 to 20,000 angstroms. Feature method.   12. A method according to claim 11, wherein the measurement of the thickness of the second insulating layer on the metallization pattern is made by optical interference.   12. The method according to claim 11, wherein the thickness measurement of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate is made by optical interference.   12. The method of claim 11, wherein the chemical / mechanical polishing (CMP) of the second insulating layer is performed at a pH of 9-14 using a polishing slurry comprising abrasive particles and a chemical etchant. Feature method.   12. The method of claim 11, wherein the re-measurement of the thickness of the second insulating layer on the metallization pattern after chemical / mechanical polishing is done by optical interference. 12. The method according to claim 11, wherein the re-measurement of the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate after chemical / mechanical polishing is performed by optical interference. Feature method. In a method of chemically / mechanically polishing a semiconductor substrate (CMP),
Depositing and molding a first insulating layer on the semiconductor substrate;
Forming a metallization pattern on the first insulating layer;
Attaching and forming a second insulating layer on the first insulating layer and the metallization pattern so as to coincide;
Measuring the thickness of the second insulating layer on the metallization pattern;
Measuring a thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate;
Applying chemical / mechanical polishing (CMP) to the second insulating layer;
Transporting the semiconductor substrate to an in-line cleaning station with a water spray nozzle and an air spray nozzle;
Removing polishing slurry from the semiconductor substrate with water from the water spray nozzle;
Drying the semiconductor substrate with air from the air spray nozzle;
Transporting the semiconductor substrate to an inline optical thickness measuring tool, aligning the semiconductor substrate within the optical thickness measuring tool,
After chemical / mechanical polishing (CMP), again measuring the thickness of the second insulating layer on the metallization pattern;
Measuring again the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate after chemical / mechanical polishing (CMP);
Calculating a first polishing removal rate of the second insulating layer on the metallization pattern;
Calculating a second polishing removal rate of the second insulating layer on the semiconductor substrate;
Dividing the second polishing removal rate by the first polishing removal rate to calculate a ratio of the polishing removal rate;
Further applying chemical / mechanical polishing (CMP) until the polishing removal rate ratio exceeds 0.9 to 1.1.   26. The method of claim 25, wherein the first insulating layer is silicon oxide.   26. The method of claim 25, wherein the silicon oxide is adhesively molded using a chemical vapor deposition (CVD) method at a temperature of 200 to 450 degrees to a thickness of 2,000 to 20,000 angstroms. Feature method.   26. The method of claim 25, wherein the metallization pattern comprises metal islands having a length and width dimension of 50 to 1,000 [mu] m.   29. The method of claim 28, wherein the metal island has a thickness of 3,000 to 8,000 angstroms.   30. The method of claim 28, wherein the metal island is aluminum.   30. The method of claim 28, wherein the metal island is aluminum-copper-silicon. 26. The method of claim 25 , wherein the second insulating layer is silicon oxide.   33. The method of claim 32, wherein the silicon oxide is adhesively molded using a CVD (chemical vapor deposition) method at a temperature of 200 to 450 degrees to a thickness of 2,000 to 20,000 angstroms. Feature method.   26. The method of claim 25, wherein measuring the thickness of the second insulating layer on the metallization pattern is made by optical interference.   26. The method according to claim 25, wherein the measurement of the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate is made by optical interference.   26. The method of claim 25, wherein the chemical / mechanical polishing (CMP) of the second insulating layer is performed at a pH of 9-14 using a polishing slurry containing abrasive particles and a chemical etchant. Feature method.   26. The method of claim 25, wherein the re-measurement of the thickness of the second insulating layer on the metallization pattern after chemical / mechanical polishing is done by optical interference.   26. The method of claim 25, wherein the thickness of the combination of the second insulating layer and the first insulating layer on the semiconductor substrate after chemical / mechanical polishing is re-measured by optical interference. Feature method.

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