JP3187162B2 - Polishing device and semiconductor device - Google Patents

Polishing device and semiconductor device

Info

Publication number
JP3187162B2
JP3187162B2 JP27044092A JP27044092A JP3187162B2 JP 3187162 B2 JP3187162 B2 JP 3187162B2 JP 27044092 A JP27044092 A JP 27044092A JP 27044092 A JP27044092 A JP 27044092A JP 3187162 B2 JP3187162 B2 JP 3187162B2
Authority
JP
Japan
Prior art keywords
polishing
wafer
film
conductive film
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27044092A
Other languages
Japanese (ja)
Other versions
JPH06120183A (en
Inventor
貞浩 岸井
由弘 有本
博 堀江
文利 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27044092A priority Critical patent/JP3187162B2/en
Priority to US08/131,949 priority patent/US5562529A/en
Publication of JPH06120183A publication Critical patent/JPH06120183A/en
Priority to US08/676,663 priority patent/US5624300A/en
Application granted granted Critical
Publication of JP3187162B2 publication Critical patent/JP3187162B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は研磨装置及び半導体装置
に関し、より詳しくは、配線層及び被覆絶縁膜等の形成
されたウエハ表面を平坦化するための研磨装置及び半導
体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing apparatus and a semiconductor device, and more particularly, to a polishing apparatus and a semiconductor device for flattening a wafer surface on which a wiring layer and a covering insulating film are formed.

【0002】[0002]

【従来の技術】図7(a),(b)は従来例の研磨装置
の構成図、図8(a)〜(c)は従来例の研磨方法につ
いて説明する断面図である。
2. Description of the Related Art FIGS. 7 (a) and 7 (b) are structural views of a conventional polishing apparatus, and FIGS. 8 (a) to 8 (c) are cross-sectional views for explaining a conventional polishing method.

【0003】図7(a),(b)において、1は回転可
能な円板状の定盤、2は定盤1上に張り付けられた研磨
布、3は定盤1に対向して設けられ、被研磨体としての
配線層及び被覆絶縁膜の形成されたウエハ5を固定する
円板状のウエハ保持具で、定盤1の直径よりも小さく、
定盤1の回転方向と同じ方向に回転するようになってい
る。4はコロイダルシリカを含む研磨剤を滴下するノズ
ルである。
In FIGS. 7 (a) and 7 (b), reference numeral 1 denotes a rotatable disk-shaped platen, 2 denotes a polishing cloth stuck on the platen 1, and 3 denotes a plate facing the platen 1. A disk-shaped wafer holder for fixing the wafer 5 on which the wiring layer and the coating insulating film as the object to be polished are formed, and which is smaller than the diameter of the platen 1;
The platen 1 rotates in the same direction as the rotation direction. Reference numeral 4 denotes a nozzle for dropping an abrasive containing colloidal silica.

【0004】上記の研磨装置を用いて研磨する方法につ
いて、図8(a)〜(c)を参照しながら説明する。図
8(a)は配線層及び被覆絶縁膜の形成された後の状態
であって、研磨前の状態を示すウエハの断面図で、6は
半導体基板、7は半導体基板6上の下地絶縁膜、8は下
地絶縁膜7上に形成された下部配線層、9a,9bは下
部配線層8を後に形成される上部配線層と接続するため
の円柱状の接続導電体で、下部配線層8上に2か所形成
されている。10は下部配線層8及び接続導電体9a,
9bを被覆する層間絶縁膜である。
A method of polishing using the above polishing apparatus will be described with reference to FIGS. 8 (a) to 8 (c). FIG. 8A is a cross-sectional view of a wafer showing a state after a wiring layer and a covering insulating film are formed and before polishing, wherein 6 is a semiconductor substrate, and 7 is a base insulating film on the semiconductor substrate 6. , 8 are lower wiring layers formed on the underlying insulating film 7, 9 a and 9 b are columnar connection conductors for connecting the lower wiring layer 8 to an upper wiring layer to be formed later, Are formed in two places. 10 is a lower wiring layer 8 and a connecting conductor 9a,
9b is an interlayer insulating film that covers 9b.

【0005】このような状態で,まず、ウエハ5を下部
配線層8及び層間絶縁膜10の形成された面が研磨面に
なるように、図7(a)に示すウエハ保持具3に保持
し、固定する。次いで、下部配線層8及び層間絶縁膜1
0の形成された面と研磨布2の面とが平行に対向するよ
うに、ウエハ保持具3と研磨布2の張りつけられた定盤
1とを対向させた後、ウエハ保持具3と定盤1とを同じ
方向に回転させながらウエハ保持具3を下に移動させ
て、ノズル4から研磨剤を研磨布2上に滴下する。
In such a state, first, the wafer 5 is held on the wafer holder 3 shown in FIG. 7A so that the surface on which the lower wiring layer 8 and the interlayer insulating film 10 are formed becomes a polished surface. , Fix. Next, the lower wiring layer 8 and the interlayer insulating film 1
After the wafer holder 3 and the platen 1 on which the polishing cloth 2 is attached are opposed to each other so that the surface on which the polishing pad 2 is formed and the surface of the polishing pad 2 face in parallel, the wafer holder 3 and the platen The wafer holder 3 is moved downward while rotating the wafer holder 1 in the same direction, and the abrasive is dropped from the nozzle 4 onto the polishing pad 2.

【0006】ウエハ保持具3を押圧してウエハ保持具3
を定盤1上を適当に移動させながら、接続導電体9a,
9bが表出するまで、ウエハ5上の層間絶縁膜10を研
磨する。所定の時間の経過の後、層間絶縁膜10が研磨
され、ウエハ5の表面が平坦化されるとともに、接続導
電体9a,9bが表出する(図8(b))。
[0006] The wafer holder 3 is pressed to
Are appropriately moved on the surface plate 1, while the connection conductors 9a,
The interlayer insulating film 10 on the wafer 5 is polished until 9b is exposed. After a lapse of a predetermined time, the interlayer insulating film 10 is polished, the surface of the wafer 5 is flattened, and the connection conductors 9a and 9b are exposed (FIG. 8B).

【0007】その後、表出した接続導電体9a,9bと
接続して上部配線層11a,11bを形成すると、接続導電
体9a,9bを介して下部配線層8と上部配線層11a,
11bとが接続される(図8(c))。
After that, when the upper wiring layers 11a and 11b are formed by connecting to the exposed connecting conductors 9a and 9b, the lower wiring layer 8 and the upper wiring layers 11a and 11a are connected via the connecting conductors 9a and 9b.
11b is connected (FIG. 8 (c)).

【0008】[0008]

【発明が解決しようとする課題】しかし、上記の従来例
の研磨方法によれば、研磨時にウエハ保持具3を押圧す
る力のかけ具合により、ウエハ5面内で研磨量がばらつ
くため、ウエハ5面内いたるところ等しい層間絶縁膜1
0の残存膜厚を得ることは困難である。このため、図9
に示すように、残存する接続導電体9a,9bや層間絶
縁膜10aの膜厚が薄くなり、上下配線層間の絶縁膜の耐
圧の低下や上下配線層間のショートが発生するという問
題がある。
However, according to the above-described conventional polishing method, the amount of polishing varies within the surface of the wafer 5 due to the degree of force applied to the wafer holder 3 during polishing. The same interlayer insulating film 1 throughout the plane
It is difficult to obtain a residual film thickness of 0. Therefore, FIG.
As shown in (1), there is a problem that the film thickness of the remaining connection conductors 9a and 9b and the interlayer insulating film 10a becomes thin, and the breakdown voltage of the insulating film between the upper and lower wiring layers is reduced and a short circuit occurs between the upper and lower wiring layers.

【0009】この問題を解決するため、研磨途中にウエ
ハの研磨面を観察すればよいが、ウエハの清浄処理、顕
微鏡観察等を行なう必要があり、スループットの低下を
招く。本発明は、係る従来例の問題点に鑑みて創作され
たものであり、研磨途中にウエハ研磨面を観察すること
なく、ウエハ面内を均一に研磨することができる研磨装
置及び半導体装置の提供を目的とするものである。
In order to solve this problem, it is only necessary to observe the polished surface of the wafer during polishing. However, it is necessary to perform a cleaning process on the wafer, observe with a microscope, or the like, which causes a decrease in throughput. The present invention has been made in view of the problems of the related art, and provides a polishing apparatus and a semiconductor device capable of uniformly polishing the inside of a wafer without observing the wafer polishing surface during polishing. It is intended for.

【0010】[0010]

【課題を解決するための手段】上記課題は、第1に、回
転可能な定盤と、該定盤上の第1の導電体膜と、該第1
の導電体膜が表出するように開口部が形成された前記第
1の導電体膜上の研磨布と、ウエハの保持面に第2の導
電体膜が形成され、前記保持面が前記研磨布と対向する
ように配置されて前記定盤の移動又は自身の移動により
前記保持面上のウエハを前記研磨布と接触させ、前記ウ
エハを研磨する回転可能なウエハ保持具と、イオンを含
む研磨剤を吐出するノズルと、電流検出手段を介して前
記第1の導電体膜及び第2の導電体膜と接続された電源
とを有する研磨装置によって達成され、第2に、半導体
基板に直接接触し、かつ研磨される被研磨体の残存膜厚
に等しい高さの導電体からなる電流通流部が複数形成さ
れ、かつ該複数の電流通流部の断面積は、基準となる電
流通流部の断面積に対してxn倍(x≧2、nは整数)
となっていることを特徴とする半導体装置によって達成
される。
SUMMARY OF THE INVENTION The first object of the present invention is to firstly provide a rotatable platen, a first conductive film on the platen,
A polishing cloth on the first conductive film having an opening formed so that the conductive film is exposed, and a second conductive film formed on a holding surface of the wafer, wherein the holding surface has the polishing surface. A rotatable wafer holder, which is arranged to face a cloth and contacts the wafer on the holding surface with the polishing cloth by moving the surface plate or by moving itself, and polishing the wafer by polishing; This is achieved by a polishing apparatus having a nozzle for discharging an agent and a power supply connected to the first conductor film and the second conductor film via current detection means, and secondly, a direct contact with the semiconductor substrate. And a plurality of current conducting portions made of a conductor having a height equal to the remaining film thickness of the object to be polished are formed, and a cross-sectional area of the plurality of current conducting portions is a reference current passing portion. X n times the cross-sectional area of the part (x ≧ 2, n is an integer)
This is achieved by a semiconductor device characterized by the following.

【0011】[0011]

【作用】本発明の研磨装置においては、定盤上に第1の
導電体膜が形成され、その上に第1の導電体膜が表出す
る開口部を有する研磨布が形成されており、かつ定盤と
対向するウエハ保持具の保持面に第2の導電体膜が形成
されている。さらに、イオンを含む研磨剤を吐出するノ
ズルと、電流検出手段を介して第1の導電体膜及び第2
の導電体膜と接続された電源とを有している。
In the polishing apparatus of the present invention, a first conductive film is formed on a surface plate, and a polishing cloth having an opening through which the first conductive film is exposed is formed thereon. In addition, a second conductive film is formed on a holding surface of the wafer holder facing the surface plate. Further, the first conductive film and the second conductive film are discharged via a nozzle for discharging an abrasive containing ions, and a current detecting means.
And a power supply connected to the conductive film.

【0012】また、本発明の半導体装置においては、半
導体基板に直接接触し、かつ研磨された後の被研磨体の
残存すべき膜厚に等しい高さの導電体からなる電流通流
部を有している。特に、基準となる電流通流部の断面積
に対して電流通流部の断面積をxn倍(x≧2、nは整
数)とすると、任意の複数の電流通流部が通電しても常
に異なる値が得られる。例えば、x=2とすると、基準
となる電流通流部の断面積1に対して、n=1,2,
3,4,・・・に対応して、2、4、8、16、・・・
という関係になる。
Further, the semiconductor device of the present invention has a current flow portion made of a conductor which is in direct contact with the semiconductor substrate and has a height equal to the thickness of the polished body to be polished. are doing. In particular, assuming that the cross-sectional area of the current flow portion is xn times (x ≧ 2, n is an integer) with respect to the cross-sectional area of the reference current flow portion, any of the plurality of current flow portions is energized. Different values are always obtained. For example, when x = 2, n = 1, 2, 2, with respect to the cross-sectional area 1 of the reference current flow portion.
2, 4, 8, 16,... Corresponding to 3, 4,.
It becomes the relationship.

【0013】従って、ウエハの表面の配線層等を被覆す
る層間絶縁膜等を研磨する場合、ウエハをウエハ保持具
の第2の導電体膜上に保持し、定盤上の第1の導電体膜
の上の研磨布とウエハとを接触させ、押圧して研磨す
る。ウエハ上の電流通流部のいずれかが表出したとき
に、研磨布に設けられた開口部内に入り込んでいるウエ
ハ研磨剤中のイオンが介在することにより、第1の導電
体膜/イオン/電流通流部/半導体基板/第2の導電体
膜という電流通路により被研磨体を介して定盤上の第1
の導電体膜とウエハ保持具の第2の導電体膜との間に電
流が流れる。従って、この電流を監視しながら研磨する
ことにより、残存膜厚が所定の膜厚よりも厚い部分に相
当する、電流の通流していない電流通流部及びその周辺
部を特定し、この部分の押圧力を強めて研磨量を多くす
ることができる。
Therefore, when polishing an interlayer insulating film or the like covering a wiring layer or the like on the surface of the wafer, the wafer is held on the second conductor film of the wafer holder, and the first conductor on the surface plate is polished. The polishing cloth on the film is brought into contact with the wafer and pressed to polish. When any one of the current flow portions on the wafer is exposed, ions in the wafer abrasive that have entered the opening provided in the polishing pad intervene, so that the first conductive film / ion / The first path on the surface plate through the object to be polished by the current path of the current conducting portion / semiconductor substrate / second conductive film.
An electric current flows between the conductive film of the wafer holder and the second conductive film of the wafer holder. Therefore, by polishing while monitoring this current, the current flowing portion where current does not flow and the peripheral portion corresponding to the portion where the remaining film thickness is larger than the predetermined film thickness and the peripheral portion thereof are specified. By increasing the pressing force, the polishing amount can be increased.

【0014】このように、電流を監視しながら研磨量を
部分的に調整することができるので、従来のように、研
磨途中にウエハ表面の観察をしなくてもよい。これによ
り、工程の簡略化を図り、より均一な研磨を行うことが
できる。
As described above, since the polishing amount can be partially adjusted while monitoring the current, it is not necessary to observe the wafer surface during polishing as in the related art. Thereby, the process can be simplified and more uniform polishing can be performed.

【0015】[0015]

【実施例】次に、図面を参照しながら本発明の実施例に
ついて説明する。 (1)本発明の第1の実施例の研磨装置 図1(a),(b)は本発明の第1の実施例に係る研磨
装置の構成図である。
Next, an embodiment of the present invention will be described with reference to the drawings. (1) Polishing Apparatus of First Embodiment of the Present Invention FIGS. 1A and 1B are configuration diagrams of a polishing apparatus according to a first embodiment of the present invention.

【0016】図1(a),(b)において、21は回転
可能な円板状の定盤で、表面に第1の導電体膜22が形
成されている。23は第1の導電体膜22上に張り付け
られた研磨布で、小さい開口部24が多数形成されてお
り、開口部24の底部に第1の導電体膜22が表出して
いる。25は定盤21に対向して設けられ、被研磨体と
しての下部配線層及び被覆絶縁膜の形成されたウエハ3
0を固定する円板状のウエハ保持具で、定盤21の直径
よりも小さく、回転するようになっている。また、ウエ
ハ保持具25の表面には第2の導電体膜26が形成され
ている。27はイオン、例えばNaイオンやKイオンを
含むコロイダルシリカを含む研磨剤を滴下するノズル、
28は電圧を供給する電源で、定盤21の第1の導電体
膜22とウエハ保持具25の第2の導電体膜26とに電
流計(電流検出手段)29を介して接続されている。
In FIGS. 1 (a) and 1 (b), reference numeral 21 denotes a rotatable disk-shaped surface plate on which a first conductive film 22 is formed. Reference numeral 23 denotes a polishing cloth adhered on the first conductive film 22, and a large number of small openings 24 are formed. The first conductive film 22 is exposed at the bottom of the opening 24. Reference numeral 25 denotes a wafer 3 which is provided opposite to the surface plate 21 and has a lower wiring layer and a coating insulating film as a body to be polished.
This is a disc-shaped wafer holder for fixing 0, which is smaller than the diameter of the platen 21 and rotates. Further, a second conductor film 26 is formed on the surface of the wafer holder 25. 27 is a nozzle for dropping an abrasive containing ions, for example, colloidal silica containing Na ions and K ions,
Reference numeral 28 denotes a power supply for supplying a voltage, which is connected to the first conductive film 22 of the surface plate 21 and the second conductive film 26 of the wafer holder 25 via an ammeter (current detecting means) 29. .

【0017】以上のように、本発明の第1の実施例の研
磨装置によれば、定盤21及びウエハ保持具25の各表
面に第1の導電体膜22及び第2の導電体膜26が張り
つけられ、かつ定盤21の第1の導電体膜22上の研磨
布23に開口部24が形成され、更に、イオンを含む研
磨剤が滴下されるノズル27を有している。
As described above, according to the polishing apparatus of the first embodiment of the present invention, the first conductor film 22 and the second conductor film 26 are formed on the surfaces of the surface plate 21 and the wafer holder 25, respectively. An opening 24 is formed in the polishing pad 23 on the first conductive film 22 of the platen 21, and a nozzle 27 into which an abrasive containing ions is dropped.

【0018】従って、ウエハ30をウエハ保持具25に
保持し、ウエハ30の表面の下部配線層を被覆する層間
絶縁膜を研磨する場合、定盤21上の第1の導電体膜2
2の上の研磨布23とウエハ保持具25上の第2の導電
体膜26の上のウエハ30とを接触させ、押圧して研磨
し、ウエハ30上の電流通流部32a〜32dのいずれかが
表出したときに開口部24内に入り込んでいる研磨剤中
のイオンが介在することにより、第1の導電体膜22/
イオン/電流通流部32a〜32d/半導体基板31/第2
の導電体膜26を介して底部の定盤21上の第1の導電
体膜22とウエハ保持具25上の第2の導電体膜26と
の間に電流を流すことができる。
Accordingly, when the wafer 30 is held by the wafer holder 25 and the interlayer insulating film covering the lower wiring layer on the surface of the wafer 30 is polished, the first conductive film 2 on the surface plate 21 is polished.
The polishing cloth 23 on the wafer 2 and the wafer 30 on the second conductive film 26 on the wafer holder 25 are brought into contact with each other, pressed and polished, and any one of the current passing portions 32a to 32d on the wafer 30 is polished. When the ions appear in the polishing agent that has entered the opening 24 when the first conductive film 22 /
Ion / current flow part 32a-32d / semiconductor substrate 31 / second
A current can flow between the first conductive film 22 on the bottom platen 21 and the second conductive film 26 on the wafer holder 25 via the conductive film 26 of FIG.

【0019】これにより、電流を監視しながら研磨を行
うことができるので、従来のように、研磨途中にウエハ
表面の観察をしなくてもよい。工程の簡略化を図り、よ
り均一な研磨を行うことができる。
As a result, the polishing can be performed while monitoring the current, so that it is not necessary to observe the wafer surface during polishing as in the prior art. The process can be simplified and more uniform polishing can be performed.

【0020】(2)本発明の第2の実施例の半導体装置 図2(a),(b)は本発明の第2の実施例に係る半導
体装置についての説明図で、図2(a)はウエハの上面
図、図2(b)はウエハの断面図である。
(2) Semiconductor Device of Second Embodiment of the Present Invention FIGS. 2A and 2B are explanatory views of a semiconductor device according to a second embodiment of the present invention. Is a top view of the wafer, and FIG. 2B is a sectional view of the wafer.

【0021】図2(a),(b)において、31は例え
ばシリコンからなる半導体基板、32a〜32eはウエハ3
0の中央部に1か所(C)、周辺部に4か所(A,B,
D,E)形成された円柱状のタングステン(W)膜から
なる電流通流部で、下地絶縁膜33の開口部の底部の半
導体基板31と直接接続し、電流通流部の断面積はA部
の電流通流部32aの1に対してB,C,D,E部の電流
通流部32b〜32dでそれぞれ2,4,8,16となって
いる。断面積を1,2,4,8,16という関係にして
いるのは、任意の複数の電流通流部が導通しても常に異
なる値が得られるようにして電流通流部を特定するため
である。
2 (a) and 2 (b), reference numeral 31 denotes a semiconductor substrate made of, for example, silicon;
0 at the center (C) and 4 at the periphery (A, B,
D, E) formed by a column-shaped tungsten (W) film current flow portion, which is directly connected to the semiconductor substrate 31 at the bottom of the opening of the base insulating film 33, and has a cross-sectional area of A The current flowing portions 32b to 32d of the B, C, D, and E portions are 2, 4, 8, and 16, respectively, with respect to one of the current flowing portions 32a of the portion. The cross-sectional areas are set to 1, 2, 4, 8, and 16 because the current conducting portions are specified so that different values are always obtained even when a plurality of current conducting portions are conducted. It is.

【0022】例えば、ウエハ30の表面の下部配線層を
被覆する層間絶縁膜を研磨する場合、定盤21とウエハ
保持具25上のウエハ30とを接触させて研磨し、ウエ
ハ30上の電流通流部32a〜32dのいずれかが表出した
ときに開口部24内に入り込んでいるウエハ研磨剤中の
イオンが介在することにより、第1の導電体膜22/イ
オン/電流通流部32a〜32d/半導体基板31/第2の
導電体膜26を介して底部の定盤21の第1の導電体膜
22とウエハ保持具25の第2の導電体膜26との間に
電流を流す。
For example, when polishing the interlayer insulating film covering the lower wiring layer on the surface of the wafer 30, the surface plate 21 and the wafer 30 on the wafer holder 25 are brought into contact with each other and polished. When any of the flow portions 32a to 32d is exposed, the ions in the wafer abrasive that have entered the opening 24 are interposed, so that the first conductive film 22 / ion / current flow portions 32a to 32d are exposed. A current flows between the first conductive film 22 of the bottom platen 21 and the second conductive film 26 of the wafer holder 25 via the 32d / semiconductor substrate 31 / second conductive film 26.

【0023】(3)本発明の第3の実施例の研磨方法 上記の研磨装置を用いて研磨する本発明の第2の実施例
の研磨方法について、図3(a),(b),図4(a)
〜(c)及び図1(a),(b),図2(a),(b)
を参照しながら説明する。図3(a),(b)は電流計
に流れる電流の経時変化を示す図、図4(a)〜(c)
は実施例の研磨方法を含む半導体装置の製造方法につい
て示す断面図である。
(3) Polishing method of the third embodiment of the present invention FIGS. 3 (a), 3 (b), and 3 (b) show the polishing method of the second embodiment of the present invention in which the above-mentioned polishing apparatus is used for polishing. 4 (a)
-(C) and FIGS. 1 (a), (b), 2 (a), (b)
This will be described with reference to FIG. 3 (a) and 3 (b) are diagrams showing changes with time in the current flowing through the ammeter, and FIGS. 4 (a) to 4 (c).
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device including the polishing method according to the embodiment.

【0024】図4(a)は下部配線層及び被覆絶縁膜の
形成された後の状態であって、研磨前の状態を示すウエ
ハの断面図で、31はシリコンからなる半導体基板、3
3は半導体基板31上のシリコン酸化膜からなる下地絶
縁膜、34は下地絶縁膜33上に形成されたアルミニウ
ムからなる下部配線層(導電体層)、35a,35bは下部
配線層34を後に形成される上部配線層と接続するため
の円柱状のアルミニウムからなる接続導電体で、下部配
線層34上に2か所形成されている。36は下部配線層
34及び接続導電体35a,35bを被覆するシリコン酸化
膜からなる層間絶縁膜(絶縁膜)である。
FIG. 4A is a cross-sectional view of a wafer showing a state after a lower wiring layer and a covering insulating film are formed and before polishing, and reference numeral 31 denotes a semiconductor substrate made of silicon;
Reference numeral 3 denotes a base insulating film made of a silicon oxide film on the semiconductor substrate 31, reference numeral 34 denotes a lower wiring layer (conductor layer) made of aluminum formed on the base insulating film 33, and reference numerals 35a and 35b denote a lower wiring layer 34 to be formed later. A connection conductor made of columnar aluminum for connecting to the upper wiring layer to be formed, and is formed at two places on the lower wiring layer 34. Reference numeral 36 denotes an interlayer insulating film (insulating film) made of a silicon oxide film that covers the lower wiring layer 34 and the connection conductors 35a and 35b.

【0025】このような状態で,まず、ウエハ30を下
部配線層34及び層間絶縁膜36の形成された面が表出
するように、図1(a)に示すウエハ保持具25に保持
し、固定する。次いで、下部配線層34及び層間絶縁膜
36の形成された面と研磨布23の面とが平行に対向す
るように、ウエハ保持具25と研磨布23の張りつけら
れた定盤21とを対向させた後、ウエハ保持具25と定
盤21とを同じ方向に回転させながらウエハ保持具25
を下に移動させるか又は定盤21を上に移動させて接触
させるとともに、ノズル27から研磨剤を研磨布23上
に滴下する。
In this state, first, the wafer 30 is held on the wafer holder 25 shown in FIG. 1A so that the surface on which the lower wiring layer 34 and the interlayer insulating film 36 are formed is exposed. Fix it. Next, the wafer holder 25 and the surface plate 21 on which the polishing pad 23 is adhered face each other so that the surface on which the lower wiring layer 34 and the interlayer insulating film 36 are formed faces the surface of the polishing pad 23 in parallel. Then, while rotating the wafer holder 25 and the surface plate 21 in the same direction, the wafer holder 25
Is moved downward or the surface plate 21 is moved upward to make contact therewith, and the abrasive is dropped from the nozzle 27 onto the polishing pad 23.

【0026】ウエハ保持具25を押圧してウエハ保持具
25を定盤21上を適当に移動させながら、ウエハ30
上の層間絶縁膜36を研磨する。このとき、電流計29
を監視する。いま、ある程度研磨が進み、電流通流部32
bが表出したとすると、このとき、断面積2に相当する
電流が流れ、電流計29に検出される。従って、B部以
外の部分を比較的強く押圧する。研磨が進み、次いで、
電流通流部32eが表出したとすると、断面積2+16に
相当する電流が流れ、電流計29に検出される。従っ
て、B部及びE部以外の部分を比較的強く押圧する。研
磨が進み、次に、電流通流部32aが表出したとすると、
断面積2+16+1に相当する電流が流れ、電流計29
に検出される。従って、B部,E部及びA部以外の部分
を比較的強く押圧する。研磨が進み、次いで、電流通流
部32cが表出したとすると、断面積2+16+1+4に
相当する電流が流れ、電流計29に検出される。従っ
て、B部,E部,A部及びC部以外のD部周辺を比較的
強く押圧する。研磨が進み、次に、電流通流部32dが表
出したとすると、断面積2+16+1+4+8に相当す
る電流が流れ、電流計29に検出される。これにより、
全ての電流通流部32a〜32eが導通し、所定の研磨量が
達成されたことになると判断し、研磨を終了する(図3
(a))。なお、図3(b)の場合、最初にB部の電流
通流部32bが導通し、その後電流通流部32a,32c〜32
eが同時に導通したことを示す。
While pressing the wafer holder 25 and moving the wafer holder 25 on the surface plate 21 appropriately, the wafer 30
The upper interlayer insulating film 36 is polished. At this time, the ammeter 29
To monitor. Now, polishing has progressed to some extent, and the current
Assuming that b is exposed, at this time, a current corresponding to the cross-sectional area 2 flows and is detected by the ammeter 29. Therefore, parts other than the part B are pressed relatively strongly. Polishing proceeds, then
Assuming that the current flow portion 32e is exposed, a current corresponding to the cross-sectional area 2 + 16 flows and is detected by the ammeter 29. Therefore, parts other than the part B and the part E are pressed relatively strongly. Assuming that the polishing proceeds, and then the current flow portion 32a is exposed,
A current corresponding to the cross-sectional area 2 + 16 + 1 flows, and the ammeter 29
Is detected. Therefore, parts other than the B part, the E part and the A part are pressed relatively strongly. Assuming that the polishing proceeds and then the current flow portion 32c is exposed, a current corresponding to a cross-sectional area of 2 + 16 + 1 + 4 flows and is detected by the ammeter 29. Therefore, the periphery of the portion D other than the portions B, E, A and C is pressed relatively strongly. Assuming that the polishing progresses and then the current flow portion 32d is exposed, a current corresponding to a cross-sectional area of 2 + 16 + 1 + 4 + 8 flows and is detected by the ammeter 29. This allows
It is determined that all of the current flow portions 32a to 32e are conductive and a predetermined polishing amount has been achieved, and polishing is terminated (FIG. 3).
(A)). In the case of FIG. 3B, first, the current flow portion 32b of the portion B conducts, and thereafter, the current flow portions 32a, 32c to 32c.
e indicate that they are conducting simultaneously.

【0027】これにより、図5に示すように、所定の量
の層間絶縁膜36がウエハ30全面にわたり均一に研磨
され、ウエハ30の表面が平坦化される。そして、接続
導電体35a,35bが表出する(図4(b))。
As a result, as shown in FIG. 5, a predetermined amount of the interlayer insulating film 36 is uniformly polished over the entire surface of the wafer 30, and the surface of the wafer 30 is flattened. Then, the connecting conductors 35a and 35b are exposed (FIG. 4B).

【0028】その後、表出した接続導電体35a,35bと
接続して上部配線層37a,37bを形成すると、接続導電
体35a,35bを介して下部配線層34と上部配線層37
a,37bとが接続される(図4(c))。
Thereafter, when the upper wiring layers 37a and 37b are formed by connecting to the exposed connection conductors 35a and 35b, the lower wiring layer 34 and the upper wiring layer 37 are connected via the connection conductors 35a and 35b.
a and 37b are connected (FIG. 4C).

【0029】上記のようにして作成されたウエハ30上
の層間絶縁膜36aのウエハ30内の残存膜厚のばらつき
と、ウエハ30間の平均残存膜厚を調査した。その結果
をそれぞれ図6(a),(b)に示す。
The variation in the remaining film thickness of the interlayer insulating film 36a on the wafer 30 formed as described above in the wafer 30 and the average remaining film thickness between the wafers 30 were examined. The results are shown in FIGS. 6A and 6B, respectively.

【0030】上記の調査結果によれば、ウエハ内の残存
膜厚のばらつき及びウエハ間の平均残存膜厚のばらつき
ともに従来例に比較して大幅に改善された。以上のよう
に、本発明によれば、電流計29を監視しながらウエハ
各部の研磨量のチェックが可能なので、必要な部分の押
圧力を調整することにより、研磨量を均一化することが
できる。これにより、研磨された後の層間絶縁膜36aの
ウエハ30内の残存膜厚のばらつき,ウエハ30間の平
均残存膜厚のばらつきとも従来例に比較して大幅に改善
することができるとともに、研磨途中でのウエハ観察を
不要にして工程を簡略化できる。
According to the results of the above investigation, both the variation in the remaining film thickness in the wafer and the variation in the average remaining film thickness between the wafers were significantly improved as compared with the conventional example. As described above, according to the present invention, it is possible to check the polishing amount of each part of the wafer while monitoring the ammeter 29. Therefore, the polishing amount can be made uniform by adjusting the pressing force of the necessary portion. . As a result, the variation in the remaining film thickness of the interlayer insulating film 36a after polishing in the wafer 30 and the variation in the average remaining film thickness between the wafers 30 can be significantly improved as compared with the conventional example. The process can be simplified by obviating the need for wafer observation on the way.

【0031】[0031]

【発明の効果】以上のように、本発明の研磨装置におい
ては、定盤上に第1の導電体膜が形成され、第1の導電
体膜が露出する開口部を有する研磨布がその上に形成さ
れており、かつ定盤と対向するウエハ保持具の保持面に
第2の導電体膜が形成されている。さらに、イオンを含
む研磨剤を吐出するノズルと、電流検出手段を介して第
1の導電体膜及び第2の導電体膜と接続された電源とを
有している。
As described above, in the polishing apparatus of the present invention, the first conductive film is formed on the surface plate, and the polishing cloth having the opening through which the first conductive film is exposed is formed thereon. And a second conductive film is formed on the holding surface of the wafer holder facing the surface plate. Further, it has a nozzle for discharging a polishing agent containing ions, and a power supply connected to the first conductor film and the second conductor film via current detection means.

【0032】また、本発明の半導体装置においては、半
導体基板に直接接触し、かつ研磨された後の被研磨体の
残存すべき膜厚に等しい高さの導電体からなる電流通流
部を有している。特に、基準となる電流通流部の断面積
に対して電流通流部の断面積をxn倍(x≧2、nは整
数)とすることにより、任意の複数の電流通流部が通電
しても常に異なる値が得られ、非導通の電流通流部を特
定することができる。
Further, the semiconductor device of the present invention has a current flow portion made of a conductor which is in direct contact with the semiconductor substrate and has a height equal to the thickness of the polished body to be polished to remain. are doing. In particular, by making the cross-sectional area of the current flow portion xn times (x ≧ 2, n is an integer) the cross-sectional area of the reference current flow portion, an arbitrary plurality of current flow portions can be energized. However, a different value is always obtained, and a non-conductive current flow portion can be specified.

【0033】従って、ウエハの表面の配線層等を被覆す
る層間絶縁膜等を研磨する場合、ウエハをウエハ保持具
の第2の導電体膜上に保持し、定盤上の第1の導電体膜
の上の研磨布とウエハとを接触させて押圧し、第1の導
電体膜と第2の導電体膜との間に流れる電流を監視しな
がら研磨することにより、ウエハ上の電流の通流してい
ない電流通流部及びその周辺部、即ち残存膜厚が所定の
膜厚よりも厚い部分を特定し、かつその部分の押圧力を
強めて研磨量を多くすることができる。
Therefore, when polishing an interlayer insulating film or the like covering a wiring layer or the like on the surface of the wafer, the wafer is held on the second conductive film of the wafer holder, and the first conductive film on the surface plate is polished. The polishing cloth on the film is brought into contact with and pressed against the wafer, and the polishing is performed while monitoring the current flowing between the first conductive film and the second conductive film. It is possible to specify a current flowing portion and a peripheral portion thereof that are not flowing, that is, a portion where the remaining film thickness is larger than a predetermined film thickness, and increase the pressing force of the portion to increase the polishing amount.

【0034】このように、電流を監視しながら研磨量を
部分的に調整することができるので、従来のように、研
磨途中にウエハ表面の観察をしなくてもよい。これによ
り、工程の簡略化を図り、より均一な研磨を行うことが
できる。
As described above, since the polishing amount can be partially adjusted while monitoring the current, it is not necessary to observe the wafer surface during polishing as in the related art. Thereby, the process can be simplified and more uniform polishing can be performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例に係る研磨装置の構成図
である。
FIG. 1 is a configuration diagram of a polishing apparatus according to a first embodiment of the present invention.

【図2】本発明の第2の実施例に係る半導体装置につい
ての説明図である。
FIG. 2 is an explanatory diagram of a semiconductor device according to a second example of the present invention.

【図3】本発明の第3の実施例に係る研磨方法による監
視電流の経時変化についての説明図である。
FIG. 3 is an explanatory diagram of a change over time of a monitoring current by a polishing method according to a third embodiment of the present invention.

【図4】本発明の第3の実施例に係る研磨方法を含む半
導体装置の製造方法について説明する断面図である。
FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor device including a polishing method according to a third embodiment of the present invention.

【図5】本発明の第3の実施例に係る研磨方法により得
られたウエハ表面の平坦性について説明する断面図であ
る。
FIG. 5 is a cross-sectional view illustrating flatness of a wafer surface obtained by a polishing method according to a third embodiment of the present invention.

【図6】本発明の第3の実施例に係る研磨方法により得
られた残存膜のウエハ内の残存膜厚のばらつき及びウエ
ハ間の平均残存膜厚の調査結果についての説明図であ
る。
FIG. 6 is an explanatory diagram showing the results of a survey on the variation in the remaining film thickness in a wafer of the remaining film obtained by the polishing method according to the third embodiment of the present invention and the average remaining film thickness between wafers.

【図7】従来例に係る研磨装置の構成図である。FIG. 7 is a configuration diagram of a polishing apparatus according to a conventional example.

【図8】従来例に係る研磨方法を含む半導体装置の製造
方法について説明する断面図である。
FIG. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device including a polishing method according to a conventional example.

【図9】従来例に係る研磨方法により得られたウエハ表
面の平坦性について説明する断面図である。
FIG. 9 is a cross-sectional view illustrating flatness of a wafer surface obtained by a polishing method according to a conventional example.

【符号の説明】[Explanation of symbols]

21 定盤、 22 第1の導電体膜、 23 研磨布、 24 開口部、 25 ウエハ保持具、 26 第2の導電体膜、 27 ノズル、 28 電源、 29 電流計(電流検出手段)、 30 ウエハ、 31 半導体基板、 32a〜32d 電流通流部、 33 下地絶縁膜、 34 下部配線層(導電体層)、 35a,35b 接続導電体、 36,36a 層間絶縁膜(絶縁膜)、 37a,37b 上部配線層。 Reference Signs List 21 surface plate, 22 first conductive film, 23 polishing cloth, 24 opening, 25 wafer holder, 26 second conductive film, 27 nozzle, 28 power supply, 29 ammeter (current detecting means), 30 wafer 31 semiconductor substrate, 32a-32d current flow section, 33 base insulating film, 34 lower wiring layer (conductor layer), 35a, 35b connecting conductor, 36, 36a interlayer insulating film (insulating film), 37a, 37b upper part Wiring layer.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉本 文利 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 昭61−8943(JP,A) 特開 平1−207929(JP,A) 特開 平3−97226(JP,A) 特開 昭55−54174(JP,A) 特開 平3−174740(JP,A) 特開 平4−261773(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/304 621 H01L 21/304 622 H01L 21/3205 B24B 37/00 B24B 37/04 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Bunri Sugimoto 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-61-8943 (JP, A) JP-A-1- 207929 (JP, A) JP-A-3-97226 (JP, A) JP-A-55-54174 (JP, A) JP-A-3-174740 (JP, A) JP-A-4-261773 (JP, A) (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/304 621 H01L 21/304 622 H01L 21/3205 B24B 37/00 B24B 37/04

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】回転可能な定盤と、該定盤上の第1の導電
体膜と、該第1の導電体膜が表出するように開口部が形
成された前記第1の導電体膜上の研磨布と、ウエハの保
持面に第2の導電体膜が形成され、前記保持面が前記研
磨布と対向するように配置されて前記定盤の移動又は自
身の移動により前記保持面上のウエハを前記研磨布と接
触させ、前記ウエハを研磨する回転可能なウエハ保持具
と、イオンを含む研磨剤を吐出するノズルと、電流検出
手段を介して前記第1の導電体膜及び第2の導電体膜と
接続された電源とを有する研磨装置。
1. A rotatable surface plate, a first conductor film on the surface plate, and the first conductor having an opening formed to expose the first conductor film. A second conductive film is formed on the polishing cloth on the film and the holding surface of the wafer, and the holding surface is disposed so as to face the polishing cloth, and the holding surface is moved by the movement of the platen or by itself. A rotatable wafer holder for bringing the upper wafer into contact with the polishing cloth and polishing the wafer, a nozzle for discharging a polishing agent containing ions, and the first conductive film and the A polishing apparatus having a power supply connected to the second conductive film.
【請求項2】半導体基板に直接接触し、かつ研磨される
被研磨体の残存膜厚に等しい高さの導電体からなる電流
通流部が複数形成され、かつ該複数の電流通流部の断面
積は、基準となる電流通流部の断面積に対してxn
(x≧2、nは整数)となっていることを特徴とする半
導体装置。
2. A method according to claim 1, further comprising: forming a plurality of current flow portions made of a conductor which is in direct contact with the semiconductor substrate and has a height equal to the remaining film thickness of the object to be polished; A semiconductor device, wherein a cross-sectional area is xn times (x ≧ 2, n is an integer) times a cross-sectional area of a reference current flow portion.
JP27044092A 1992-10-08 1992-10-08 Polishing device and semiconductor device Expired - Fee Related JP3187162B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP27044092A JP3187162B2 (en) 1992-10-08 1992-10-08 Polishing device and semiconductor device
US08/131,949 US5562529A (en) 1992-10-08 1993-10-08 Apparatus and method for uniformly polishing a wafer
US08/676,663 US5624300A (en) 1992-10-08 1996-07-10 Apparatus and method for uniformly polishing a wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27044092A JP3187162B2 (en) 1992-10-08 1992-10-08 Polishing device and semiconductor device

Publications (2)

Publication Number Publication Date
JPH06120183A JPH06120183A (en) 1994-04-28
JP3187162B2 true JP3187162B2 (en) 2001-07-11

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