JP2002328832A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a display device to obtain required access frequency in fixed period and to simultaneously enable a CPU and a plotting device to make best use of accessibility to a memory owned by a microcomputer system having the CPU, the plotting device and the display device in the system. SOLUTION: The memory controller is provided with a control/mode register in which write is possible from the CPU, an access report detecting circuit, a priority level-judging circuit, a timer and a status register capable of read from the CPU. It periodically monitors accesses to the respective devices, stores them in the status register accessible from the CPU, compares a value of the status register with a restriction register set by software and can change priority level of the next prescribed period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system including a microprocessor, a memory, a ROM, and an IO device, and more particularly to a technique for controlling memory access when a plurality of devices access one memory, and more particularly to a memory controller. .

[0002]

2. Description of the Related Art A system comprising a microprocessor, a memory, a ROM, an IO device and the like is disclosed in Japanese Unexamined Patent Application Publication No.
There is a display controller disclosed in Japanese Patent Publication No. JP-A-8-255107 discloses that C
PU and drawing device, display device and IO device are one S
Access DRAM.

In the graphics system disclosed in Japanese Patent Application Laid-Open No. 11-296154, a display device is given top priority, and one memory access period of another device is limited.

Further, in the prior art shown in FIG.
It includes a PU 3, a display device 4, a drawing device 5, an IO device 6, a memory controller 1, an address generation unit 10, a command control unit 40, and a selection circuit 20. In the prior art, C
The access arbitration is set from the PU-accessible register bus, and the access control of the CPU 3, the display device 4, the drawing device 5, and the IO device 6 is performed with fixed priority according to the setting.

[0005]

SUMMARY OF THE INVENTION The above-mentioned Japanese Patent Application Laid-Open No. 8-255.
In the configuration of JP-A-107, the access priority of each de-hase is determined at the time of system design, and thereafter, performance must be improved within the range. Also, after developing such a system, it is not possible to grasp the amount of access, the weight overhead, and the number of accesses during a certain period when each device operates dynamically, which is a problem during software development and debugging. Was.

In the graphics system disclosed in Japanese Patent Application Laid-Open No. H11-296154, all accesses must be stopped once in advance during the access cycle of the display device, which involves overhead.

An object of the present invention is to solve the above problems.

[0008]

SUMMARY OF THE INVENTION A memory controller of the present invention measures an access report of each device for a fixed period during dynamic operation, and changes the priority of each device for the next fixed period according to the report result.

The memory controller of the present invention can make an access request as needed by each device regardless of the display performance required of the display device in the target system, and can continue the access until the display device accesses.

A memory controller according to the present invention comprises a control / mode register writable by a CPU, an access report detection circuit, a priority determination circuit, a timer,
A status register that can be read from the PU is provided, a timer is set for a period, access to each device is periodically monitored, and the status is stored in the status register.

In the memory controller of the present invention, this status register can always be accessed from the CPU.
There is provided a priority determination circuit which compares the value of the status register with the value of the restriction register set by software and can change the priority for the next predetermined period according to the result. The priority determination circuit sends the determined priority information to the arbiter and determines the priority for a certain period.

The memory controller of the present invention makes an access request as necessary for each device regardless of the display performance of the target system, makes a display access temporarily when the display device makes an access, and when the display access is completed, It has an abort function to continue accessing the original device again.

[0013]

1 to 3 show the configuration of a memory controller (MCU) 1 according to the present invention. As shown in FIG. 1, a CPU 3, a display device 4, a drawing device 5, and an IO device 6 arbitrate and access one memory (SDRAM) 2 with another device via a memory controller 1. . CPU 3, display device 4, and drawing device 5
The I / O device 6 outputs an access request to the memory controller 1 in response to the access request signal 33. The access request signal 33 selects a device that can be accessed by the arbiter 30 according to a predetermined priority signal 51 and returns an access permission signal 32. At the time of writing by the selection circuit 20, each device of the CPU 3, the display device 4, the drawing device 5, and the IO device 6 transmits data from the memory 2.
Signal is transferred to the
3, the display device 4, the drawing device 5, and the IO device 6.

The address at the time of reading / writing is generated by the address generator 10 and sent to the memory 2. The command control unit 40 issues an active command and a read / write command required for access, and performs memory access.

In FIG. 2, except that the output signal of the status register section 80 in the memory controller 1 is output to the outside of the memory controller 1 via the buffer 7,
Is the same as

FIG. 3 is the same as FIG. 1 except that the output signal of the status register unit 80 in the memory controller 1 and the output of the mode register unit 90 are input to the selection circuit 20.

Each device in FIG. 1 and memory controller 1
The interface with the server will be described below. FIG. 5 shows a timing chart in the case where only the drawing device makes an access request, and a display device having a higher priority than the drawing device issues an access request while the drawing device is being accessed. When the access request signal 33 of the drawing device is permitted, the memory controller 1 asserts a drawing access permission signal to the drawing device. When the drawing access permission signal is asserted, the drawing apparatus sends an access address and the number of access words to the memory controller 1 in the next cycle. Thus, after a few cycles, the memory access starts, and the read data is sent from the memory controller 1 to the drawing device 5 together with the drawing read strobe.

In FIG. 5, since the display device issues an access request when the drawing device 5 reads the third word, the memory controller temporarily suspends the access of the drawing device 5 having a lower priority and stops the access of the display device. Accept. At this time, the access permission signal 32 is asserted as in the case of the drawing device 5. In response to this, the display device 4 transmits the address and the number of access words to the memory controller 1, display access starts, 32 words are read, and the process ends. After the display access is completed, the drawing access is restarted, and the transmission of the read data to the drawing device 5 is restarted.

In FIG. 5, the read access of the drawing apparatus is
Temporarily suspended with display device access request. Even if an access request for the display device and an access request for the drawing device occur, if the banks on the memory are different, as shown in FIG. 6, while the active command is issued to the bank to be accessed by the display device. May continue to access the drawing device. As a result, it is possible to reduce overhead due to contention access between the drawing device and the display device. As described above, since the drawing device is continuously accessed up to the processing break unit, when a display device with a higher priority issues an access request during drawing, the drawing device is temporarily stopped.

During the suspension, the drawing apparatus waits for the read strobe. However, since the request is made in a predetermined small unit, the processing efficiency is improved. The priority is
It is determined according to the value of the priority determination mode register shown in FIG. In FIG. 20, the smaller the numerical value, the higher the priority. Since various priority relationships among the devices can be expressed by this setting, numerical values are tuned so that the performance of each device required by the target system can be obtained.

FIG. 21 shows an example of the definition of the priority mode register. FIG. 22 shows an example in which four priority calculation registers are provided, and shows an example of definitions from the priority calculation register 1 to the priority calculation register 4. FIG. 23 shows each of the priority calculation formulas shown in FIG. Here is a description of the register operators.
FIG. 24 shows a state transition diagram of the method for controlling the priority. FIG. 25 shows a definition and a setting example of the state transition register provided in the memory controller of the present invention.

The present invention is not a variation of the priority determination mode, but the above-described example of the priority enables each of the devices being accessed to issue an access request up to the unit of processing for each device. The memory controller responds to the interrupt access request from the device with the higher priority, so that the device with the lower priority can be re-accessed without being re-queued.

Next, an access report will be described. FIG.
An access request signal, an access permission signal output by the arbiter 30 for each device, and a read / write strobe signal generated by the command control unit are connected to the access report 70 shown in FIG. FIG. 7 is a timing chart of the access report. The access report counts the number of memory access wait cycles for a certain period,
Stored in the memory access wait cycle number register. These pieces of information are stored in registers for each device. An example in which the report is stored in the register of the access report 70 will be described below. It is sufficient that the access report has a function that can be accessed from the CPU and that can set the report timing. Then, it may be accessed by the CPU. Also, as shown in FIG. 2, an output is made from an external terminal of the memory controller to an external device, and the external device is connected to the CP.
The same processing can be performed if access can be made with U. In short, it is only necessary to have a function of saving report information and a function of referring to it. When report information is passed from an external terminal to an external device, the external device may refer to and determine the report information to determine the next priority.

FIG. 26 shows a report of access information for a certain period. Hereinafter, the screen display cycle of the display device will be described as a report unit. In a normal display system, the next drawing process is performed during the display period of one frame, and the screen of each frame is updated. Therefore, the calculation, data transfer process, and drawing process by the drawing device that must be completed in one frame period are completed. The question is whether or not.

According to the present invention, these states can be sequentially traced during debugging, thereby assisting the development of application programs and device drivers. In the present invention, the same information as the above trace is obtained for each user-definable short period 2605, and the result is stored in the next short period 2605.
At 605, the access priority of each device of the priority determination circuit in the memory controller can be changed.

First, a trace in one frame period will be described. In order to trace for one frame period, the frame switching timing is known by a signal 2601 generated by the display device and indicating one frame. The switching timing interval is set as one frame period, and the access information during that period is cumulatively added. For example, if the display device is the highest priority device, and a plurality of devices make an access request at the same time, the display device 4 is given priority 2602. At this time, other devices
In the waiting state, the waiting period is counted by the system clock, and the number of memory access wait cycles represented by the number of system cycles 2603 is cumulatively added for each device for one frame period.

The count 2603 of the number of words to be transferred is also cumulatively added for each frame, similarly to the number of memory access wait cycles. Thus, the data transfer amount required for the drawing process of the drawing device 5 can be calculated in advance, and the data transfer amount is set in the transfer count setting register (TRNENR) 1101 in the mode register unit 90 in FIG. Then, the size is compared for each frame, and an error flag in the drawing device access status register in the status register unit 80 in FIG. 1 is set. When debugging,
This can be used to detect errors. This error flag generates an interrupt by setting an interrupt enable. This is also effective at the time of debugging, but a countermeasure process for an error is prepared in the interrupt processing routine, and a control program relating to an access process to the memory controller at the next frame is prepared to improve the performance of the final system, Contributes to eliminating defects.

Next, a method for acquiring trace information in the short cycle 2605 and changing the access priority of each device using the information in the next short cycle 2606 will be described. As with the method obtained during the one frame period, the short period 26
The memory access information in 05 is acquired. FIG. 9 shows a block diagram in which the number of memory access wait cycles is cumulatively added for a certain period, compared with a setting register, stored in a status register, and an interrupt occurs. FIG. 10 is a block diagram in which the number of words to be transferred is cumulatively added for a certain period of time, compared with a setting register, stored in a status register, and an interrupt occurs. FIG. 3 is a block diagram showing a comparison, storing in a status register, and occurrence of an interrupt.

The check timing strobe 90 of FIG.
The information can be changed depending on whether 1 is a frame unit or a short cycle unit, the check timing strobe 901 is asserted, and the memory access wait cycle register 903 updates the value until the next assertion. Hold. In the next cycle in which the check timing strobe 901 is asserted, the comparator 907 makes a comparison in accordance with a preset comparison mode of the memory access wait cycle comparison mode register 908, and stores the result in the memory access wait cycle status register 906.

Further, a memory access wait cycle comparison interrupt enable register is set, and a memory access wait cycle comparison interrupt 911 is generated.
The CPU receives this interrupt and performs interrupt processing.
When it is no longer necessary, set the memory access wait cycle comparison interrupt clear register to clear the interrupt signal.

FIG. 14 shows a comparison mode of the comparator 907. The comparator 907 compares the value of the memory access wait cycle with the value of the memory access wait cycle number setting register and determines whether the value is equivalent, large or small, and
The above calculation is performed.

A report section relating to the memory access wait cycle shown in FIG. 9 and a calculation section and an interrupt generation section based on the result are prepared for each of the CPU, drawing section, display section and IO section. Performs a comparison operation on an access basis and holds the result.
An interrupt is generated for the PU. Note that the interrupt enable register 910 controls whether or not this interrupt occurs.

FIG. 15 shows the types of access reports. The contents of the access report include the number of memory access waits, the number of words to be transferred, and the number of times of transfer, and these are stored in registers to hold information. Here, these information may be stored in a specific memory area instead of the register. In this case, an access report storage destination address register indicating the start address of the storage destination on the memory is prepared, and the information of the access report shown in FIG. 15 is stored from the address indicated by the register. These access reports,
It is stored for each device that accesses the memory. FIG. 16 shows an example of the definition of the report area start register.

The method of storing the access report, the evaluation thereof, and the occurrence of an interrupt are output from the terminal of the memory controller to the outside, and received externally.
A circuit for storing, evaluating, and generating an interrupt may be separately provided. In this case, the transfer word number register shown in FIG. 10 and the transfer number register shown in FIG. 11 perform the same operation as the memory access wait cycle register.

FIG. 7 shows a method of calculating access report information. FIG. 8 shows a schematic timing chart of FIG. 9, FIG. 10, and FIG. FIG. 12 shows a timing chart of the counter with reset, and FIG. 13 shows a timing chart of the accumulator with reset.

FIG. 27 shows an example of a system using the present memory controller. Since the SDRAM exists on the system bus, the transfer efficiency is increased by using the memory controller of the present invention, and the priority of the CPU is set to the highest, the integrated memory environment of only the memory (SDRAM) managed by the memory controller is used. Can be realized.

[0037]

According to the present invention, there is provided a microcomputer system having a CPU, a drawing device, and a display device.
The required access frequency can be obtained in a certain period, and the CPU and the drawing device can make maximum use of the access capability of the memory of the system.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a configuration of a memory controller of the present invention.

FIG. 2 is an explanatory diagram of another configuration of the memory controller of the present invention.

FIG. 3 is an explanatory diagram of still another configuration of the memory controller of the present invention.

FIG. 4 is an explanatory diagram of a conventional memory controller.

FIG. 5 is a timing chart in the case where a display device having a higher priority accesses while a drawing device is being accessed.

FIG. 6 is a timing chart in a case where a display device having a higher priority accesses while a drawing device is being accessed when banks on a memory are different.

FIG. 7 is a timing chart of an access report of the memory controller of the present invention.

FIG. 8 is a schematic timing chart of a series of processing of a memory controller of the present invention, such as acquisition of report information, comparison with a setting register, storage of a result in a status register, occurrence of an interrupt, and clearing.

FIG. 9 is a block diagram in which the number of memory access wait cycles is cumulatively added for a predetermined period, compared with a setting register, stored in a status register, and an interrupt occurs.

FIG. 10 is a block diagram in which the number of words to be transferred is cumulatively added for a predetermined period, compared with a setting register, stored in a status register, and an interrupt occurs.

FIG. 11 is a block diagram in which the number of transfers is cumulatively added for a certain period, compared with a setting register, stored in a status register, and an interrupt occurs.

FIG. 12 is an explanatory diagram of a counter with reset.

FIG. 13 is an explanatory diagram of an accumulator with reset.

FIG. 14 is an explanatory diagram of a calculation mode of the comparator.

FIG. 15 is an explanatory diagram of types of access reports.

FIG. 16 is an explanatory diagram of a definition of a report area start register.

FIG. 17 is an explanatory diagram of a definition of a priority control register.

FIG. 18 is an explanatory diagram of priority order determination mode control in a priority order control register.

FIG. 19 is an explanatory diagram of bits 9 and 8 in the priority control register.

FIG. 20 is an explanatory diagram of a priority mode register.

FIG. 21 is an explanatory diagram of the definition of a priority mode register.

FIG. 22 is an explanatory diagram of definitions of the priority calculation formula register 1, the priority calculation formula register 2, the priority calculation formula register 3, and the priority calculation formula register 4.

FIG. 23 is an explanatory diagram for explaining the operators of the priority calculation formula register 1, the priority calculation formula register 2, the priority calculation formula register 3, and the priority calculation formula register 4.

FIG. 24 is an explanatory diagram of an example in which priorities are controlled using a state transition diagram.

FIG. 25 is an explanatory diagram of definitions and setting examples of a state transition control register 1, a state transition control register 2, and a state transition control register 3.

FIG. 26 is an explanatory diagram of an access report.

FIG. 27 is an explanatory diagram of a system configuration using a memory controller.

[Explanation of symbols]

1. Memory controller, 2. Memory (SDRAM),
3 ... CPU, 4 ... Display device, 5 ... Drawing device, 6 ... IO device, 7 ... Output signal buffer, 10 ... Address generation unit,
20 selection circuit, 30 arbiter, 32 access permission signal, 33 access request signal, 40 command control unit, 50 priority determination unit, 51 priority signal, 60
... Timer 70 Access report 80 Status register 90 Mode register 100 SGB
C, 111: SRAM, 112: Flash ROM, 1
13 SDRAM, 114 ATAPI, 115 ASI
C, 116 CPU interface unit, 117 display control, 118 drawing control, 119 YUV, 120 D
MA, 121: memory interface unit, 130: C
PU register access bus, 901, check timing strobe, 903, memory access wait cycle register, 906, memory access wait cycle status register, 907, comparator, 908, memory access wait cycle comparison mode register, 910 ...
Interrupt enable register, 911: memory access wait cycle comparison interrupt, 1101: transfer count setting register (TRNENR), 2601 ... signal indicating one frame, 2605, 2606 ... short cycle.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiro Nakatsuka 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Inventor Yuichiro Morita 7-1 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Kazushige Yamagishi 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi, Ltd. Semiconductor Group (72) Inventor Yutaka Okada Kodaira, Tokyo 5-20-1, Ichijomizuhoncho, F-term in Hitachi Semiconductor Group 5B042 GC08 MC06 MC25 MC26 MC28 5B060 CD14 KA03 5C082 AA01 BA02 BA12 BB15 BB22 BB42 CB01 DA54 DA64 EA11 MM02

Claims (6)

[Claims] 1. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory A memory controller that controls memory access at the request timing of each device, calculates the number of access words of each device, the number of wait cycles for an access request, and the number of accesses in a certain period; A memory controller for storing the number of access words, the number of wait cycles for an access request, and the number of accesses in a register in the memory controller or in a memory area. 2. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory A memory controller that controls memory access at the request timing of each device, calculates the number of access words of each device, the number of wait cycles for an access request, and the number of accesses for each device, A memory controller having a terminal capable of outputting the number of access words, the number of wait cycles for an access request, and the number of accesses to the outside of the memory controller. 3. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory A memory controller that controls memory access at the request timing of each device, calculates the number of access words of each device, the number of wait cycles for an access request, and the number of accesses in a settable period; The information of the CPU, the drawing device, the display device, the IO device, the number of access words, the number of wait cycles for an access request, and the number of accesses is stored in a register in the controller, and is equal to a preset limit value. , Compare the magnitude and compare the result with the status flag A memory controller characterized by storing in a register. 4. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory A memory controller that controls memory access at the request timing of each device, calculates the number of access words of each device, the number of wait cycles for an access request, and the number of accesses in a settable period; Store in the register in the controller or the memory area of the specified address,
The CPU, the drawing device, the display device, and the IO device, the number of access words, the number of wait cycles for access requests, and the information on the number of accesses are compared with a preset limit value or are compared in magnitude. A memory controller characterized in that the access order of each device for the next fixed period can be changed based on the following. 5. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory In a memory controller that controls memory access at the request timing of each device, the number of access words of each device, the number of wait cycles for an access request, and the number of accesses in a settable period are calculated. The number of access words on the device,
The number of wait cycles for the access request and the number of accesses are externally output from the terminal of the memory controller, and the number of access words, the number of access words, the number of wait cycles for the access request for each of the CPU, the drawing device, the display device, and the IO device by the external device. Number, and the number of times of access information is equal to a preset limit value, or
A memory controller that performs a magnitude comparison and changes the access order of each device for the next fixed period based on the result. 6. A CPU for performing arithmetic processing and data transfer control
A display device having a frame buffer area in the memory and performing read / write, a drawing device performing graphic drawing and character drawing in the frame buffer, and executing read / write to the memory In a memory controller that controls memory access at the request timing of each device, each device has a priority defined at the time of contention,
When an access request is issued from a device having a higher priority while the device having a lower priority is being accessed, access to a device having a lower priority is interrupted, access to a device having a higher priority is executed, and A memory controller for resuming access of a device having a low number of times, the number of access words of each device during a configurable fixed period, the number of wait cycles for an access request,
And the number of accesses are output from the terminal of the memory controller to an external device, and the external device uses the CPU, the drawing device, the display device, and the IO device for each device, the number of access words, the number of wait cycles for an access request, and the number of access times. A memory controller wherein information is equal to a preset limit value or a magnitude comparison is performed, and based on a result of the comparison, an access order of each device in a next fixed period is changed.