JP2002315210A - Discharge control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a discharge control circuit wherein current consumption during non-discharging operation is reduced and further the speed of response at start of discharge is enhanced. SOLUTION: In the discharge control circuit 1, a first discharge control signal XDIS which oscillates between a ground potential VSS and supply potential VDD is supplied to a first input terminal, and the supply potential VDD is supplied to a second input terminal. A power supply generating potential VH is supplied as a high potential-side supply potential and a ground potential is supplied as a low potential-side supply potential. The discharge control circuit is provided with a two-circuit NAND circuit 3 which outputs the power supply generating potential VH as a second discharge control signal DISCTL to an external discharge circuit 2 when the supply potential VDD is off. The two-input NAND circuit includes pairs of N-channel MOS transistors 4 and 5 and P- channel MOS transistors 7 and 6 whose gates are connected in common with the first and second input terminals, respectively, and the P-channel MOS transistors have a on-resistance value which is higher than the N-channel MOS transistors do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for controlling a discharge circuit in a semiconductor integrated circuit to discharge accumulated charges.

[0002]

2. Description of the Related Art In a power supply generating circuit, it is common to store a charge using a capacitor in order to stably maintain a generated potential. However, when a power supply is cut off, a reverse flow of the stored charge causes a semiconductor chip or a semiconductor chip to lose charge. The LCD panel may be damaged. Therefore, it is important that the discharge control circuit controls the discharge circuit to perform the discharge.

[0003] A conventional discharge control circuit will be described below.

FIG. 4 is a circuit diagram of a conventional discharge control circuit. In FIG. 4, a discharge control circuit 50 includes N-channel type MOS transistors 51 and 52 and a P-channel type MOS transistor.
And a transistor 53. The N-channel MOS transistor 51 includes a power supply potential VDD and a ground potential VSS.
Is supplied to the gate, and the ground potential VSS is applied to the source. N
The power supply potential VDD is applied to the gate of the channel type MOS transistor 52, and the drain of the N-channel type MOS transistor 51 is connected to the source. The P-channel MOS transistor 53 has a gate connected to the ground potential V.
The power supply generation potential VH is applied to the source, the drain of the N-channel MOS transistor 52 is connected to the drain, and the discharge control signal DISCTL is output to the VH discharge circuit 55 from the commonly connected drain. Here, the on-resistance value of P-channel MOS transistor 53 is set to be much larger than that of N-channel MOS transistors 51 and 52.

In the VH discharge circuit 55, a discharge control signal DISCTL is supplied to a gate, and a ground potential VS is supplied to a source.
It is constituted by an N-channel MOS transistor 54 to which S is applied and a power supply generation potential VH is applied to the drain.

Next, the operation of discharging the power generation potential VH when the power supply potential VDD is turned off in the discharge control circuit 50 configured as described above will be described.

First, when the discharging operation is not performed, the power supply potential VDD is on and the discharge control base signal X
DIS is the power supply potential VDD, and the discharge control signal DISC
TL is almost equal to the ground potential VSS, and N
The channel type MOS transistor 54 is off.

Next, when the power supply potential VDD is turned off, the N-channel MOS transistor 52 is turned off, the discharge control signal DISCTL becomes the power generation potential VH, the N-channel MOS transistor 54 is turned on, and the power generation potential VH
Is discharged.

[0009]

In this conventional discharge control circuit, when no discharge is performed (when the power supply potential VDD is on,
When the discharge control base signal XDIS is at the power supply potential VDD), the through current I flows.
It is necessary to increase the on-resistance value of the channel type MOS transistor 53 (that is, increase the gate length). The circuit area of each of the N-channel type MOS transistors 51 and 52 is set to S, and the circuit area of the P-type MOS transistor 53 is set. Is 1000 × S, the total circuit area is 1002 × S, and there is a problem that the circuit area becomes large.

The P-channel type MOS transistor 5
3, the discharge control signal DISCTL is set to the power generation potential at the time of discharging (when the discharge control base signal XDIS is at the ground potential VSS or the power supply potential VDD is off). There is a problem that the time to reach VH is long and the response speed is slow.

Further, since the discharging operation is performed only when one kind of power supply potential (here, power supply potential VDD) is turned off, the discharge control circuit having such a configuration is provided with a plurality of power supply input specifications (power supply potential VDD, power supply potential VCC). And the like, there is a problem that the power generation potential VH is not discharged when the power supply potential VCC or the like is turned off.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide a discharge control circuit which has a small circuit area, a high response speed, and is compatible with a plurality of power supplies.

[0013]

To achieve the above object, a first discharge control circuit according to the present invention comprises a first potential (VSS) and a second potential (VDD) higher than the first potential.
Is supplied to the first input terminal, the second potential is supplied to the second input terminal, and a third potential (XDIS) higher than the first potential is supplied to the first input terminal. VH) is supplied as a high-potential-side power supply potential, the first potential is supplied as a low-potential-side power supply potential, and when the second potential is turned off, the third potential is supplied to an external discharge circuit by a second discharge. A two-input NAND circuit that outputs a control signal (DISCTL) is provided. The two-input NAND circuit includes a pair of N-channel and P-channel MOS transistors whose gates are commonly connected to first and second input terminals, respectively. Including
A P-channel MOS transistor is an N-channel MO
It has a higher on-resistance than the S transistor, and outputs a third potential supplied to the source from the drain as a second discharge control signal.

In the first discharge control circuit, the two-input NAND circuit includes a first N-channel MOS transistor having a gate supplied with a first discharge control signal and a source applied with a first potential; A second potential is applied to the gate, a second N-channel MOS transistor having the source connected to the drain of the first N-channel MOS transistor, a second potential is applied to the gate, and a third potential is applied to the source. Is applied, and the drain of the second N-channel type M
The first P in which the drains of the OS transistors are commonly connected
A first discharge control signal is supplied to the channel type MOS transistor and the gate, a third potential is applied to the source,
A drain of the second N-channel MOS transistor is commonly connected to the drain, and a second P-channel MOS transistor that outputs a second discharge control signal from the common connection portion.

According to the first discharge control circuit having the above configuration,
The current consumption when the discharging operation is not performed can be reduced as compared with the related art, and the discharging operation can be started faster than before when the power supply potential (the second potential VDD) is off.

In order to achieve the above object, a second discharge control circuit according to the present invention oscillates between a first potential (VSS) and a second potential (VDD) higher than the first potential. The first discharge control signal (XDIS) is caused to oscillate between a first potential and a third potential (VH) higher than the first potential.
A level shift circuit for converting the level into a discharge control signal (XD), a second discharge control signal is supplied to a first input terminal, and a second potential is supplied to a second input terminal. The potential is supplied as a power supply potential on a high potential side, the first potential is supplied as a power supply potential on a low potential side, and when the second potential is off, the third potential is supplied to an external discharge circuit by a third discharge control. A two-input NAND circuit for outputting a signal (DISCTL) as a signal (DISCTL). The two-input NAND circuit includes a pair of N-channel and P-channel MOS transistors whose gates are commonly connected to a second input terminal. MO
The S transistor has a larger on-resistance than the N-channel MOS transistor, and the third transistor supplied to the source
Is output from the drain as a third discharge control signal.

In the second discharge control circuit, the two-input NAND circuit includes a first N-channel MOS transistor having a gate supplied with a second discharge control signal and a source applied with a first potential; A second potential is applied to the gate, a second N-channel MOS transistor having the source connected to the drain of the first N-channel MOS transistor, a second potential is applied to the gate, and a third potential is applied to the source. Is applied, and the drain of the second N-channel type M
The first P in which the drains of the OS transistors are commonly connected
A second discharge control signal is supplied to the channel type MOS transistor and the gate, a third potential is applied to the source,
A drain of the second N-channel MOS transistor is commonly connected to the drain, and a second P-channel MOS transistor that outputs a third discharge control signal from the common connection portion.

According to the second discharge control circuit having the above configuration,
In addition to the advantages of the first discharge control circuit, the circuit area can be reduced.

To achieve the above object, a third discharge control circuit according to the present invention oscillates between a first potential (VSS) and a second potential (VDD) higher than the first potential. The first discharge control signal (XDIS) is supplied to the first input terminal, the second potential is supplied to the second input terminal, and the third potential (VCC) higher than the first potential is supplied to the third input terminal. A fourth potential (VH) higher than the first potential is supplied as a power supply potential on the high potential side, the first potential is supplied as a power supply potential on the low potential side, and the second or third potential is supplied to the input terminal. Is a three-input NAND that outputs the fourth potential as a second discharge control signal (DISCTL) to an external discharge circuit when the potential of the third input is turned off.
The three-input NAND circuit includes a pair of N-channel and P-channel MOS transistors having gates connected in common at first, second and third input terminals, respectively. Has a larger on-resistance than an N-channel MOS transistor, and outputs the fourth potential supplied to the source from the drain as a second discharge control signal.

In the third discharge control circuit, the three-input NAND circuit includes a first N-channel MOS transistor having a gate supplied with a first discharge control signal and a source applied with a first potential; A second potential is applied to the gate, a second potential is applied to the gate, a second potential is applied to the gate, and a second potential is applied to the source. A third N-channel MOS transistor to which the drain of the N-channel MOS transistor is connected, a second potential applied to the gate, a fourth potential applied to the source, and a third N-channel MOS transistor applied to the drain A first P-channel type MO in which drains of MOS transistors are commonly connected
An S transistor, a second P-channel MOS transistor in which a third potential is applied to the gate, a fourth potential is applied to the source, and a drain of the third N-channel MOS transistor is commonly connected to the drain; , The first discharge control signal is supplied to the gate, the fourth potential is applied to the source, the drain of the third N-channel MOS transistor is commonly connected to the drain, and the second discharge control signal is supplied from the common connection. And a third P-channel MOS transistor that outputs the same.

According to the third discharge control circuit having the above configuration,
In addition to the advantages of the first discharge control circuit, a plurality of power supply potentials (second potential VDD, third potential V
CC), the discharge operation can be realized even when any one of the power supply potentials is turned off.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a discharge control circuit according to the embodiment.

In FIG. 1, reference numeral 3 denotes a two-input NAND circuit, which comprises an N-channel MOS transistor 4, an N-channel MOS transistor 5, a P-channel MOS transistor 6, and a P-channel MOS transistor 7. , P-channel MOS transistors 6 and 7
Is set to be larger than the resistance values of the N-channel MOS transistors 4 and 5, the power generation potential VH is supplied as a high potential power supply potential, and the ground potential VSS is supplied as a low potential power supply potential. ing.

Reference numeral 1 denotes a discharge control circuit, which has a power supply potential VDD.
Control signal XDIS that oscillates between the ground and the ground potential VSS is used as the first input signal, and the power supply potential VDD is set to the second input signal.
And a discharge control signal DISCTL.

Reference numeral 2 denotes a discharge circuit, which is an N-channel type MOS.
The discharge control signal DISCTL is input as a gate signal.

Next, the discharging operation of the power generation potential VH when the power supply potential VDD is turned off in the discharge control circuit having this configuration will be described.

First, when the discharge operation is not performed, the power supply potential VDD is on and the discharge control base signal X
DIS is the power supply potential VDD, and the discharge control signal DISC
TL is almost equal to the ground potential VSS, and N
The channel type MOS transistor 8 is off.

Next, when the power supply potential VDD turns off, the N-channel MOS transistor 5 turns off, the P-channel MOS transistor 6 turns on, and the discharge control signal DIS
CTL becomes the power generation potential VH, and the N-channel MOS
The transistor 8 is turned on, and the power generation potential VH is discharged.

When the first discharging operation is not performed, that is, when the power supply potential VDD ≧ the power generation potential VH, the through current I does not flow, so that lower power consumption can be realized as compared with the related art.

In addition, power supply potential VDD <power supply generation potential VH
, The P-channel MOS transistors 6 and 7
When the through current I is designed to be equal to the conventional one, the on-resistance value of the P-channel MOS transistor 6 becomes the conventional P-channel MOS transistor 53 (FIG. 4). Of the on-resistance value of
Double.

However, at the time of discharging when the power supply potential VDD is turned off, the gate potential of the P-channel type MOS transistor 6 becomes the ground potential VSS, so that the P-channel type MOS transistor 6 is turned off.
The on-resistance value of S transistor 6 is reduced to 以下 or less, which is lower than the on-resistance value of conventional P-channel MOS transistor 53.

Thus, the discharge control signal DISCTL
Becomes faster than in the prior art, and the N-channel MOS transistor 8 turns on faster than in the prior art, realizing a high-speed response.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a discharge control circuit according to the embodiment. The discharge control circuit 10 according to the present embodiment is such that a level shift circuit 13 is provided on one input terminal side of the two-input NAND circuit 3 of the first embodiment.
Of the P-channel MOS transistors constituting the D circuit 3, only the P-channel MOS transistor 6 has an on-resistance greater than the N-channel MOS transistors 5 and 4, and the on-resistance of the P-channel MOS transistor 7 Except that the value may be small, the other components are the same, and are denoted by the same reference numerals and description thereof will be omitted.

The level shift circuit 13 has a power supply potential VDD.
It has a function of converting the discharge control base signal XDIS that oscillates between the power supply generation potential VH and the ground potential VSS to the discharge control base signal XD that oscillates between the power supply generation potential VH and the ground potential VSS.

Next, the discharging operation of the power generation potential VH when the power supply potential VDD is turned off in the discharge control circuit having this configuration will be described.

First, when the discharging operation is not performed, the power supply potential VDD is on and the discharge control base signal X
DIS is the power supply potential VDD, and the discharge control signal DISC
TL is almost equal to the ground potential VSS, and N
The channel type MOS transistor 8 is off.

Next, when the power supply potential VDD turns off, the N-channel MOS transistor 5 turns off, the P-channel MOS transistor 6 turns on, and the discharge control signal DIS
CTL becomes the power generation potential VH, and the N-channel MOS
The transistor 8 is turned on, and the power generation potential VH is discharged.

When the first discharging operation is not performed, that is, when the power supply potential VDD ≧ the power generation potential VH, the through current I does not flow, so that lower power consumption can be realized as compared with the related art.

The power supply potential VDD <the power supply generation potential VH
In this case, the P-channel MOS transistor 7 is off, and if the through current I flowing through the P-channel MOS transistor 6 is designed to be equal to the conventional one, the on-resistance value of the P-channel MOS transistor 6 becomes It is equal to the on-resistance value of P-channel MOS transistor 53 (FIG. 4).

However, at the time of the discharge in which the power supply potential VDD is turned off, the gate potential of the P-channel MOS transistor 6 becomes the ground potential VSS.
The on-resistance value of S transistor 6 is reduced to 以下 or less, which is lower than the on-resistance value of conventional P-channel MOS transistor 53.

Thus, the discharge control signal DISCTL
Becomes faster than in the prior art, and the N-channel MOS transistor 8 turns on faster than in the prior art, realizing a high-speed response.

When the through current I is designed to be equal to that of the conventional one, the gate potential of the P-channel MOS transistor 6 is the power supply potential VDD, and the gate potential of the conventional P-channel MOS transistor 53 is the ground potential VSS. Therefore, if the circuit area of the P-channel MOS transistor 6 can be reduced to １ ／ of the circuit area (1000 × S) of the conventional P-channel MOS transistor 53, the level shift circuit 13 is configured. N-channel MOS transistors 4, 5, 14, 16,
18 and P-channel MOS transistors 7, 15, 1
Since the circuit areas of 7 and 19 are small, if each is S, the total circuit area is 509 × S.
It can be smaller than × S.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a discharge control circuit according to the embodiment. In the present embodiment, a plurality of power supply potentials (VDD, VCC)
It corresponds to.

In FIG. 3, reference numeral 32 denotes a three-input NAND circuit, which includes N-channel MOS transistors 33 and 34,
35, P-channel MOS transistors 36, 37,
38, the resistance values of the P-channel MOS transistors 36, 37, 38 are set to be larger than the resistance values of the N-channel MOS transistors 33, 34, 35, and the power generation potential VH And the ground potential VSS is supplied as a power source on the low potential side.

Reference numeral 30 denotes a discharge control circuit, which has a power supply potential VD.
A three-input NAND circuit that uses a discharge control base signal XDIS that oscillates between D and a ground potential VSS as a first input signal, uses the power supply potential VDD as a second input signal, and uses the power supply potential VCC as a third input signal. 32, and outputs a discharge control signal DISCTL.

Next, the discharging operation of the power generation potential VH when the power supply potential VDD or the power supply potential VCC is turned off in the discharge control circuit having this configuration will be described.

First, when the discharging operation is not performed, the power supply potential VDD and the power supply potential VCC are on, the discharge control base signal XDIS is the power supply potential VDD,
The discharge control signal DISCTL is substantially equal to the ground potential VSS, and the N-channel MOS transistor 8
Is off.

Next, when the power supply potential VDD is turned off,
The N-channel MOS transistor 35 is turned off, the P-channel MOS transistor 36 is turned on, the discharge control signal DISCTL becomes the power generation potential VH, the N-channel MOS transistor 8 is turned on, and the power generation potential VH is discharged. .

When the power supply potential VCC is turned off,
The N-channel MOS transistor 34 is turned off, the P-channel MOS transistor 37 is turned on, the discharge control signal DISCTL becomes the power generation potential VH, the N-channel MOS transistor 8 is turned on, and the power generation potential VH is discharged. .

As described above, a plurality of power supply potentials VDD, VC
Even when any one of the power supply potentials C is turned off, the discharging operation can be realized.

When the first discharging operation is not performed,
That is, when the power supply potential VDD ≧ the power generation potential VH, the through current I does not flow, so that lower power consumption can be realized as compared with the related art.

[0053]

As described above, according to the present invention,
The current consumption when the discharging operation is not performed can be reduced as compared with the related art, and the discharging operation can be started at a higher speed than the related art when the power supply potential VDD is off.

Further, the circuit area can be reduced as compared with the prior art.

Further, even when any one of the plurality of power supply potentials is turned off, the discharging operation can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a discharge control circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a discharge control circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a discharge control circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional discharge control circuit.

[Explanation of symbols]

1, 10, 30 Discharge control circuit 2 Discharge circuit 3 2-input NAND circuit 32 3-input NAND circuit 13 Level shift circuit 4, 5, 8, 14, 16, 18, 33, 34, 35N
Channel MOS transistors 6, 7, 15, 17, 19, 36, 37, 38 P-channel MOS transistors XDIS Discharge control base signal DISCTL Discharge control signal VDD Power supply potential VCC Power supply potential VH Power supply generation potential VSS Ground potential

Claims (6)

[Claims] 1. A first discharge control signal oscillating between a first potential and a second potential higher than the first potential is supplied to a first input terminal, and the second potential is changed to a second potential. 2, a third potential higher than the first potential is supplied as a high-potential power supply potential, the first potential is supplied as a low-potential power supply potential, and the second potential is supplied to the second input terminal. A two-input NAND circuit that outputs the third potential as a second discharge control signal to an external discharge circuit when the potential is turned off, wherein the two-input NAND circuit includes a first input terminal and a second input terminal. Each of the transistors includes a pair of N-channel and P-channel MOS transistors whose gates are connected in common. The P-channel MOS transistor has a larger on-resistance than the N-channel MOS transistor and is supplied to a source. Discharge control circuit, characterized in that the output from the drain of the third potential as the second discharge control signal. 2. The two-input NAND circuit, wherein a first discharge control signal is supplied to a gate and a first potential is applied to a source.
A second potential is applied to a transistor and a gate, and the first potential is applied to a source.
A second N-channel MOS transistor to which a drain of the N-channel MOS transistor is connected; a gate to which the second potential is applied;
Is applied, a drain of the second N-channel MOS transistor is commonly connected to a first P-channel MOS transistor, a gate is supplied with the first discharge control signal, and a source is A third potential is applied, a drain of the second N-channel MOS transistor is commonly connected to a drain, and a second P-channel MOS transistor that outputs the second discharge control signal from a common connection portion. The discharge control circuit according to claim 1, wherein the discharge control circuit includes: 3. A first discharge control signal that oscillates between a first potential and a second potential higher than the first potential, the first discharge control signal oscillating between the first potential and a third potential higher than the first potential. A level shift circuit that performs level conversion to a second discharge control signal that oscillates between the first discharge terminal and the second discharge control signal, the second discharge control signal being supplied to a first input terminal;
The second potential is supplied to a second input terminal, and the third potential is supplied to the third input terminal.
Is supplied as a power supply potential on the high potential side,
Is supplied as a low-potential-side power supply potential, and the second
And a two-input NAND circuit that outputs the third potential as a third discharge control signal to an external discharge circuit when the potential of the second input terminal is turned off. The two-input NAND circuit has a gate connected to the second input terminal. A pair of commonly connected N-channel and P-channel MOS transistors,
Discharge control, wherein the S transistor has an on-resistance greater than that of the N-channel MOS transistor, and outputs the third potential supplied to the source from the drain as the third discharge control signal. circuit. 4. The two-input NAND circuit, wherein the second discharge control signal is supplied to a gate, and the first potential is applied to a source.
A second potential is applied to a transistor and a gate, and the first potential is applied to a source.
A second N-channel MOS transistor to which a drain of the N-channel MOS transistor is connected; a gate to which the second potential is applied;
Is applied, the drain of the second N-channel MOS transistor is connected in common to the first P-channel MOS transistor, the gate is supplied with the second discharge control signal, and the source is A third potential is applied, a drain of the second N-channel MOS transistor is commonly connected to a drain, and a second P-channel MOS transistor that outputs the third discharge control signal from a common connection portion. The discharge control circuit according to claim 3, wherein the discharge control circuit includes: 5. A first discharge control signal that oscillates between a first potential and a second potential higher than the first potential is supplied to a first input terminal, and the second potential is changed to a second potential. 2 and a third potential (VC) higher than the first potential.
C) is supplied to a third input terminal, a fourth potential (VH) higher than the first potential is supplied as a power supply potential on a high potential side, and the first potential is supplied as a power supply potential on a low potential side. A three-input NAND circuit that is supplied and outputs the fourth potential as a second discharge control signal to an external discharge circuit when the second or third potential is turned off. First, second and third
Include a pair of N-channel and P-channel MOS transistors each having a gate connected in common, wherein the P-channel MOS transistor has a larger on-resistance than the N-channel MOS transistor. A discharge control circuit for outputting the fourth potential supplied to the source from the drain as the second discharge control signal. 6. The three-input NAND circuit, wherein the first discharge control signal is supplied to a gate, and the first potential is applied to a source.
The third potential is applied to a transistor and a gate, and the first potential is applied to a source.
A second N-channel MOS transistor to which the drain of the N-channel MOS transistor is connected; a gate to which the second potential is applied;
A third N-channel MOS transistor to which the drain of the N-channel MOS transistor is connected; a gate to which the second potential is applied;
A first P-channel MOS transistor having a drain commonly connected to a drain of the third N-channel MOS transistor; a third potential applied to a gate;
A second P-channel MOS transistor having a drain connected in common with a drain of the third N-channel MOS transistor, a gate supplied with the first discharge control signal, and a source connected with the source. A fourth potential is applied, a drain of the third N-channel MOS transistor is commonly connected to a drain, and a third P-channel MOS transistor that outputs the second discharge control signal from a common connection portion. 6. The discharge control circuit according to claim 5, further comprising: