JP2000068804A - Output circuit for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the output circuit for a semiconductor device that prevents a steady-state current from flowing from a power supply to a ground line after switching resulting in increasing power consumption regardless of a level outputted from an output terminal. SOLUTION: The output circuit has an output section of a structure where a high voltage N-channel MOS transister(TR) N1 and a high voltage N-channel MOS TR N2 are connected and this output section outputs an output voltage OUT1 via an output terminal 6. A P-channel thick gate TR P1 having a gate with a thickness to which a voltage from a power supply voltage VDD2 up to a ground level GND is applied is connected between a power supply 4 and a gate of the N-channel MOS TR N1. A level shift section 1 that converts a low level signal into a level from the power supply voltage VDD2 to the ground level GND connects to the gate of the P-channel thick gate TR P1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output circuit of a semiconductor device capable of reducing power consumption.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an output circuit of a conventional semiconductor device. As shown in FIG.
Channel MOS transistor N5 and high-voltage N-channel MO
An output portion having a structure connected to the S transistor N6 is provided, and an output voltage OUT2 is output from the output portion via an output terminal 13. Power supply 1
1 and N-channel MOS transistor N5
A high-voltage thin gate P-channel MOS transistor P4 having a gate thinner than the channel MOS transistors N5 and N6 and controlling the gate voltage of the N-channel MOS transistor N5 is connected.

Since the high-voltage power supply potential VDD2 cannot be applied between the gate and the source of the high-voltage thin gate P-channel MOS transistor P4, the power supply 11
A resistor R3 is connected between the transistor and the gate of the P-channel MOS transistor P4. Further, the resistor R3 includes:
Gate of P-channel MOS transistor P4 and resistor R3
High-voltage N-channel M for controlling the potential of node f (gate voltage of P-channel MOS transistor P4) between
The OS transistor N7 is connected, and the power supply 11 is connected to the ground point 14 via the resistor R3 and the N-channel MOS transistor N7. As described above, in the output circuit of the conventional semiconductor device, the resistor R3 and the N-channel M
The OS transistor N7 constitutes the level shift unit 3.

Further, a gate of an N-channel MOS transistor N7 is connected to a power supply potential VDD2 from an input terminal 12.
The low-voltage signal IN2 having a lower voltage level is input, and the low-voltage signal IN2 is input via the inverter INV7 to the gate of the N-channel MOS transistor N6 constituting the output unit. Has become.

FIG. 4 is a timing chart showing the operation of an output circuit of a conventional semiconductor device. As shown in FIG.
First, when the low voltage signal IN2 input from the input terminal 12 changes from the ground potential GND to the potential VDD1, the potential at the node h between the inverter INV7 and the gate of the N-channel MOS transistor N6 changes from the potential VDD1 to the ground potential G.
Since it changes to ND, the N-channel MOS transistor N6 in the output section is turned off.

At the same time, the potential at node g between input terminal 12 and N-channel MOS transistor N7 changes from ground potential GND to potential VDD1, so that N-channel MOS transistor N7 is turned on. Then, the potential of the node f starts to fall, reaches a predetermined voltage V by the voltage division of the resistance of the resistor R3 and the on-resistance of the N-channel MOS transistor N7, and a voltage is applied between the gate and the source of the P-channel MOS transistor P4. This allows P
The channel MOS transistor P4 is turned on, a current flows through the resistor R2, a gate voltage is applied to the N-channel MOS transistor N5 in the output section, and the N-channel
S transistor N5 is turned on. Therefore, charging of the capacitive load CL1 connected to the output terminal 13 is started,
Thereafter, the potential output from the output terminal 13 is changed to the ground potential G.
The potential changes from ND to the potential VDD2.

[0007]

However, when the above-mentioned conventional output circuit is used, even after the potential output from the output terminal 13 changes to the potential VDD2, the power supply 11 is connected to the ground point in the level shift unit 3. Since the steady current I5 continues to flow toward the power supply 14, the power consumption is increased, which causes a problem that the IC generates heat and the like.

Heretofore, various output circuits having a level shift circuit have been disclosed (JP-A-61-19).
8915, JP-A-63-105522, JP-A-7-302842, JP-A-8-307242
And JP-A-59-212283). However, power consumption cannot be sufficiently reduced by using any of these circuits.

The present invention has been made in view of such a problem, and regardless of the potential output from the output terminal,
It is an object of the present invention to provide an output circuit of a semiconductor device capable of preventing a steady current from flowing from a power supply to a ground line after a switching operation and increasing power consumption.

[0010]

An output circuit of a semiconductor device according to the present invention comprises a power supply for outputting a predetermined voltage, an output terminal for outputting a signal, and an output transistor unit for transmitting an output signal to the output terminal. A first MOS transistor connected between the power supply and the output transistor unit for controlling a voltage input to the output transistor unit, and an external input signal having a voltage level lower than the power supply potential is grounded from the power supply potential to the ground. A level shift unit that converts the voltage to a level up to the potential and applies the voltage to the gate of the first MOS transistor; a ground line connected to the level shift unit;
It is characterized by having.

The output transistor section includes a second MOS transistor connected between the power supply and the output terminal, and a third MOS transistor connected between the ground line and the output terminal.
And a MOS transistor. Also,
The first MOS transistor may have a gate with a thickness capable of applying a voltage from a ground potential to a power supply potential.

Further, the level shift section has a source connected to the power supply and a drain connected to the first MO.
A fourth MOS transistor connected to the gate of the S transistor; a fifth MOS transistor having a drain connected to the gate of the first MOS transistor and a source connected to the ground line;
The source connected to the gate of the OS transistor is connected to the fourth transistor.
A sixth MOS transistor having a drain connected to the source of the MOS transistor and a drain connected to the gate of the fourth MOS transistor, and a drain connected to the sixth MOS transistor;
A seventh MOS transistor connected to the drain of the OS transistor and having a source connected to the ground line.

Still further, the output circuit of the semiconductor device according to the present invention comprises: an input terminal to which an external input signal is input;
An output control unit connected between the input terminal and the level shift unit and the output transistor unit for converting the input signal and sending the converted signal to the level shift unit and the output transistor unit may be provided. In this case, the output control unit is connected to a gate of a fifth MOS transistor and a gate of a seventh MOS transistor of the level shift unit, and a third MOS transistor of the output transistor unit.
The third, fifth, and seventh MOS transistors may be connected to a gate of the transistor to perform on / off operations based on the input signal.

According to the present invention, the output circuit of the semiconductor device has a level shift section for applying a voltage from the power supply potential to the ground potential to the gate of the first MOS transistor for controlling the voltage input to the output transistor section. Since the first MOS transistor can be operated at a voltage from the power supply potential to the ground potential by this level shift unit, an output characteristic independent of the power supply potential can be obtained, and a signal output from the output terminal is supplied to the power supply potential. Alternatively, it is possible to prevent a steady current from flowing from the power supply to the ground line after changing to the ground potential, thereby reducing power consumption.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an output circuit of a semiconductor device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing an output circuit of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the output circuit is a high voltage N-channel MOS transistor (second MO transistor).
An output portion (output transistor portion) having a structure in which an S transistor) N1 and a high-voltage N-channel MOS transistor (third MOS transistor) N2 are connected, and an output voltage OUT1 is output from the output portion via an output terminal 6 It is output. Power supply 4 and N-channel M
Between the gate of the OS transistor N1 and the power supply potential V
A high-voltage P-channel thick gate transistor (first MOS transistor) P1 having a gate with a thickness capable of applying a voltage from DD2 to the ground potential GND is connected, and the P-channel thick gate transistor P1 causes an N-channel MOS transistor. The gate voltage of N1 is controlled. Further, between the gate and the source of the N-channel MOS transistor N1, a resistor R1 for applying a gate voltage to the N-channel MOS transistor N1 and clamping it to a predetermined voltage and a Zener diode Di1 are connected in parallel.

The gate of the N-channel MOS transistor N2 has a voltage level lower than the power supply potential VDD2, and receives a low-voltage signal output from the output control unit 2. Channel MO
The on / off operation of the S transistor N2 is performed. The output control unit 2 has a plurality of inverters.
From an input terminal 5 via an inverter INV4, INV5 and INV6 in the N-channel MOS transistor N2.
, A low-voltage signal is input to the gate.

Further, the gate of the P-channel thick gate transistor P1 is connected to a level shift unit 1 for converting a low-voltage signal from the power supply potential VDD2 to the amplitude of the level of the ground potential GND. That is, the drain of the high-voltage thick gate P-channel MOS transistor (fourth MOS transistor) P2 having a gate with a thickness capable of applying a voltage from the power supply potential VDD2 to the ground potential GND is connected to the gate of the P-channel thick gate transistor P1. , High pressure N
The drain of the channel MOS transistor (fifth MOS transistor) N3 and the gate of a high-voltage thick gate P-channel MOS transistor (sixth MOS transistor) P3 having a gate with a thickness capable of applying a voltage from the power supply potential VDD2 to the ground potential GND are provided. They are connected via a node a. The gate of the high-voltage N-channel MOS transistor N3 is connected to the output control unit 2, and a low-voltage signal is input from the input terminal 5 to the gate of the high-voltage N-channel MOS transistor N3 via the inverters INV2 and INV3 in the output control unit 2. It is supposed to be.

The gate of the P-channel MOS transistor P2 has a high-voltage thick gate P-channel MOS transistor P
3 and the drain of a high-voltage N-channel MOS transistor (seventh MOS transistor) N4 are connected via a node b. The gate of the high-voltage N-channel MOS transistor N4 is connected to the output control unit 2, and the input terminal 5 is connected via the inverter INV1 in the output control unit 2.
Thus, a low-voltage signal is input to the gate of the high-voltage N-channel MOS transistor N4.

The operation of the output circuit thus configured will be described below. FIG. 2 is a timing chart showing the operation of the output circuit of the semiconductor device according to the embodiment of the present invention. From the input terminal 5, from the ground potential GND to the potential VDD
When the input signal IN1 that changes to 1 is input, the output control unit 2 and the high-voltage N-channel MOS
A signal sent to a node c between the transistor N4 and a node e between the output control unit 2 and the high-voltage N-channel MOS transistor N2 changes from the potential VDD1 to the ground potential GND. As a result, the high-voltage N-channel MOS transistor N4 in the level shift unit 1 and the high-voltage N-channel MOS transistor N2 in the output unit are turned off.

On the other hand, a node d between the output control unit 2 and the high-voltage N-channel MOS transistor N3 is output from the output control unit 2.
Is changed from the potential GND to the potential VDD1 after a predetermined delay time, first, the high-voltage N-channel MOS transistor N3 in the level shift unit 1 is turned on. Then, the potential at the node a in the level shift unit 1 starts to fall, and the P-channel thick gate transistor P1 and the high-voltage thick gate P-channel MOS transistor P3 in the level shift unit 1 are turned on. As a result, the potential at the node b in the level shift unit 1 starts to rise, and the high-voltage thick gate P-channel MOS transistor P2 is turned off.

In such an operation, during the period from when the high-voltage N-channel MOS transistor N3 is turned on to when the high-voltage thick gate P-channel MOS transistor P2 is turned off, the high-voltage thick gate P-channel MOS transistor P2 is turned off. Through current I2 flows toward high-voltage N-channel MOS transistor N3. Also, when the P-channel thick gate transistor P1 is turned on, a current starts flowing through the resistor R1 and the high-voltage N-channel MO
A gate voltage is applied between the source and the gate of S transistor N1, and high-voltage N-channel MOS transistor N1 is applied.
Is turned on.

When a predetermined current flows through the resistor R1, a high voltage N
The gate voltage of the channel MOS transistor N1 is clamped by the Zener diode Di1. At this time, regardless of the value of the power supply voltage VDD2 input from the power supply 4, the gate voltage determined by the Zener diode Di1 causes the high-voltage N-channel M
A current I3 is generated toward the OS transistor N1.
Then, the capacitive load CL1 connected to the output terminal 6 is charged by the current I3. As described above, the operation of changing the output voltage output from the output terminal 6 from the potential GND to the potential VDD2 without depending on the power supply potential is completed, and the current flowing from the power supply 4 to the ground point 7 becomes zero.

Next, when an input signal IN1 that changes from the potential VDD1 to the potential GND is input from the input terminal 5, the signal sent from the output control unit 2 to the node d changes from the potential VDD1 to the potential GND. I do. Thereby, the high-voltage N-channel MOS transistor N in the level shift unit 1
3 is turned off.

On the other hand, the signal sent from the output control unit 2 to the node c changes from the potential GND to the potential VDD1, so that the potential at the node b in the level shift unit 1 starts falling, and the high-voltage thick gate P-channel MOS Transistor P
2 is turned on. Then, the potential at node a in level shift section 1 starts to rise, and P-channel thick gate transistor P1 and high-voltage thick gate P-channel MOS transistor P3 are turned off.

In such an operation, during the period from when the high-voltage N-channel MOS transistor N4 is turned on to when the high-voltage thick gate P-channel MOS transistor P3 is turned off, the high-voltage thick gate P-channel MOS transistor P3 is turned off. Through current I1 flows toward high-voltage N-channel MOS transistor N4. Further, the P-channel thick gate transistor P1 is turned off, and the resistance R
1 causes the gate and source voltages of the high-voltage N-channel MOS transistor N1 in the output section to have the same potential,
High-voltage N-channel MOS transistor N1 is turned off.

Thereafter, the signal sent from the output control unit 2 to the node e changes from the potential GND to the potential V after a predetermined delay time.
The state changes to DD1, and the high-voltage N-channel MOS transistor N2 in the output section is turned on. As a result, the charge of the capacitive load CL1 connected to the output terminal 6 is discharged, and the high-voltage N-channel MOS transistor N
2, a discharge current I4 flows.

In this embodiment, a low-voltage signal lower than the power supply potential VDD2 of the input signal IN1 is converted into a high-voltage signal at the power supply potential level, and the potentials at the nodes a and b are operated from the power supply potential VDD2 to the ground potential GND. Thus, the on / off operation of the P-channel thick gate transistor P1 is performed. Thereby, the high-voltage N-channel MOS transistor N1 operates, and the potential of the output terminal OUT1 changes. Therefore, according to the present embodiment, the charging / discharging operation of the capacitive load CL1 connected to the output terminal 6 is completed, and the output terminal 6
From the power supply potential VDD2 or the ground potential G
After the change to ND, it is possible to prevent a steady current from flowing between the power supply 4 and the ground point 7.

[0028]

As described in detail above, according to the present invention,
Between the power supply potential and the gate of the first MOS transistor controlling the voltage input to the output transistor section, a first M
A level shift unit for applying a voltage from the power supply potential to the ground potential is connected to the gate of the OS transistor, and the level shift unit allows the first MOS transistor to operate with the voltage from the power supply potential to the ground potential. In addition, an output characteristic independent of the power supply potential can be obtained, and an increase in power consumption due to a steady current flowing from the power supply toward the ground line can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an output circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the output circuit of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing an output circuit of a conventional semiconductor device.

FIG. 4 is a timing chart showing an operation of an output circuit of a conventional semiconductor device.

[Explanation of symbols]

 1, 3; level shift section 2: output control section 4, 11; power supply 5, 12; input terminal 6, 13; output terminal 7, 14;

Claims (7)

[Claims] A power supply for outputting a predetermined voltage; an output terminal for outputting a signal; an output transistor for transmitting an output signal to the output terminal; and an output transistor connected between the power supply and the output transistor. A first MOS transistor for controlling a voltage input to the output transistor section, and an external input signal having a voltage level lower than the power supply potential being converted into a voltage of a level from the power supply potential to the ground potential, and A level shift unit applied to the gate, a ground line connected to the level shift unit,
An output circuit of a semiconductor device, comprising: A second MOS transistor connected between the power supply and the output terminal; and a third MOS transistor connected between the ground line and the output terminal.
2. The output circuit according to claim 1, further comprising a MOS transistor. 3. The output circuit according to claim 1, wherein the first MOS transistor has a gate having a thickness capable of applying a voltage from a ground potential to a power supply potential. 4. The level shift unit includes a fourth MOS transistor having a source connected to the power supply and a drain connected to a gate of the first MOS transistor, and a drain connected to a gate of the first MOS transistor. A fifth MOS transistor having a source connected to the ground line, and a gate connected to the first MOS transistor.
The source is connected to the gate of the transistor and the source is the fourth MO.
A sixth MOS transistor connected to the source of the S transistor and having a drain connected to the gate of the fourth MOS transistor, and a drain connected to the sixth MOS transistor;
A seventh MOS transistor connected to a drain of the transistor and having a source connected to the ground line;
4. The method according to claim 1, further comprising:
13. The output circuit of the semiconductor device according to the paragraph. 5. An input terminal to which an external input signal is input, and an input terminal connected between the input terminal and the level shift unit and the output transistor unit to convert the input signal and convert the input signal to the level shift unit and the output transistor unit. The output circuit of a semiconductor device according to claim 1, further comprising an output control unit that sends the output signal to an output transistor unit. 6. The output control section is connected to a gate of a fifth MOS transistor and a gate of a seventh MOS transistor of the level shift section, and is connected to a gate of a third MOS transistor of the output transistor section. 6. The output circuit according to claim 5, wherein the third, fifth, and seventh MOS transistors are turned on and off based on an input signal. 7. The first, fourth and sixth MOS transistors are first conductivity type MOS transistors, and the second, third, fifth and seventh transistors are second conductivity type MOS transistors.
7. An S-transistor, wherein:
The output circuit of the semiconductor device according to any one of the above.