JP2002299630A - Thin film transistor using integrated thin film of mow/al or al alloy/mow, thin film transistor array and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome the problem of damage to a base film by dry etching when a Ti/Al/Ti film is used as the source/drain wiring electrode of an amorphous silicon thin film transistor. SOLUTION: When MoW/Al/MoW is used as the source/drain wiring electrode, wet etching is realized. The cross section shape of the wiring electrode is controlled by optimizing various conditions. In working the electrode, damage to an underlying semiconductor layer is eliminated and characteristic deterioration is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type liquid crystal display (LCD) and a thin film transistor used for a memory integrated circuit.
or: Hereinafter, abbreviated as TFT. ), A wiring electrode used for an organic EL, and the like, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional thin film transistor has a gate metal film 2 of a predetermined shape, a SiNx film 3 as a gate insulating film, and an amorphous silicon film 4 as a semiconductor film, as shown in FIG. An n + Si film 5 is formed as an impurity semiconductor film for making contact, and a source / drain metal film 6 having a predetermined shape is formed thereon.
To form SiNx as a passivation film 7 thereon
A film is formed, and an ITO film of the transparent conductive film 8 that is in contact with the drain metal via the contact hole is formed thereon. As the source metal film 6, a laminated film of Ti / Al / Ti or the like is used. It has a structure sandwiching Al, which is a low-resistance wiring material, with a barrier metal such as Ti that does not cause thermal diffusion or battery phenomena in an electrolytic solution even when it comes into contact with silicon or an ITO film.

[0003]

However, when a laminated film of Ti / Al / Ti or the like is used as the source metal film 6, it is difficult to perform wet etching, so that dry etching has been performed. Dry etching has good workability but has problems such as damaging the base under some conditions. SUMMARY OF THE INVENTION It is an object of the present invention to solve these problems of the prior art and to provide a source wiring structure of a thin film transistor capable of producing a large-area display with high stability, that is, high yield. However, these wiring electrodes are not limited to thin film transistors, but are also used as electrodes for organic EL and the like.

[0004]

In order to prevent the source / drain wiring electrodes from being damaged by the dry etching of the base, the source / drain wiring electrodes are processed by a wet etching method. Wet etching is possible,
Further, it has a three-layer structure of MoW / Al or Al alloy / MoW, which can be processed with the same etching solution and has low resistance and does not cause thermal diffusion or corrosion during the process.

In order to make the processed shape of MoW / Al or Al alloy / MoW a positive taper shape, when the intermediate layer is an Al layer, the W concentration in the upper and lower MoW layers is 3 at% or more and 15 at% or more.
If the intermediate layer is an Al alloy layer, the upper and lower Mo layers
The W concentration in the W layer is set to 16 at% or more and 40 at% or less. A mixed solution of phosphoric acid, nitric acid, acetic acid, and water is used as an etching solution. In order to make the etching rate of the upper and lower MoW films equal to or higher than that of Al or Al alloy, the concentration of nitric acid in the etching solution is set to 3 vol% or more and 10 vol% or less.
The adjustment of the etching rate of the MoW film is controlled by the film forming conditions.

[0006] Wet etching of the source / drain wiring electrodes does not damage the underlying semiconductor layer. Therefore, transistor characteristics are improved.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. As shown in FIG. 1, a gate electrode is formed on a translucent substrate 1 with an Al alloy. At this time, a gate bus line is also formed at the same time.

A gate insulating film 3, an amorphous silicon film 4, and an n + amorphous silicon film 5 made of a SiNx film are successively formed by a PECVD method and then processed into a predetermined shape. Thereafter, MoW10 is used as a source / drain electrode.
After forming a laminated film 6 of 0 nm / Al200 nm / MoW50 nm, it is processed into a predetermined shape by wet etching.
The W concentration used was 10 at%. The etching solution is mixed with phosphoric acid, nitric acid, acetic acid and water, and etched at 35 ° C. SiNx is formed as the passivation film 7.
In this etching step, the source bus line is also processed at the same time. Thus, a thin film transistor array is formed. Further, after forming a contact window in the passivation film 7, an ITO transparent conductive film 8 is deposited and processed into a predetermined shape as a pixel electrode to complete an array. The above manufacturing steps are summarized in FIG.

FIG. 4 shows the variation in the mobility of the transistor characteristics between the twelve thin film transistor substrates of the present invention and the conventional variation in the mobility of the transistor characteristics between the twelve transistors for comparison. In the characteristics of the thin film transistor of the present invention, the variation in the mobility of each substrate is shown by setting the average value of the mobility of 12 substrates to 100. It can be seen that in the present invention, the variation in the mobility is very small and the value is good as compared with the prior art.

On the other hand, FIG. 5 shows the result of examining the difference in etching rate depending on the concentration of nitric acid in the etching solution.

Referring to FIG. 5, when the nitric acid concentration is lower than vol. 3%, the etching rate of both Al and MoW tends to decrease, and when the nitric acid concentration exceeds 10 vol.%, Only the etching rate of MoW tends to decrease. It becomes difficult to form a tapered shape. FIG. 6 shows the relationship between the W concentration and the etching rate, where the etching rate is particularly likely to vary greatly. The same figure also shows the etching rate of Al. Al at W concentration vol15%
And MoW etching rates are about the same, but W concentration is 35vo
At l%, the MoW etching rate sharply decreases, so that the etched cross-section becomes an inversely tapered shape, which may affect the characteristics. Table 1 shows MoW / A
1 shows the etched cross-sectional shape and etching time when the W and Al alloy concentrations of l and Al alloy / MoW were changed and when the nitric acid concentration in the etching solution was changed.

[0012]

[Table 1]

In the overall evaluation, a sample in which both the cross-sectional shape and the etching time were ○ was judged as ○.

According to Table 1, in the case of MoW / Al / MoW (sample Nos. 1 to 14), the W concentration is 3 to 10 at% and the nitric acid concentration is 3
At 1010 vol%, a product satisfying both the sectional shape and the etching time was obtained. When the Zr concentration of the Al alloy in MoW / Al alloy / MoW is 2 at% (Sample Nos. 15 to 2)
4) At a W concentration of 10 to 15 at%, a material satisfying both the sectional shape and the etching time was obtained. Further about Zr concentration
An experiment was performed at a W concentration of 15 at% for the case of 0.3 to 11 at%,
The results are shown in Sample Nos. 25 to 32. Good results were obtained at a Zr concentration of 3.5 at%.

Although an Al-Zr alloy is shown as an example of the Al alloy, Ti, Ta, Hf, Nd, Si, Cu, Ni, Fe, Gd, Id
n, Su can be used. These elements form an Al alloy having high heat resistance and low heat diffusion.

The present inventors have also proposed that the upper layer MoW
The case where the MoW is different from that of the lower layer was also examined, but many good results were obtained when the upper and lower layers were the same. If the upper and lower layers have the same W concentration, the target and equipment are simplified, which leads to cost reduction.

[Brief description of the drawings]

FIG. 1 illustrates an example of a thin film transistor of the present invention.

FIG. 2 illustrates an example of a conventional thin film transistor.

FIG. 3 is a diagram showing an example of a process flow of the thin film transistor of the present invention.

FIG. 4 is a diagram showing a variation in mobility between thin film transistors of the present invention and a conventional thin film transistor.

FIG. 5 is a diagram showing the relationship between the nitric acid concentration in the etching solution of the present invention and the etching rate.

FIG. 6 is a diagram showing the relationship between the W concentration and the MoW etching rate according to the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 translucent substrate 2 gate electrode 3 gate insulating film (SiNx) 4 amorphous silicon film 5 n + silicon film 6 source / drain electrode (MoW / Al or Al alloy / MoW) 7 passivation film 8 pixel electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 H05B 33/14 A 5F043 21/306 33/26 Z 5F110 21/3205 H01L 29/78 616U 21 / 3213 21/306 F 21/336 21/88 N H05B 33/14 R 33/26 C 29/78 612C 616V 616K F term (reference) 2H092 HA06 JA24 JA34 JA37 JA44 KA18 MA20 NA25 NA27 NA29 3K007 AB18 EB00 FA01 4M104 AA09 AA10 BB02 BB16 BB18 BB36 CC01 DD17 DD64 EE05 EE17 FF03 FF09 FF18 GG04 GG20 HH11 5C094 AA42 AA44 BA03 BA29 BA43 CA19 DA14 DA15 EA04 EA07 QEB KK02 HF08 JJ04 FF02 GG04 VV00 VV15 WW04 XX00 5F043 AA27 BB15 BB16 GG03 5F110 AA16 AA26 AA28 BB01 BB05 CC07 EE06 FF03 FF30 GG02 GG15 GG45 HK03 HK06 HK22 HK16 HK22 HK35 HL07 HM03 NN02 NN24 NN72 QQ05 QQ09

Claims (10)

[Claims] 1. A gate wiring electrode is formed on a light-transmitting substrate, and a gate insulating film, a semiconductor film, and an impurity semiconductor film are stacked thereon, and a MoW layer and Al or Al are formed thereon.
A thin film transistor, wherein a three-layer film of an alloy layer and a MoW layer is formed as a source / drain wiring electrode. 2. The MoW layer having a W concentration of 3 at% or more and 40% or more.
2. The thin film transistor according to claim 1, wherein the content is at% or less. 3. The method according to claim 1, wherein the Al alloy comprises one or more additional elements and A
and the concentration of the additive element from 0.5 at%
2. The thin film transistor according to claim 1, wherein the content is in a range of 10 at%. 4. The W concentration of the MoW layer is 3 at% or more and 15% or more.
at%, and the three-layer film is composed of a MoW layer, an Al layer, and a Mo layer.
2. The thin film transistor according to claim 1, comprising a W layer. 5. The MoW layer has a W concentration of at least 10 at%.
2. The thin film transistor according to claim 1, wherein the thickness is 0 at% or less, and the three-layer film includes a MoW layer, an Al alloy layer, and a MoW layer. 6. An MoW layer and an Al or Al alloy layer and Mo
A method for manufacturing a thin film transistor, wherein a wet etching method is used to process a three-layer film of a W layer into a source / drain wiring electrode. 7. An etching solution used in the wet etching method is a mixed solution of phosphoric acid, nitric acid, acetic acid and water, and the wet etching method processes the three-layered film collectively. A method for manufacturing the thin film transistor according to the above. 8. The etching solution according to claim 1, wherein the mixing ratio of nitric acid is 3
The amount is not less than vol% and not more than 10 vol%.
8. The method for manufacturing a thin film transistor according to 7. 9. A thin film transistor array comprising the thin film transistor according to claim 1 and pixel electrodes arranged in a matrix. 10. A method for manufacturing a thin film transistor array, comprising: the thin film transistor according to claim 1; forming a pixel electrode for driving liquid crystal; and forming a gate bus line and a source bus line.