JP2002110678A - Ag ALLOY, Ag ALLOY THIN FILM AND, THIN-FILM TRANSISTOR USING THE SAME, AND THIN-FILM TRANSISTOR ARRAY AND MANUFACTURING METHOD OF THEM - Google Patents

Ag ALLOY, Ag ALLOY THIN FILM AND, THIN-FILM TRANSISTOR USING THE SAME, AND THIN-FILM TRANSISTOR ARRAY AND MANUFACTURING METHOD OF THEM

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Publication number
JP2002110678A
JP2002110678A JP2000300067A JP2000300067A JP2002110678A JP 2002110678 A JP2002110678 A JP 2002110678A JP 2000300067 A JP2000300067 A JP 2000300067A JP 2000300067 A JP2000300067 A JP 2000300067A JP 2002110678 A JP2002110678 A JP 2002110678A
Authority
JP
Japan
Prior art keywords
film
thin film
substrate
based alloy
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000300067A
Other languages
Japanese (ja)
Inventor
Mayumi Inoue
真弓 井上
Masaharu Terauchi
正治 寺内
Mikihiko Nishitani
幹彦 西谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000300067A priority Critical patent/JP2002110678A/en
Publication of JP2002110678A publication Critical patent/JP2002110678A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve the problems of the adhesive properties of a substrate board, surface oxidation of a film due to a later step, when an Ag alloy film is used as a gate metal film of an amorphous silicon thin film transistor. SOLUTION: The adhesive properties of the film are improved by subjecting it to reverse sputtering of the surface of the substrate before the film formed by using a nitrogen gas, when a gate metal Ag alloy film is formed. After the pattern of the gate metal Ag alloy film has been formed, the surface of the film is reversely sputtered or plasma treated to prevent a deterioration of characteristics, due to the oxidation of the Ag alloy film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、アクティブマトリ
クス方式の液晶ディスプレイ(LCD)やメモリ集積回
路に利用される薄膜トランジスタ(Thin Film Transist
or:以下、TFTと略記する。)や有機ELなどに用い
られる配線電極およびその製造方法に属する。
The present invention relates to an active matrix type liquid crystal display (LCD) and a thin film transistor (Thin Film Transistor) used for a memory integrated circuit.
or: Hereinafter, abbreviated as TFT. ), A wiring electrode used for an organic EL, and the like and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来薄膜トランジスタの構成は図2に示
すように、透光性基板1上に、所定形状のゲート金属膜
2、その上にゲート絶縁膜SiNx膜3、アモルファス
シリコン膜4、その上にソースおよびドレイン電極とコ
ンタクトをとるためのn+Si膜5が連続製膜されており、
その上に所定形状のソース・ドレイン金属膜6を形成す
る。その上にパッシベーション膜7としてSiNx膜が
形成され、その上にドレイン金属とコンタクト穴を介し
て接触している透明導電膜8のITO膜が形成されてい
るという構成からなっている。ゲート金属膜として、A
g系合金膜が近年注目されつつある。Ag系合金膜はシ
リコンやITO膜と接触しても熱拡散や電解液中での電
池現象を起こさないという点でゲート金属膜の単層化が
可能であり、工程が簡略化できると期待されている。
2. Description of the Related Art As shown in FIG. 2, a conventional thin film transistor has a gate metal film 2 of a predetermined shape on a light-transmitting substrate 1, a gate insulating film SiNx film 3, an amorphous silicon film 4, and a gate metal film 2. An n + Si film 5 for making contact with the source and drain electrodes is continuously formed.
A source / drain metal film 6 having a predetermined shape is formed thereon. A SiNx film is formed thereon as a passivation film 7, and an ITO film of a transparent conductive film 8 that is in contact with the drain metal via a contact hole is formed thereon. A as the gate metal film
In recent years, g-based alloy films have been receiving attention. The Ag-based alloy film can be made into a single-layered gate metal film in that it does not cause thermal diffusion or battery phenomena in the electrolyte even when it comes into contact with silicon or ITO film, and it is expected that the process can be simplified. ing.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、ゲート
金属膜2としてAg系合金膜を用いた場合、ガラスなど
透光性基板との密着性が悪く、配線パターン形成中にA
g合金膜が剥離するという問題があった。一方、Ag合
金膜は酸素プラズマで酸化されやすく、パターン形成後
にアッシング工程などがある場合、配線が黒化して抵抗
が大きくなるという問題もあった。
However, when an Ag-based alloy film is used as the gate metal film 2, the adhesion to a light-transmitting substrate such as glass is poor, and the A
There was a problem that the g alloy film was peeled off. On the other hand, the Ag alloy film is easily oxidized by oxygen plasma, and when an ashing step or the like is performed after pattern formation, there is a problem that the wiring is blackened and the resistance is increased.

【0004】本発明はこれら従来技術の問題点を解決
し、プロセス中に剥離したり酸化されたりすることがな
く、安定性の高い、即ち高歩留まりの大面積ディスプレ
イの作成可能な薄膜トランジスタのゲート配線構造を提
供することを目的とする。なお、これら配線電極は薄膜
トランジスタにかぎられたものでなく、有機ELなどの
電極としても用いられるものである。
The present invention solves these problems of the prior art, and does not peel or oxidize during the process and has a high stability, that is, a gate wiring of a thin film transistor capable of producing a large-area display with a high yield. The purpose is to provide a structure. Note that these wiring electrodes are not limited to thin film transistors, but are also used as electrodes for organic EL or the like.

【0005】[0005]

【課題を解決するための手段】本発明の薄膜トランジス
タは、Ag系合金膜と下地基板との密着性をよくするた
めに、Ag系合金膜との界面部分における下地基板の窒
素含有量を、Ag系合金膜内部の窒素含有量よりも多く
する。このとき、界面の窒素含有量を膜内部のそれより
2桁以上多く含むことが望ましい。また、その形成方法
において、あらかじめ下地基板表面を窒素プラズマや窒
素ガスによる逆スパッタによって窒化処理する。一方、
Ag系合金膜の酸化を防止するために、Ag系合金膜の
ゲート絶縁膜との界面部分に窒素が多く含まれるように
する。またその形成方法において、Ag系合金膜の形成
後に膜表面を窒素プラズマや窒素ガスによる逆スパッタ
を行う。
According to the thin film transistor of the present invention, in order to improve the adhesion between the Ag-based alloy film and the underlying substrate, the nitrogen content of the underlying substrate at the interface between the Ag-based alloy film and the Ag-based alloy film is reduced. More than the nitrogen content inside the base alloy film. At this time, it is desirable that the nitrogen content at the interface be two orders of magnitude greater than that inside the film. In the formation method, the surface of the base substrate is previously subjected to nitriding by reverse sputtering using nitrogen plasma or nitrogen gas. on the other hand,
In order to prevent oxidation of the Ag-based alloy film, a large amount of nitrogen is contained in the interface between the Ag-based alloy film and the gate insulating film. In the formation method, after the formation of the Ag-based alloy film, the film surface is subjected to reverse sputtering using nitrogen plasma or nitrogen gas.

【0006】以下、本発明の作用について説明する。The operation of the present invention will be described below.

【0007】Ag系合金膜との界面部分における下地基
板の窒素含量を増加させることにより、Ag系合金膜の
密着性を改善し、またAg系合金膜のゲート絶縁膜との
界面部分に窒素が多く含まれるようにすることにより、
プロセス中にAg系合金膜が酸化されるのを防止でき
る。
[0007] By increasing the nitrogen content of the underlying substrate at the interface with the Ag-based alloy film, the adhesion of the Ag-based alloy film is improved, and nitrogen is present at the interface of the Ag-based alloy film with the gate insulating film. By including a lot,
The oxidation of the Ag-based alloy film during the process can be prevented.

【0008】[0008]

【発明の実施の形態】以下、本発明の実施の形態を図面
を用いて説明する。図1には、本発明の薄膜トランジス
タの一例を示す。また、図3には、本発明の薄膜トラン
ジスタの製造プロセスの一例を示す。図1に示すよう
に、透光性基板1の表面を窒化するために、ゲート金属
膜を成膜する前に100〜300Wで30秒程度窒素ガ
スを用いて逆スパッタした後、Ag系合金薄膜2を所定
の膜厚に成膜する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a thin film transistor of the present invention. FIG. 3 shows an example of a manufacturing process of the thin film transistor of the present invention. As shown in FIG. 1, in order to nitride the surface of the translucent substrate 1, before forming a gate metal film, reverse sputtering is performed using nitrogen gas at 100 to 300 W for about 30 seconds, and then an Ag-based alloy thin film is formed. 2 is formed to a predetermined thickness.

【0009】次に、SiNx膜からなるゲート絶縁膜3
を330nmとアモルファスシリコン膜4を200n
m、n+アモルファスシリコン膜5を50nm連続してP
ECVD法で形成したのち、所定の形状に加工する。そ
の後、ソース・ドレイン電極としてTi/Al/Ti膜
6などを製膜したのち所定形状に加工する。パッシベ―
ション膜7としてSiNxを300nm形成する。この
ようにして薄膜トランジスタを形成する。
Next, a gate insulating film 3 made of a SiNx film
330 nm and amorphous silicon film 4 200 n
m, n + amorphous silicon film 5
After being formed by the ECVD method, it is processed into a predetermined shape. Thereafter, a Ti / Al / Ti film 6 or the like is formed as a source / drain electrode and then processed into a predetermined shape. Passive
A 300 nm thick SiNx is formed as the option film 7. Thus, a thin film transistor is formed.

【0010】なお、薄膜トランジスタアレイを作成する
ために、パッシベ―ション膜7にコンタクトウインドウ
を形成した後、ITO透明導電膜8を750nm形成す
る。画素電極として所定の形状に加工してアレイを完成
する。
In order to form a thin film transistor array, after a contact window is formed in the passivation film 7, an ITO transparent conductive film 8 is formed to a thickness of 750 nm. The array is completed by processing the pixel electrode into a predetermined shape.

【0011】本発明の薄膜トランジスタ基板12枚間の
ゲート電極配線の抵抗のばらつきと、比較のために、従
来のトランジスタ12枚間のゲート電極配線の抵抗のば
らつきを図4に示す。なお、本発明の薄膜トランジスタ
のゲート電極配線12枚の抵抗の平均値を100として
各基板の抵抗のばらつきを示した。本発明では従来と比
較して抵抗のばらつきが非常に少なく、また再現性も良
好であることがわかる。
FIG. 4 shows the variation of the resistance of the gate electrode wiring between the twelve thin film transistor substrates of the present invention and the conventional variation of the resistance of the gate electrode wiring between the twelve transistors, for comparison. Note that the average value of the resistances of the twelve gate electrode wires of the thin film transistor of the present invention is set to 100, and the variation in the resistance of each substrate is shown. It can be seen that in the present invention, the variation in resistance is very small and the reproducibility is good as compared with the conventional case.

【0012】一方、Ag系合金膜の成膜前の窒素ガスに
よる逆スパッタやプラズマ処理によって、界面の窒素濃
度の異なる薄膜を作成し、テープ試験による密着性評価
を行なった。またパターン形成した後、成膜前処理と同
様に窒素ガスによる逆スパッタやプラズマ処理を行った
あと、抵抗値を測定し抵抗評価を行った。結果を(表
1)に示す。
On the other hand, thin films having different nitrogen concentrations at the interface were prepared by reverse sputtering or plasma treatment with nitrogen gas before the formation of the Ag-based alloy film, and the adhesion was evaluated by a tape test. After pattern formation, reverse sputtering or plasma treatment with nitrogen gas was performed in the same manner as in the pretreatment before film formation, and then the resistance was measured to evaluate the resistance. The results are shown in (Table 1).

【0013】[0013]

【表1】 [Table 1]

【0014】(表1)より、下地基板との界面を窒素ガ
スで逆スパッタした後やプラズマ窒化処理した後にAg
系合金薄膜を成膜し、下地基板の界面の窒素濃度を合金
膜中より高くした試料No.4、5、9、10、14〜1
7では、また、Ag合金膜の下地界面の窒素濃度を合金
膜中より高くした試料No.2、3、7、8、12、13
では、密着性のよいAg系合金膜を形成することができ
た。また、Ag系合金膜をパターン形成した後ゲート絶
縁膜を製膜する前に、窒素ガス逆スパッタやプラズマ窒
化処理し、合金膜表面の窒素濃度を膜中より高くしたN
o.6〜17では、プロセス中のダメージ(合金膜の酸化)
などを防止することができ、抵抗値が比較的低いものが
得られた。
From Table 1, it can be seen that Ag was reversely sputtered at the interface with the underlying substrate with nitrogen gas or after plasma nitriding.
Nos. 4, 5, 9, 10, 14 to 1 in which a base alloy thin film was formed and the nitrogen concentration at the interface of the underlying substrate was higher than that in the alloy film
In Sample No. 7, samples Nos. 2, 3, 7, 8, 12, and 13 in which the nitrogen concentration at the base interface of the Ag alloy film was higher than in the alloy film.
Thus, an Ag-based alloy film having good adhesion could be formed. Also, after forming the Ag-based alloy film pattern and before forming the gate insulating film, nitrogen gas reverse sputtering or plasma nitridation was performed so that the nitrogen concentration on the alloy film surface was higher than that in the film.
o. In 6 to 17, damage during process (oxidation of alloy film)
Can be prevented, and a resistor having a relatively low resistance value is obtained.

【0015】発明者等は、これら以外にも、Ag合金膜の
組成(Ag、Pd、Cu、N)を種々変えた試料で同様の検討を
行ったが、PdとCuが各々0.05at%以上5at%以下で窒
素が0.1〜1at%の範囲内であれば、下地基板の界面の窒
素濃度を合金膜中より高くすることで、基板との密着性
のよいAg系合金膜を形成することができ、またAg系
合金膜表面の窒素濃度を膜中より高くしたものではプロ
セスダメージが少なく、プロセス中の抵抗値変化がない
ものが得られ、結果として良好な特性の薄膜トランジス
タが得られた。また、ソース・ドレイン電極としても下
地界面や表面の窒化処理は同様に有効であった。
The present inventors have also conducted similar studies on samples in which the composition (Ag, Pd, Cu, N) of the Ag alloy film is variously changed, but Pd and Cu are each at least 0.05 at%. If the nitrogen content is 5 at% or less and the nitrogen content is in the range of 0.1 to 1 at%, it is possible to form an Ag-based alloy film having good adhesion to the substrate by increasing the nitrogen concentration at the interface of the underlying substrate to be higher than in the alloy film. In addition, when the nitrogen concentration on the surface of the Ag-based alloy film was higher than that in the film, a thin film transistor having less process damage and no change in resistance during the process was obtained, and as a result, a thin film transistor having good characteristics was obtained. Nitriding of the interface between the base and the surface was similarly effective for the source / drain electrodes.

【発明の効果】本発明のAg系合金は、Ag系合金を金
属膜や配線に用いた場合でも、プロセス中に剥離したり
酸化されたりすることがなく、安定性が高い。また、こ
のAg系合金膜を薄膜トランジスタのゲート金属膜とし
て用いれば、高歩留まりの大面積ディスプレイの作成可
能な薄膜トランジスタのゲート配線構造を提供すること
ができる。
The Ag-based alloy of the present invention has high stability without being peeled or oxidized during the process even when the Ag-based alloy is used for a metal film or wiring. Further, when this Ag-based alloy film is used as a gate metal film of a thin film transistor, it is possible to provide a gate wiring structure of the thin film transistor capable of forming a large-area display with a high yield.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の薄膜トランジスタの一例を示す図FIG. 1 illustrates an example of a thin film transistor of the present invention.

【図2】従来の薄膜トランジスタの一例を示す図FIG. 2 illustrates an example of a conventional thin film transistor.

【図3】本発明の薄膜トランジスタのプロセスフローの
一例を示す図
FIG. 3 is a diagram showing an example of a process flow of the thin film transistor of the present invention.

【図4】本発明と従来発明の薄膜トランジスタのゲート
配線抵抗のばらつきを示す図
FIG. 4 is a diagram showing variations in gate wiring resistance of the thin film transistors of the present invention and the conventional invention.

【符号の説明】[Explanation of symbols]

1 透光性基板 2 ゲート金属膜 (AgPdCu) 3 ゲート絶縁膜(SiNx) 4 アモルファスシリコン膜 5 n+Si膜 6 ソース・ドレイン金属膜 7 パッシベーション膜SiNx 8 透明導電膜 REFERENCE SIGNS LIST 1 translucent substrate 2 gate metal film (AgPdCu) 3 gate insulating film (SiNx) 4 amorphous silicon film 5 n + Si film 6 source / drain metal film 7 passivation film SiNx 8 transparent conductive film

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) // C22C 5/06 G02F 1/136 500 5/08 H01L 29/78 617M (72)発明者 西谷 幹彦 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 2H092 JA26 JA29 JA38 JA42 JA44 JB13 JB23 JB32 JB33 JB38 JB57 KA05 KA07 KA12 KA16 KA18 KB14 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA35 MA37 MA43 NA15 NA27 NA28 PA07 4M104 BB08 BB39 CC05 DD22 DD89 GG20 HH09 5C094 AA32 AA42 BA03 BA43 CA19 CA24 DA14 DA15 EA05 FB12 FB14 FB15 5F033 HH14 LL02 VV15 XX13 XX20 5F110 AA26 AA30 BB01 BB05 CC07 DD25 EE06 FF03 GG02 GG15 GG24 GG45 HK03 HK04 HK09 HK16 HK22 HK35 NN04 NN24 NN72 QQ09 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) // C22C 5/06 G02F 1/136 500 5/08 H01L 29/78 617M (72) Inventor Mikihiko Nishitani Osaka 1006, Kazuma, Kamon, Fumonma-shi Matsushita Electric Industrial Co., Ltd.F-term (reference) NA28 PA07 4M104 BB08 BB39 CC05 DD22 DD89 GG20 HH09 5C094 AA32. NN72 QQ09

Claims (17)

【特許請求の範囲】[Claims] 【請求項1】Agを主成分とし、界面の窒素含有量が内
部より高いことを特徴とするAg系合金。
1. An Ag-based alloy comprising Ag as a main component and having a higher nitrogen content at the interface than at the inside.
【請求項2】Agを主成分とする基板上に形成されたA
g系合金薄膜であって、前記基板の前記Ag系合金薄膜
との界面に、窒素を前記基板の内部より2桁以上多く含
むことを特徴とするAg系合金薄膜。
2. A method according to claim 1, wherein said substrate is formed on a substrate containing Ag as a main component.
An Ag-based alloy thin film, characterized in that the interface between the substrate and the Ag-based alloy thin film contains two or more digits of nitrogen from the inside of the substrate.
【請求項3】Agを主成分とする基板上に形成されたA
g系合金薄膜であって、窒素を下地基板との界面に膜内
部より2桁以上多く含むことを特徴とするAg系合金薄
膜。
3. The method according to claim 1, wherein the substrate is formed on a substrate containing Ag as a main component.
An Ag-based alloy thin film, wherein the Ag-based alloy thin film contains nitrogen at an interface with an underlying substrate by two digits or more from the inside of the film.
【請求項4】Agを主成分とし、窒素を上層膜との界面
側に膜内部含有量より2桁以上多く含むことを特徴とす
るAg系合金薄膜。
4. An Ag-based alloy thin film containing Ag as a main component and containing nitrogen by two orders of magnitude or more at the interface side with the upper layer film than the internal content of the film.
【請求項5】下地基板との界面と、上層膜との界面に窒
素を基板内部より2桁以上多く含むAg系合金薄膜。
5. An Ag-based alloy thin film containing two or more digits of nitrogen at the interface with the underlying substrate and at the interface with the upper layer film more than inside the substrate.
【請求項6】下地基板のAg系合金との界面と、上層膜
との界面に窒素を膜内部より2桁以上多く含むAg系合
金薄膜。
6. An Ag-based alloy thin film containing two or more digits of nitrogen at the interface between the underlying substrate and the Ag-based alloy and between the interface with the upper layer film.
【請求項7】下地基板との界面と上層膜との界面に窒素
を基板内部より2桁以上多く含み且つ、濃度が傾斜的に
変化するAg系合金薄膜。
7. An Ag-based alloy thin film containing two or more digits of nitrogen at the interface between the underlayer substrate and the upper layer film from the inside of the substrate, and whose concentration changes in a gradient manner.
【請求項8】透光性基板上に、請求項1記載のAg系合
金薄膜が、ゲート金属膜として形成され、この上にSi
Nxゲート絶縁膜とa−Si半導体膜とn+Si膜および
ソース・ドレイン電極が積層されており、前記下地透光
性基板の、前記Ag系合金薄膜との界面部における窒素
含量が、前記Ag合金薄膜内部より2桁以上多いことを
特徴とする薄膜トランジスタ。
8. The Ag-based alloy thin film according to claim 1 is formed on a light-transmitting substrate as a gate metal film, and a Si metal thin film is formed thereon.
An Nx gate insulating film, an a-Si semiconductor film, an n + Si film, and a source / drain electrode are laminated, and the nitrogen content at the interface between the under translucent substrate and the Ag-based alloy thin film is the Ag content. A thin film transistor characterized by being two or more digits larger than the inside of the alloy thin film.
【請求項9】透光性基板上に、請求項1記載のAg系合
金薄膜が、ゲート金属膜として形成され、この上にSi
Nxゲート絶縁膜とa−Si半導体膜とn+Si膜および
ソース・ドレイン電極が積層されており、前記Ag系合
金薄膜の前記下地透光性基板との界面部における窒素含
量が、前記Ag合金薄膜内部より2桁以上多いことを特
徴とする薄膜トランジスタ。
9. The Ag-based alloy thin film according to claim 1 is formed on a light-transmitting substrate as a gate metal film, and a Si metal thin film is formed thereon.
An Nx gate insulating film, an a-Si semiconductor film, an n + Si film, and a source / drain electrode are laminated, and the nitrogen content at the interface between the Ag-based alloy thin film and the underlying translucent substrate is the same as that of the Ag alloy. A thin film transistor characterized by being two or more digits larger than the inside of the thin film.
【請求項10】透光性基板上に、請求項1記載のAg系
合金薄膜が、ゲート金属膜として形成され、この上にS
iNxゲート絶縁膜とa−Si半導体膜とn+Si膜およ
びソース・ドレイン電極が積層されており、前記Ag系
合金薄膜の前記SiNxゲート絶縁膜との界面部におけ
る窒素含量が、前記Ag合金薄膜内部よ2桁以上多いこ
とを特徴とする薄膜トランジスタ。
10. The Ag-based alloy thin film according to claim 1 is formed on a light-transmitting substrate as a gate metal film, and S
An iNx gate insulating film, an a-Si semiconductor film, an n + Si film, and a source / drain electrode are laminated, and the nitrogen content at the interface between the Ag-based alloy thin film and the SiNx gate insulating film is the Ag alloy thin film. A thin film transistor characterized by being two or more digits larger than the inside.
【請求項11】透光性基板上に、請求項1記載のAg系
合金薄膜が、ゲート金属膜として形成され、この上にS
iNxゲート絶縁膜とa−Si半導体膜とn+Si膜およ
びソース・ドレイン電極が積層されており、下地基板側
界面と上層膜との界面に窒素を基板内部より2桁以上多
く含むAg系合金薄膜を有することを特徴とする薄膜ト
ランジスタ。
11. An Ag-based alloy thin film according to claim 1 is formed as a gate metal film on a light-transmitting substrate.
Ag-based alloy in which an iNx gate insulating film, an a-Si semiconductor film, an n + Si film, and a source / drain electrode are laminated, and nitrogen is contained in the interface between the underlying substrate side and the upper layer film at least two orders of magnitude more than inside the substrate. A thin film transistor having a thin film.
【請求項12】透光性基板上に請求項1記載のAg合金
ゲート金属膜が形成され、この上にSiNxゲート絶縁
膜とa−Si半導体膜とn+Si膜およびソース・ドレイ
ン電極が積層されており、前記下地透光性基板の前記A
g系合金薄膜との界面部における窒素含量と前記ゲート
絶縁膜との界面部における窒素含量が前記Ag合金薄膜
内部より2桁以上多いことを特徴とする薄膜トランジス
タ。
12. An Ag alloy gate metal film according to claim 1 is formed on a translucent substrate, and a SiNx gate insulating film, an a-Si semiconductor film, an n + Si film, and source / drain electrodes are laminated thereon. A of the base translucent substrate
A thin film transistor, wherein the nitrogen content at the interface with the g-based alloy thin film and the nitrogen content at the interface with the gate insulating film are at least two orders of magnitude greater than inside the Ag alloy thin film.
【請求項13】透光性基板上に、請求項1記載のAg系
合金薄膜が、ゲート金属膜として形成され、この上にS
iNxゲート絶縁膜とa−Si半導体膜とn+Si膜およ
びソース・ドレイン電極が積層されており、下地基板と
の界面と上層膜との界面に窒素を基板内部より2桁以上
多く含み且つ、濃度が傾斜的に変化するAg系合金薄膜
を有することを特徴とする薄膜トランジスタ。
13. The Ag-based alloy thin film according to claim 1 is formed as a gate metal film on a light-transmitting substrate, and S
An iNx gate insulating film, an a-Si semiconductor film, an n + Si film, and a source / drain electrode are stacked, and nitrogen is contained in the interface between the underlying substrate and the upper layer film at least two orders of magnitude greater than the inside of the substrate, and A thin film transistor having an Ag-based alloy thin film whose concentration changes in a gradient manner.
【請求項14】前記透光性基板表面あるいは前記Ag合
金ゲート金属膜表面を、窒素プラズマで窒化処理するこ
とにより、窒素含有量を調整することを特徴とする請求
項8〜13のいずれかに記載の薄膜トランジスタの製造
方法。
14. The nitrogen content is adjusted by nitriding the surface of the transparent substrate or the surface of the Ag alloy gate metal film with nitrogen plasma. A method for manufacturing the thin film transistor according to the above.
【請求項15】前記透光性基板表面あるいは前記Ag合
金ゲート金属膜表面を、窒素ガスで逆スパッタすること
ことにより、窒素含有量を調整することを特徴とする請
求項8〜13のいずれかに記載の薄膜トランジスタの製
造方法。
15. The nitrogen content is adjusted by reverse-sputtering the surface of the translucent substrate or the surface of the Ag alloy gate metal film with a nitrogen gas. 3. The method for manufacturing a thin film transistor according to item 1.
【請求項16】請求項8〜13のいずれかに記載の薄膜
トランジスタと、画素電極とをマトリックス状に配して
なることを特徴とする薄膜トランジスタアレイ。
16. A thin-film transistor array comprising the thin-film transistor according to claim 8 and pixel electrodes arranged in a matrix.
【請求項17】請求項8〜13のいずれかに記載の薄膜
トランジスタと、液晶駆動用の画素電極とを形成する工
程と、ゲートバライン及びソースバスラインを形成する
工程と、を含む薄膜トランジスタアレイの製造方法。
17. A thin-film transistor array comprising: the thin-film transistor according to claim 8; a pixel electrode for driving liquid crystal; and a step of forming a gate line and a source bus line. Production method.
JP2000300067A 2000-09-29 2000-09-29 Ag ALLOY, Ag ALLOY THIN FILM AND, THIN-FILM TRANSISTOR USING THE SAME, AND THIN-FILM TRANSISTOR ARRAY AND MANUFACTURING METHOD OF THEM Pending JP2002110678A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100750922B1 (en) * 2001-04-13 2007-08-22 삼성전자주식회사 A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same
CN102484149A (en) * 2009-09-04 2012-05-30 三菱电机株式会社 Solar battery and method of manufacturing the same
CN104766803A (en) * 2015-04-01 2015-07-08 京东方科技集团股份有限公司 TFT manufacturing method and TFTs, array base panel and display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100750922B1 (en) * 2001-04-13 2007-08-22 삼성전자주식회사 A wiring and a method for manufacturing the wiring, and a thin film transistor array panel including the wiring and method for manufacturing the same
CN102484149A (en) * 2009-09-04 2012-05-30 三菱电机株式会社 Solar battery and method of manufacturing the same
US8841541B2 (en) 2009-09-04 2014-09-23 Mitsubishi Electric Corporation Solar battery and method of manufacturing the same
CN104766803A (en) * 2015-04-01 2015-07-08 京东方科技集团股份有限公司 TFT manufacturing method and TFTs, array base panel and display device
US9905580B2 (en) 2015-04-01 2018-02-27 Boe Technology Group Co., Ltd. Method for manufacturing thin film transistor, thin film transistor, and array substrate and display device using the same
CN104766803B (en) * 2015-04-01 2018-09-11 京东方科技集团股份有限公司 Production method and TFT, array substrate, the display device of TFT

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