KR100480368B1 - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- KR100480368B1 KR100480368B1 KR10-1998-0056451A KR19980056451A KR100480368B1 KR 100480368 B1 KR100480368 B1 KR 100480368B1 KR 19980056451 A KR19980056451 A KR 19980056451A KR 100480368 B1 KR100480368 B1 KR 100480368B1
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- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052802 copper Inorganic materials 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 17
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 12
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910017604 nitric acid Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910003087 TiOx Inorganic materials 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 238000007772 electroless plating Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000007747 plating Methods 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000002184 metal Substances 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- -1 (NH 4) 2 S 2 O 8 Chemical class 0.000 description 3
- 241001239379 Calophysus macropterus Species 0.000 description 3
- 229910001182 Mo alloy Inorganic materials 0.000 description 3
- 229910016024 MoTa Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서 절연기판 상에 게이트전극을 형성하는 단계; 상기 게이트전극 표면에 상기 게이트전극을 구성하는 금속원소의 확산을 방지하는 확산방지층을 형성하는 단계; 상기 확산방지층 상에 게이트절연막, 활성층 및 오믹콘택층을 순차적으로 형성하고 상기 활성층 및 오믹콘택층을 상기 게이트절연막이 노출되도록 패터닝하여 상기 게이트전극과 대응하는 부분을 제외한 나머지 부분을 제거하는 단계 및 상기 오믹콘택층과 접촉되어 전기적으로 연결되는 소오스전극 및 드레인전극을 형성하는 단계를 포함한다. 상기 확산방지층이 게이트전극을 이루는 구리가 활성층으로 확산되지 않도록 하여 채널의 저항이 변하지 않도록 하므로 소자 특성 및 재현성의 저하를 방지할 수 있다.The present invention relates to a method of manufacturing a thin film transistor, comprising the steps of: forming a gate electrode on an insulating substrate; Forming a diffusion barrier layer on the gate electrode surface to prevent diffusion of metal elements constituting the gate electrode; Sequentially forming a gate insulating layer, an active layer, and an ohmic contact layer on the diffusion barrier layer, and patterning the active layer and the ohmic contact layer to expose the gate insulating layer to remove the remaining portions except the portions corresponding to the gate electrodes; and And forming a source electrode and a drain electrode in contact with the ohmic contact layer to be electrically connected to the ohmic contact layer. The diffusion preventing layer prevents copper from forming the gate electrode from diffusing into the active layer so that the resistance of the channel does not change, thereby preventing deterioration of device characteristics and reproducibility.
Description
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서, 특히 게이트전극을 저저항 금속으로 형성하는 박막트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor in which a gate electrode is formed of a low resistance metal.
액정표시장치는 박막트랜지스터(Thin Film Transistor; TFT)로 이루어진 구동소자인 스위칭소자와 빛을 투과하거나 반사하는 화소(pixel)전극을 기본단위로 하는 화소가 매트릭스 구조로 배열된 구조를 가진다. 박막트랜지스터는 액정표시장치가 대면적화 될수록 게이트 신호의 지연을 방지하기 위해 게이트전극을 구리(Cu) 등의 저저항 금속으로 형성한다.The liquid crystal display device has a structure in which a switching element, which is a driving element formed of a thin film transistor (TFT), and pixels, which are based on pixel electrodes that transmit or reflect light, are arranged in a matrix structure. In the TFT, the gate electrode is formed of a low resistance metal such as copper (Cu) to prevent delay of the gate signal as the liquid crystal display becomes larger.
도 1a 내지 도1c는 종래기술에 따른 박막트랜지스터의 제조공정도이다.1A to 1C are manufacturing process diagrams of a thin film transistor according to the prior art.
도 1a를 참조하면, 투명한 절연기판(11) 상에 스퍼터링(sputtering) 등의 방법으로 구리(Cu)를 증착하여 금속박막을 형성한다. 그리고, 구리 박막을 습식 방법을 포함하는 포토리소그래피(photolithography) 방법으로 절연기판(11)의 소정 부분에만 잔류하도록 패터닝하여 게이트전극(13)을 형성한다.Referring to FIG. 1A, copper (Cu) is deposited on a transparent insulating substrate 11 by sputtering or the like to form a metal thin film. The copper thin film is patterned to remain only in a predetermined portion of the insulating substrate 11 by a photolithography method including a wet method to form the gate electrode 13.
도 1b를 참조하면, 절연기판(11) 상에 게이트전극(13)을 덮도록 게이트절연막(15), 활성층(17) 및 오믹콘택층(ohmic contact layer)(19)을 화학기상증착(Chemical Vapor Deposition; CVD) 방법으로 순차적으로 형성한다.Referring to FIG. 1B, the gate insulating layer 15, the active layer 17, and the ohmic contact layer 19 are chemical vapor deposited to cover the gate electrode 13 on the insulating substrate 11. It is formed sequentially by the deposition (CVD) method.
상기에서 게이트절연막(15)은 산화실리콘 또는 질화실리콘 등의 절연물질을 증착하여 형성하고, 활성층(17)은 불순물이 도핑되지 않은 비정질실리콘 또는 다결정실리콘으로 형성된다. 또한, 오믹콘택층(19)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘으로 형성된다.The gate insulating film 15 is formed by depositing an insulating material such as silicon oxide or silicon nitride, and the active layer 17 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 19 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration.
오믹콘택층(19) 및 활성층(17)의 소정 부분을 이방성 식각을 포함하는 포토리소그래피 방법으로 게이트절연막(15)이 노출되도록 패터닝한다. 이 때, 활성층(17) 및 오믹콘택층(19)은 게이트전극(13)과 대응하는 부분에만 잔류되도록 한다.Predetermined portions of the ohmic contact layer 19 and the active layer 17 are patterned to expose the gate insulating film 15 by a photolithography method including anisotropic etching. At this time, the active layer 17 and the ohmic contact layer 19 are allowed to remain only in the portion corresponding to the gate electrode 13.
도 1c를 참조하면, 게이트절연막(13) 상에 오믹콘택층(19)을 덮도록 몰리브덴(Mo) 또는 MoW, MoTa 및 MoNb 등의 몰리브덴 합금(Mo alloy)을 화학기상증착 방법이나 스퍼터링 방법으로 증착하여 금속 박막을 형성한다. 상기에서 오믹콘택층(19)과 금속 박막은 오믹 접촉을 형성한다.Referring to FIG. 1C, molybdenum (Mo) or molybdenum alloys such as MoW, MoTa, and MoNb are deposited on the gate insulating layer 13 by chemical vapor deposition or sputtering to cover the ohmic contact layer 19. To form a metal thin film. In the above, the ohmic contact layer 19 and the metal thin film form ohmic contact.
그리고, 금속 박막을 포토리소그래피 방법으로 게이트절연막(13)이 노출되도록 패터닝하여 소오스전극(21) 및 드레인전극(23)을 형성한다. 이때, 상기 소오스전극(21) 및 드레인전극(23) 사이의 게이트전극(13)과 대응하는 부분은 상기 오믹콘택층(19)도 제거하여 활성층(17)이 노출되도록 한다. 상기에서 오믹콘택층(19)의 게이트전극(13)과 대응하는 소오스전극(21) 및 드레인전극(23) 사이는 채널이 된다.The metal thin film is patterned to expose the gate insulating layer 13 by a photolithography method to form the source electrode 21 and the drain electrode 23. In this case, the ohmic contact layer 19 is also removed from the source electrode 21 and the drain electrode 23 so as to expose the active layer 17. In the above, the gate electrode 13 of the ohmic contact layer 19 and the corresponding source electrode 21 and the drain electrode 23 become a channel.
그러나, 종래기술에 따른 박막트랜지스터의 제조방법은 게이트절연막, 활성층 및 오믹콘택층을 화학기상증착 방법으로 순차적으로 형성할 때 게이트전극을 이루는 구리가 확산되어 채널의 저항이 변하여 소자 특성이 저하될 뿐만 아니라 재현성이 저하되는 문제점이 있었다.However, in the method of manufacturing the thin film transistor according to the prior art, when the gate insulating layer, the active layer, and the ohmic contact layer are sequentially formed by chemical vapor deposition, copper forming the gate electrode is diffused, and the resistance of the channel is changed, thereby degrading device characteristics. But there was a problem that the reproducibility is lowered.
따라서, 본 발명의 목적은 게이트전극을 이루는 구리가 활성층 내부로 확산되는 것을 방지하여 소자 특성 및 재현성이 저하되는 것을 방지할 수 있는 박막트랜지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can prevent the copper constituting the gate electrode from being diffused into the active layer, thereby preventing deterioration of device characteristics and reproducibility.
상기 목적을 달성하기 위한 본 발명에 따른 박막트랜지스터의 제조방법은 절연기판 상에 게이트전극을 형성하는 단계, 상기 게이트전극 표면에 상기 게이트전극을 구성하는 금속원소의 확산을 방지하는 확산방지층을 형성하는 단계, 상기 확산방지층 상에 게이트절연막, 활성층 및 오믹콘택층을 순차적으로 형성하고 상기 활성층 및 오믹콘택층을 상기 게이트절연막이 노출되도록 패터닝하여 상기 게이트전극과 대응하는 부분을 제외한 나머지 부분을 제거하는 단계 및 상기 오믹콘택층과 접촉되어 전기적으로 연결되는 소오스전극 및 드레인전극을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor, the method comprising: forming a gate electrode on an insulating substrate, and forming a diffusion barrier layer on the surface of the gate electrode to prevent diffusion of metal elements constituting the gate electrode. Forming a gate insulating layer, an active layer, and an ohmic contact layer sequentially on the diffusion barrier layer, and patterning the active layer and the ohmic contact layer so that the gate insulating layer is exposed to remove the remaining portions except the portion corresponding to the gate electrode. And forming a source electrode and a drain electrode in contact with the ohmic contact layer to be electrically connected to the ohmic contact layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 도2c는 본 발명에 따른 박막트랜지스터의 제조공정도이다.2a to 2c is a manufacturing process diagram of a thin film transistor according to the present invention.
도 2a를 참조하면, 투명한 절연기판(31) 상에 구리(Cu)를 스퍼터링(sputtering) 등의 방법으로 증착하거나 무전해도금 방법으로 도포하여 금속박막을 형성한다. 상기에서 절연기판(31)으로 유리, 석영 또는 투명한 플라스틱 등이 사용된다.Referring to FIG. 2A, copper (Cu) is deposited on the transparent insulating substrate 31 by sputtering or by electroless plating to form a metal thin film. As the insulating substrate 31, glass, quartz or transparent plastic is used.
구리 박막을 습식 방법을 포함하는 포토리소그래피 방법으로 절연기판(11)의 소정 부분에만 잔류하도록 패터닝하여 게이트전극(33)을 형성한다. 이때, 식각 용액으로 여러 가지 묽은 산, 예를 들면 (NH4)2S2O8, 인산, 질산, 초산 또는 인산+초산+질산+물의 혼산을 사용하여 구리 박막을 패터닝한다.The copper thin film is patterned to remain only in a predetermined portion of the insulating substrate 11 by a photolithography method including a wet method to form the gate electrode 33. At this time, the copper thin film is patterned using various dilute acids such as (NH 4) 2 S 2 O 8, phosphoric acid, nitric acid, acetic acid, or a mixture of phosphoric acid + acetic acid + nitric acid + water as an etching solution.
상기에서 게이트전극(33)을 구리로 형성하였으나, 본 발명의 다른 실시예로 인듐-틴-옥사이드(Indium Tin Oxide; ITO)/구리의 적층 구조로 형성할 수도 있다. 이러한 구조에서 상기 인듐-틴-옥사이드는 절연기판(31)과 구리 사이의 접착력을 향상시킨다.Although the gate electrode 33 is formed of copper in the above, another embodiment of the present invention may be formed of a laminated structure of indium tin oxide (ITO) / copper. In this structure, the indium tin oxide improves adhesion between the insulating substrate 31 and copper.
절연기판(31) 상에 스퍼터링 방법으로 티타늄(titanium; Ti)을 50∼100Å 정도의 두께로 게이트전극(33)을 덮도록 증착한다. 그리고, 상기 티타늄을 산소(O2) 분위기에서 200∼300℃ 정도의 온도로 10분∼2시간 동안 열산화하여 TiOx의 확산방지층(35)을 형성한다.Titanium (Ti) is deposited on the insulating substrate 31 so as to cover the gate electrode 33 with a thickness of about 50 to about 100 Å. The titanium is thermally oxidized at an oxygen (O 2) atmosphere at a temperature of about 200 to 300 ° C. for 10 minutes to 2 hours to form a diffusion barrier layer 35 of TiOx.
도 2b를 참조하면, 상기 확산방지층(35) 상에 게이트절연막(37), 활성층(39) 및 오믹콘택층(41)을 화학기상증착 방법으로 순차적으로 형성한다.Referring to FIG. 2B, the gate insulating layer 37, the active layer 39, and the ohmic contact layer 41 are sequentially formed on the diffusion barrier layer 35 by chemical vapor deposition.
상기에서 게이트절연막(37)은 산화실리콘 또는 질화실리콘 등의 절연물질을 증착하여 형성하고, 활성층(39)은 불순물이 도핑되지 않은 비정질실리콘 또는 다결정실리콘으로 형성된다. 또한, 오믹콘택층(41)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘으로 형성된다. 상기에서 게이트절연막(37), 활성층(39) 및 오믹콘택층(41)을 형성할 때 확산방지층(35)은 게이트전극(33)의 구리 성분이 게이트절연막(37) 및 활성층(39)으로 확산되는 것을 방지한다.The gate insulating layer 37 is formed by depositing an insulating material such as silicon oxide or silicon nitride, and the active layer 39 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 41 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration. In forming the gate insulating layer 37, the active layer 39, and the ohmic contact layer 41, the diffusion barrier layer 35 diffuses the copper component of the gate electrode 33 into the gate insulating layer 37 and the active layer 39. Prevent it.
오믹콘택층(41) 및 활성층(39)의 소정 부분을 게이트절연막(37)이 노출되도록 이방성 식각을 포함하는 포토리소그래피 방법으로 패터닝한다. 이때, 상기 활성층(39) 및 오믹콘택층(41)은 게이트전극(33)과 대응하는 부분에만 잔류되도록 한다.Predetermined portions of the ohmic contact layer 41 and the active layer 39 are patterned by a photolithography method including anisotropic etching so that the gate insulating layer 37 is exposed. In this case, the active layer 39 and the ohmic contact layer 41 are allowed to remain only in portions corresponding to the gate electrode 33.
도 2c를 참조하면, 게이트절연막(35) 상에 오믹콘택층(41)을 덮도록 화학기상증착 방법 또는 스퍼터링 방법으로 몰리브덴 또는 MoW, MoTa 및 MoNb 등의 몰리브덴 합금을 화학기상증착 방법이나 스퍼터링 방법으로 증착하여 금속 박막을 형성한다. 상기에서 오믹콘택층(41)과 금속 박막은 오믹 접촉을 형성한다.Referring to FIG. 2C, molybdenum or molybdenum alloys such as MoW, MoTa, and MoNb may be chemically deposited or sputtered by chemical vapor deposition or sputtering to cover the ohmic contact layer 41 on the gate insulating layer 35. Deposition forms a thin metal film. In the above, the ohmic contact layer 41 and the metal thin film form ohmic contact.
그리고, 금속 박막을 이방성 식각을 포함하는 포토리소그래피 방법으로 게이트절연막(35)이 노출되도록 패터닝하여 소오스전극(43) 및 드레인전극(45)을 형성한다. 이때, 상기 소오스전극(43) 및 드레인전극(45) 사이의 게이트전극(33)과 대응하는 부분은 오믹콘택층(41)도 제거하여 활성층(39)이 노출되도록 한다. 상기에서 오믹콘택층(41)의 게이트전극(33)과 대응하는 소오스전극(43) 및 드레인전극(45) 사이는 채널이 된다.The metal thin film is patterned to expose the gate insulating layer 35 by a photolithography method including anisotropic etching to form the source electrode 43 and the drain electrode 45. In this case, the ohmic contact layer 41 is also removed from the source electrode 43 and the drain electrode 45 so as to expose the active layer 39. In the above, the gate electrode 33 of the ohmic contact layer 41 and the corresponding source electrode 43 and the drain electrode 45 become a channel.
상기에서 소오스전극(43) 및 드레인전극(45)을 몰리브덴 또는 MoW, MoTa 및 MoNb 등의 몰리브덴 합금의 단일 금속층으로 형성하였으나, 알루미늄(Al)을 하부층에 형성시킨 2층 이상의 다층 금속층으로 형성할 수도 있다.Although the source electrode 43 and the drain electrode 45 are formed of a single metal layer of molybdenum or a molybdenum alloy such as MoW, MoTa, and MoNb, the source electrode 43 and the drain electrode 45 may be formed of two or more multilayer metal layers in which aluminum (Al) is formed on the lower layer. have.
상술한 바와 같이 본 발명에 따른 박막트랜지스터의 제조방법은 절연기판 상에 구리를 포함하는 게이트전극을 형성한 후 절연기판 상에 게이트전극을 덮도록 티타늄을 얇게 증착하고 산화하여 TiOx의 확산방지층을 형성한다. 그리고, 상기 확산지방지층 상에 게이트절연막, 활성층 및 오믹콘택층을 화학기상증착 방법으로 형성한다.As described above, in the method of manufacturing a thin film transistor according to the present invention, after forming a gate electrode including copper on an insulating substrate, a thin layer of titanium is deposited and oxidized to cover the gate electrode on the insulating substrate to form a diffusion barrier layer of TiOx. do. A gate insulating layer, an active layer, and an ohmic contact layer are formed on the diffusion barrier layer by chemical vapor deposition.
따라서, 본 발명은 확산방지층이 게이트전극을 이루는 구리가 활성층으로 확산되지 않도록 하여 채널의 저항이 변하지 않도록 하므로 소자 특성 및 재현성의 저하를 방지할 수 있는 이점이 있다.Therefore, the present invention has the advantage that the diffusion preventing layer does not diffuse the copper forming the gate electrode to the active layer so that the resistance of the channel does not change, thereby preventing deterioration of device characteristics and reproducibility.
도 1a 내지 도 1c는 종래기술에 따른 박막트랜지스터의 제조공정도.1a to 1c is a manufacturing process diagram of a thin film transistor according to the prior art.
도 2a 내지 도 2c는 본 발명에 따른 박막트랜지스터의 제조공정.2a to 2c is a manufacturing process of a thin film transistor according to the present invention.
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| KR100683752B1 (en) * | 2005-01-19 | 2007-02-20 | 삼성에스디아이 주식회사 | A thin film transistor and a method for prepairng the same |
| KR101165843B1 (en) * | 2005-06-30 | 2012-07-13 | 엘지디스플레이 주식회사 | Etchant, forming method of metal line using the same and fabrication method of LCD using the same |
| KR101244895B1 (en) * | 2006-04-06 | 2013-03-18 | 삼성디스플레이 주식회사 | Method for fabricating thin film transistor plate |
| KR100744396B1 (en) * | 2006-04-10 | 2007-07-30 | 비오이 하이디스 테크놀로지 주식회사 | Method of manufacturing array substrate for liquid crystal display |
| KR101236427B1 (en) * | 2006-05-10 | 2013-02-22 | 삼성디스플레이 주식회사 | Method of manufacturing gate insulator and thin film transistor adopting the insulator |
| KR101397444B1 (en) * | 2007-12-06 | 2014-05-20 | 엘지디스플레이 주식회사 | Method of forming a copper line and method of fabricating thin film transistor using thereof |
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