KR101165843B1 - Etchant, forming method of metal line using the same and fabrication method of LCD using the same - Google Patents

Abstract

The etchant according to the present invention is for collectively etching Cu / ITO bilayers, and is characterized in that it includes HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor.

In addition, the metal wiring forming method according to the invention, forming an ITO layer on the substrate; Laminating a Cu layer over the ITO layer; Forming a photoresist film on the Cu / ITO layer; Exposing the photoresist to perform patterning; Etching the Cu / ITO layer on the patterned photoresist using an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor; Its features are to include.

In addition, the liquid crystal display device manufacturing method according to the present invention, forming an ITO layer on the substrate; Stacking a Cu layer on the ITO layer to form a Cu / ITO layer to be used as a gate wiring and a gate electrode; Forming a photoresist film on the Cu / ITO layer; Exposing the photoresist to perform patterning; Etching the Cu / ITO layer on the patterned photoresist using an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor; Its features are to include.

Description

Etching liquid, metal wire forming method and liquid crystal display manufacturing method {Etchant, forming method of metal line using the same and fabrication method of LCD using the same}

1 to 3 is a view showing a state in which the etching performed on the Cu / ITO bilayer using the etching solution according to the present invention.

4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

5 is a cross-sectional view taken along the line VI-VI ′ and VII-VII ′ of FIG. 4.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

8A through 8C are cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

9A and 9B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

10A to 10E are cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

11 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

12 is a cross-sectional view taken along the line XI-XI 'and XII-XII' of FIG. 11;

13A to 13C are plan and cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

14A to 14C are cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

15A to 15E are cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

102, 202 ... gate line 104, 204 ... data line

106, 206 ... gate electrode 108, 208 ... source electrode

110, 210 Drain electrodes 114, 214 Active layer

116, 216 ... Ohmic contact layer 118, 218 ... Protective film

122, 222 ... pixel electrode 128, 228 ... storage electrode

130, 230 ... Thin Film Transistors 140, 240 ... Storage Capacitors

150, 250 ... gate pad 160, 260 ... data pad

180, 280 ... Common pad 184, 284 ... Common electrode

186, 286 ... common line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an etching solution capable of collectively etching a metal double layer and ensuring straightness of wiring, and to a method of manufacturing a liquid crystal display device which can reduce the number of mask processes by using the same. .

Today's liquid crystal display devices are spotlighted as next-generation advanced display devices with low power consumption, good portability, technology-intensive and high added value. The liquid crystal display device forms a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate, and displays an image by using a difference in refractive index of light according to the anisotropy of the liquid crystal. It means the display device.

In the process of manufacturing such a liquid crystal display device, a plurality of mask processes are processed in order to form required patterns such as wiring and semiconductor layers. However, when the number of mask processes used is reduced, the manufacturing process of the liquid crystal display device can be simplified. In addition, as the manufacturing process of the liquid crystal display device becomes simpler, manufacturing cost is reduced.

Accordingly, in manufacturing a liquid crystal display, research on a new manufacturing process that can reduce the number of mask processes used is actively being conducted.

An object of the present invention is to provide an etching solution capable of collectively etching a metal double layer and securing the straightness of wiring, and to provide a method of manufacturing a liquid crystal display device which can reduce the number of mask processes by using the same.

In order to achieve the above object, the etchant according to the present invention is for collectively etching Cu / ITO bilayers, and is characterized in that it includes HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor. There is this.

In addition, the metal wiring forming method according to the present invention to achieve the above object, forming an ITO layer on the substrate; Laminating a Cu layer on the ITO layer; Forming a photoresist film on the Cu / ITO layer; Exposing the photoresist to perform patterning; Etching the Cu / ITO layer on the patterned photoresist using an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor; Its features are to include.

In addition, the liquid crystal display device manufacturing method according to the present invention in order to achieve the above object, forming an ITO layer on the substrate; Stacking a Cu layer on the ITO layer to form a Cu / ITO layer to be used as a gate wiring and a gate electrode; Forming a photoresist film on the Cu / ITO layer; Exposing the photoresist to perform patterning; Etching the Cu / ITO layer on the patterned photoresist using an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor; Its features are to include.

According to the present invention, an etching solution capable of collectively etching the metal double layer and ensuring the straightness of the wiring is proposed, and an advantage of providing the liquid crystal display device manufacturing method which can reduce the number of mask processes by using the same. There is this.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, an etching solution including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor is proposed as an etching solution for collectively etching Cu / ITO bilayers. Here, the Cu-inhibitor may be used an azole-based material, an imidazole may be used as a specific example.

The HNO ₃ serves as an etching agent, the H ₂ O ₂ serves as an etching oxident, and the H ₂ MoO ₄ increases the etch rate of ITO. The Cu-inhibitor performs a function of improving the straightness of the wiring formed by etching.

In addition, the etchant presented in the present invention may be formed to further include a chelating agent for preventing changes over time to ATZ (Amino-tetra zole), MBTA (Methyl-benzo Triazole), to further enhance the effect. Here, the chelating agent for preventing the change over time may be used such as EDTA (ETHYLENE DIAMINE TETRAACETIC ACID), ethylene diamine (ETHYLENE DIAMINE).

The ATZ performs the function of adjusting the CD bias, the MBTA performs the function of adjusting the CD bias, and the chelating agent for preventing the change over time will function to prevent the change over time as described. .

Etching liquid according to the present invention having such a configuration as an example for improving the efficiency HNO ₃ (17.5 ~ 20.5wt%), H ₂ O ₂ (0.5 ~ 1.5wt%), H ₂ MoO ₄ (0.01 ~ 0.1wt %), Cu-inhibitor (0.1 ~ 2.0wt%), ATZ (Amino-tetra zole) (1.0 ~ 2.0wt%), MBTA (Methyl-benzo Triazole) (0.5 ~ 1.0wt%), Chelating Agent to prevent change over time ( 0.25 to 0.75 wt%).

The etchant according to the present invention having such a composition can perform effective etching with respect to the Cu / ITO bilayer as shown in Figures 1 to 3. 1 to 3 are views illustrating a state in which etching is performed on a Cu / ITO bilayer using an etchant according to the present invention.

Referring to the process of forming the Cu / ITO bi-layer wiring using the etching solution according to the present invention, first to form an ITO layer on the substrate and to form a Cu layer on the ITO layer. Subsequently, a photoresist layer is formed on the Cu / ITO layer, and the photoresist is exposed to perform patterning.

Subsequently, the patterned photoresist is etched at a time using the etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor. At this time, the lower end of the photoresist film is etched inward, but as shown in FIGS. 1 to 3, it is possible to form a wiring of the Cu / ITO double layer having the straightness secured. For example, in FIG. 2, the Cu layer may be formed at 2000 GPa, and the ITO layer may be formed at 500 GPa.

Next, a process of manufacturing a liquid crystal display using the etchant will be described.

FIG. 4 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along lines VI-VI ′ and VII-VII ′ of FIG. 4.

The lower array substrate of the liquid crystal display shown in FIGS. 4 and 5 has a gate line 102 and a data line 104 formed to intersect on the lower substrate 101 with a gate insulating pattern 112 interposed therebetween. The thin film transistor 130 formed in each section, the pixel electrode 122 and the common electrode 184 formed to form a horizontal electric field in the pixel region provided in the intersection structure, and the common line 186 connected to the common electrode 184. It is provided. The lower array substrate may further include a storage capacitor 140 formed at an overlapping portion of the storage electrode 128 and the gate line 102, the gate pad 150 extending from the gate line 102, and the data line 104. An additional data pad 160 and a common pad 180 extending from the common line 186 are further provided.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the pixel signal are formed in an intersecting structure to define the pixel area. The common line 186 supplying a reference voltage for driving the liquid crystal is formed in parallel with the gate line 102. The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 includes a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain integrated with the pixel electrode 122. An electrode 110 is provided.

In addition, the thin film transistor 130 further includes an active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating pattern 112 therebetween. Equipped. In addition, the active layer 114 is formed to overlap the storage electrode 128. An ohmic contact layer 116 for ohmic contact with the drain electrode 110 and the storage electrode 128 is further formed on the active layer 114.

The pixel electrode 122 is integrated with the drain electrode 110 of the thin film transistor 130 and is integrated with the storage electrode 128 to be formed in the pixel region. In particular, the pixel electrode 122 includes a horizontal portion 122a extending in parallel with the gate line 102 adjacent to the drain electrode 110 and a finger portion 122b extending in the vertical direction from the horizontal portion 122a. do. The pixel electrode 122 is formed of a data metal in the same manner as the data line 104. In this case, a metal such as molybdenum (Mo), copper (Cu), chromium (Cr), or the like is used as the data metal.

The common electrode 184 is connected to the common line 186 and is formed of the transparent conductive film 170 in the pixel region. In particular, the common electrode 184 is formed parallel to the finger portion 122b of the pixel electrode 122 in the pixel region.

Accordingly, a horizontal electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode 184 supplied with the reference voltage through the common line 186. In particular, a horizontal electric field is formed between the finger portion 122b of the pixel electrode 122 and the common electrode 184. The horizontal electric field causes the liquid crystal molecules arranged in the horizontal direction between the lower array substrate and the upper array substrate to rotate by dielectric anisotropy. The light transmittance of the liquid crystal molecules varies depending on the degree of rotation of the liquid crystal molecules, thereby realizing an image.

The storage capacitor 140 overlaps the gate line 102 with the gate line 102, the gate insulating pattern 112, the active layer 114, and the ohmic contact layer 116 interposed therebetween, and the pixel electrode 122. And a storage electrode 128 integrated therewith. The storage capacitor 140 keeps the pixel signal charged in the pixel electrode 122 stable until the next pixel signal is charged.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102 through the gate link 152. The gate pad 150 is formed in a structure in which the transparent conductive layer 170 extended from the gate link 152 connected to the gate line 102 is exposed.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104 through the data link 168. The data pad 160 has a structure in which the transparent conductive film 170 extended from the data link 168 connected to the data line 104 is exposed. Here, the data link 168 includes a data link lower electrode 162 formed of a transparent conductive film 170 and a gate metal layer 172 formed on the transparent conductive film 170, and an upper portion of the data link connected to the data line 104. It consists of an electrode 166.

The common pad 180 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the common line 186 through the common link 182. The common pad 180 is formed to have a structure in which the transparent conductive film 170 extending from the common link 182 connected to the common line 186 is exposed.

The gate electrode 106, the gate line 102, the gate link 152, the data link lower electrode 162, and the common link 182 are formed to overlap the transparent conductive film 170 and the transparent conductive film 170. The gate metal layer 172 is formed. In addition, the gate pad 150, the data pad 160, the common pad 180, and the common electrode 184 are formed of the transparent conductive film 170 from which the gate metal layer 172 is removed.

As described above, in the thin film transistor array substrate according to the first embodiment of the present invention, the gate pad 150, the data pad 160, and the common pad 180 are formed to expose the transparent conductive film 170 having high corrosion resistance. Reliability can be secured.

6A and 6B are plan and cross-sectional views illustrating a first mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

6A and 6B, the gate line 102, the gate electrode 106, the gate link 152, the gate pad 150, and the data of the two-layer structure are formed on the lower substrate 101 by the first mask process. A gate pattern including a pad 160, a data link lower electrode 162, a common electrode 184, a common line 186, a common link 182, and a common pad 180 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 is made of a transparent conductive material such as indium tin oxide (ITO), and the gate metal film 172 is made of a metal such as copper (Cu). Subsequently, the transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask to form a gate line 102, a gate electrode 106, and a gate link 152 having a two-layer structure. The gate pattern includes a gate pad 150, a data pad 160, a data link lower electrode 162, a common electrode 184, a common line 186, a common link 182, and a common pad 180. Is formed. In this case, the Cu / ITO layer may be etched collectively using an etchant including the above-described HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor.

7A and 7B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor array substrate according to the first embodiment of the present invention.

7A and 7B, a semiconductor pattern including a gate insulating pattern 112, an active layer 114, and an ohmic contact layer 116 is formed on a lower substrate 101 on which a gate pattern is formed by a second mask process. Is formed. This second mask process will be described in detail with reference to FIGS. 8A to 8C.

First, as shown in FIG. 8A, the gate insulating layer 111 and the first and second semiconductor layers 113 and 115 are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. . Here, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the material of the gate insulating layer 111, and the first semiconductor layer 113 may be formed of amorphous silicon that is not doped with impurities. As the second semiconductor layer 115, amorphous silicon doped with N-type or P-type impurities is used.

Subsequently, the photoresist film 306 is entirely formed on the second semiconductor layer 115, and then the second mask 300 is aligned on the lower substrate 101. The second mask 300 includes a mask substrate 302 made of a transparent material and a blocking portion 304 formed in the blocking region S2 of the mask substrate 302. Here, the area where the mask substrate 302 is exposed becomes the exposure area S1. By exposing and developing the photoresist film using the second mask 300, the photoresist pattern 308 is formed in the blocking region S2 corresponding to the blocking portion 304 of the first mask 300 as shown in FIG. 8B. Is formed. The first and second semiconductor patterns 113 and 115 and the gate insulating layer 111 are patterned by an etching process using the photoresist pattern 308 to form the gate insulating pattern 112 and the active layer 114 as shown in FIG. 8C. And an ohmic contact layer 116 is formed. In this case, the gate insulating pattern 112 and the semiconductor patterns 114 and 116 are formed to expose the gate pad 150, the data pad 160, the common electrode 184, and the common pad 180.

9A and 9B, the data line 104, the source electrode 108, the drain electrode 110, and the lower electrode 101 are formed on the lower substrate 101 on which the gate insulating pattern 112 and the semiconductor pattern are formed in the third mask process. A data pattern including the storage electrode 128, the data link upper electrode 166, and the pixel electrode 122 is formed. The gate metal layer 172 included in the data pad 160, the gate pad 150, the common pad 180, and the common electrode 184 is removed to expose the transparent conductive layer 170. The third mask process will be described in detail with reference to FIGS. 10A to 10E as follows.

As shown in FIG. 10A, the data metal layer 109 and the photoresist film 378 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 370, which is a partial exposure mask, is aligned on the lower substrate 101. The third mask 370 may include a mask substrate 372 of a transparent material, a blocking portion 374 formed in the blocking region S2 of the mask substrate 372, and a partial exposure region S3 of the mask substrate 372. The formed diffraction exposure part 376 (or semi-transmissive part) is provided. Here, the region where the mask substrate 372 is exposed becomes the exposure region S1. The photoresist film 378 using the third mask 370 is exposed and developed to correspond to the blocking portion 374 and the diffraction exposure portion 376 of the third mask 370 as illustrated in FIG. 10B. A photoresist pattern 360 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 360 formed in the partial exposure region S3 has a second height lower than the photoresist pattern 360 having the first height formed in the blocking region S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 360 as a mask, so that the source electrode 108 and the drain connected to the storage electrode 128, the data line 104, and the data line 104 are drained. A data pattern including an electrode 110, a pixel electrode 122, and a data link upper electrode 166 connected to the other side of the data line 104 is formed, and a gate metal film 172 formed under the data pattern is formed. By removing the gate insulating pattern 112 and the data pattern with a mask, the transparent conductive layer 170 included in the data pad 160, the gate pad 150, the common pad 180, and the common electrode 184 is exposed.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern 360 as a mask. In this case, the active layer 114 and the ohmic contact layer 116 positioned in the remaining region except for the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between the cells by the semiconductor pattern including the active layer 114 and the ohmic contact layer 116.

Subsequently, the photoresist pattern 360 having the second height in the partial exposure area S3 is removed by an ashing process using an oxygen (O ₂ ) plasma, as shown in FIG. 10C, and the blocking area S2 is removed. The photoresist pattern 360 having the first height is in a state where the height is lowered. In the etching process using the photoresist pattern 360, the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor, ie, the channel portion of the thin film transistor, are removed, thereby draining the drain electrode 110 and the source electrode 108. This is separated. The photoresist pattern 360 remaining on the data pattern is removed by a strip process as shown in FIG. 10D.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 10E. As the passivation layer 118, an inorganic insulating material such as the gate insulating pattern 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

FIG. 11 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view illustrating a thin film transistor array substrate taken along lines VII-'I 'and XII-XII' of FIG. 11.

11 and 12, the same components as those of the thin film transistor array substrate shown in FIGS. 4 and 5 except that the common electrode is formed of a transparent conductive film and a gate metal film formed on the transparent conductive film. It is provided. Accordingly, detailed description of the same components will be omitted.

The common electrode 284 is connected to the common line 286 and is formed in the pixel area. In particular, the common electrode 284 is formed parallel to the finger portion 222b of the pixel electrode 222 in the pixel area. The common electrode 284 includes a transparent conductive film 170 in the pixel region and a gate metal film 172 formed on the transparent conductive film 170.

The common pad 280 extending from the common line 286 connected to the common electrode 284, the gate pad 250 and the gate line 202 extending from the gate line 202 formed parallel to the common line 286. The data pad 260 extended from the data line 204 crossing the insulating line 204 is formed to expose the transparent conductive film 170 having high corrosion resistance.

13A to 13C are cross-sectional views illustrating a method of manufacturing the lower array substrate illustrated in FIG. 12.

Referring to FIG. 13A, a gate line 202, a gate electrode 206, a gate link 252, a gate pad 250, and a data pad 260 having a two-layer structure are formed on a lower substrate 101 by a first mask process. ), A gate pattern including a data link lower electrode 262, a common electrode 284, a common line 286, a common link 282, and a common pad 280 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive layer 170 is made of a transparent conductive material such as indium tin oxide (ITO), and the gate metal layer 172 is made of a metal such as copper (Cu). Subsequently, the transparent conductive film 170 and the gate metal layer 172 are patterned by a photolithography process and an etching process using a first mask, thereby forming a two-layered gate line 202, a gate electrode 206, and a gate link 252. The gate pattern includes a gate pad 250, a data pad 260, a data link lower electrode 262, a common electrode 284, a common line 286, a common link 282, and a common pad 280. Is formed. In this case, the Cu / ITO layer may be etched collectively using an etchant including the above-described HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , and Cu-inhibitor.

Referring to FIG. 13B, a semiconductor pattern including a gate insulating pattern 212, an active layer 214, and an ohmic contact layer 216 is formed on a lower substrate 101 on which a gate pattern is formed by a second mask process. This will be described in detail with reference to FIGS. 14A to 14C.

First, as illustrated in FIG. 14A, the gate insulating layer 211 and the first and second semiconductor layers 213 and 215 are sequentially formed on the lower substrate 101 having the gate pattern formed thereon, using a deposition method such as PECVD and sputtering. Is formed. In this case, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film 211, and amorphous silicon without doping impurities is used for the first semiconductor layer 213. As the second semiconductor layer 215, amorphous silicon doped with N-type or P-type impurities is used.

Subsequently, the photoresist film 326 is entirely formed on the second semiconductor layer 215, and then the second mask 320 is aligned on the lower substrate 101. The second mask 320 includes a mask substrate 322 made of a transparent material and a blocking portion 324 formed in the blocking region S2 of the mask substrate 322. Here, the region where the mask substrate 322 is exposed becomes the exposure region S1. By exposing and developing the photoresist film using the second mask 320, the photoresist pattern 328 is formed in the blocking region S2 corresponding to the blocking portion 324 of the second mask 320 as shown in FIG. 14B. Is formed. The first and second semiconductor patterns 213 and 215 and the gate insulating film 211 are patterned by an etching process using the photoresist pattern 328, so that the gate insulating pattern 212 and the active layer ( 214 and an ohmic contact layer 216 are formed. In this case, the gate insulating pattern 212 and the semiconductor patterns 214 and 216 are formed to expose the gate pad 250, the data pad 260, and the common pad 280.

Referring to FIG. 13C, a data line 204, a source electrode 208, a drain electrode 210, and a storage electrode may be formed on a lower substrate 101 on which a gate insulating pattern 212 and a semiconductor pattern are formed in a third mask process. 228, a data pattern including a data link upper electrode 266 and a pixel electrode 222 is formed. The gate metal layer 172 included in the data pad 260, the gate pad 250, and the common pad 280 is removed to expose the transparent conductive layer 170. This third mask process is described in detail with reference to FIGS. 15A to 15E as follows.

As shown in FIG. 15A, the data metal layer 209 and the photoresist film 348 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 340, which is a partial exposure mask, is aligned on the lower substrate 101. The third mask 340 includes a mask substrate 342 made of a transparent material, a blocking portion 344 formed in the blocking region S2 of the mask substrate 342, and a partial exposure region S3 of the mask substrate 342. The formed diffraction exposure part 346 (or semi-transmissive part) is provided. Here, the region where the mask substrate 342 is exposed becomes the exposure region S1. After exposing and developing the photoresist film 348 using the third mask 340, as shown in FIG. 15B, the blocking portion 344 and the diffraction exposure portion 346 of the third mask 340 are exposed. A photoresist pattern 350 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 350 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 350 having the first height formed in the blocking region S2.

The data metal layer 209 is patterned by a wet etching process using the photoresist pattern 350 as a mask, so that the source electrode 208 and the drain connected to the storage electrode 228, the data line 204, and the data line 204 are drained. A data pattern including an electrode 210, a pixel electrode 222, and a data link upper electrode 266 connected to the other side of the data line 204 is formed, and a gate metal film 172 formed under the data pattern is formed. The gate insulating pattern 212 is removed with a mask to expose the transparent conductive layer 170 included in the data pad 260, the gate pad 250, and the common pad 280.

The active layer 214 and the ohmic contact layer 216 are formed along the data pattern by a dry etching process using the photoresist pattern 350 as a mask. In this case, the active layer 214 and the ohmic contact layer 216 positioned in the remaining regions except for the active layer 214 and the ohmic contact layer 216 overlapping the data pattern are removed. This is to prevent a short circuit between the cells by the semiconductor pattern including the active layer 214 and the ohmic contact layer 216.

Subsequently, the photoresist pattern 350 having the second height in the partial exposure area S3 is removed by an ashing process using an oxygen (O ₂ ) plasma as shown in FIG. 15C, and the blocking area S2 is removed. The photoresist pattern 350 having the first height h1 is in a state where the height is lowered. In the etching process using the photoresist pattern 350, the data metal layer and the ohmic contact layer 216 formed in the channel portion of the thin film transistor are removed, that is, the drain electrode 210 and the source electrode 208. This is separated. The photoresist pattern 350 remaining on the data pattern is removed by a stripping process as shown in FIG. 15D.

Subsequently, a protective film 218 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 15E. As the passivation layer 218, an inorganic insulating material such as the gate insulating pattern 212 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

As such, by etching the Cu / ITO double layer using the etchant proposed in the present invention, the wiring of the Cu / ITO double layer having the linearity can be formed. In addition, the method of forming the Cu / ITO double layer wiring according to the present invention may be variously applied as necessary as well as the manufacturing method of the liquid crystal display device described above.

According to the etching solution according to the present invention as described above has the advantage of ensuring the straightness of the wiring by etching the metal double layer consisting of Cu / ITO collectively.

In addition, according to the manufacturing method of the liquid crystal display according to the present invention by forming a wiring to ensure the straightness by etching the dissimilar metal layer consisting of Cu / ITO in a single etching solution, the number of mask process using such an etching solution is reduced There is an advantage to

Claims (20)

As a batch etching of Cu / ITO bilayer, HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , Cu-inhibitor, ATZ (Amino-tetra zole), MBTA (Methyl-benzo Triazole), and chelating agent for preventing change over time, The composition of each component is HNO ₃ (17.5 ~ 20.5wt%), H ₂ O ₂ (0.5 ~ 1.5wt%), H ₂ MoO ₄ (0.01 ~ 0.1wt%), Cu-inhibitor (0.1 ~ 2.0wt% ), ATZ (Amino-tetra zole) (1.0 ~ 2.0wt%), MBTA (Methyl-benzo Triazole) (0.5 ~ 1.0wt%), etchant characterized in that the chelating agent (0.25 ~ 0.75wt%) for the change over time . The method of claim 1, The Cu-inhibitor is an etching solution, characterized in that the azole (azole) material. 3. The method of claim 2, The Cu-inhibitor is an etching solution, characterized in that the imidazole (imidazole). delete The method of claim 1, The chelating agent for preventing the change over time is EDTA (ETHYLENE DIAMINE TETRAACETIC ACID), Etching liquid, characterized in that ethylene diamine (ETHYLENE DIAMINE). delete Forming an ITO layer on the substrate; Laminating a Cu layer on the ITO layer; Forming a photoresist film on the Cu / ITO layer; Exposing the photoresist to perform patterning; For the patterned photoresist, an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , Cu-inhibitor, ATZ (Amino-tetra zole), MBTA (Methyl-benzo Triazole), and a chelating agent for preventing change over time Etching the Cu / ITO layer in a batch; / RTI &gt; The composition of each component is HNO ₃ (17.5 ~ 20.5wt%), H ₂ O ₂ (0.5 ~ 1.5wt%), H ₂ MoO ₄ (0.01 ~ 0.1wt%), Cu-inhibitor (0.1 ~ 2.0wt% ), ATZ (Amino-tetra zole) (1.0 ~ 2.0wt%), MBTA (Methyl-benzo Triazole) (0.5 ~ 1.0wt%), a chelating agent (0.25 ~ 0.75wt%) to prevent changes over time Wiring formation method. 8. The method of claim 7, The Cu-inhibitor is a metal wiring forming method, characterized in that the azole (azole) material. 9. The method of claim 8, The Cu-inhibitor is a metal wiring forming method, characterized in that the imidazole (imidazole). delete 8. The method of claim 7, The chelating agent for preventing change over time is EDTA (ETHYLENE DIAMINE TETRAACETIC ACID), ethylene diamine (ETHYLENE DIAMINE) metal wiring forming method, characterized in that. delete Forming an ITO layer on the substrate; Stacking a Cu layer on the ITO layer to form a Cu / ITO bilayer to be used as a gate wiring and a gate electrode; Forming a photoresist film on the Cu / ITO bilayer; Exposing the photoresist to perform patterning; For the patterned photoresist, an etchant including HNO ₃ , H ₂ O ₂ , H ₂ MoO ₄ , Cu-inhibitor, Amino-tetra zole (ATZ), Methyl-benzo Triazole (MBTA), and a chelating agent for preventing change over time Etching the Cu / ITO bilayers in a batch; / RTI &gt; The composition of each component is HNO ₃ (17.5 ~ 20.5wt%), H ₂ O ₂ (0.5 ~ 1.5wt%), H ₂ MoO ₄ (0.01 ~ 0.1wt%), Cu-inhibitor (0.1 ~ 2.0wt% ), ATZ (Amino-tetra zole) (1.0 ~ 2.0wt%), MBTA (Methyl-benzo Triazole) (0.5 ~ 1.0wt%), a chelating agent for the change over time (0.25 ~ 0.75wt%) Display device manufacturing method. 14. The method of claim 13, Wherein the Cu-inhibitor is an azole-based material. 15. The method of claim 14, The Cu-inhibitor is a liquid crystal display device, characterized in that the imidazole (imidazole). delete 14. The method of claim 13, The chelating agent for preventing change over time is EDTA (ETHYLENE DIAMINE TETRAACETIC ACID), ethylene diamine (ETHYLENE DIAMINE) manufacturing method of the liquid crystal display device. delete 14. The method of claim 13, Wherein the ITO layer is used as a common electrode, and the Cu / ITO double layer is used as a gate wiring and a gate electrode. 14. The method of claim 13, The Cu / ITO double layer is used as a gate wiring and a gate electrode, and is also used as a common electrode.

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