KR100744396B1 - Method of manufacturing array substrate for liquid crystal display - Google Patents

Abstract

A method for manufacturing an array substrate of an LCD is provided to simplify the manufacturing process, by using a half-tone mask so as to facilitate selective etch of a conductive layer for an opposite electrode. An electrode layer of a polycrystalline ITO(Indium Tin Oxide) material and an opaque metal layer are sequentially deposited on a substrate(41), wherein the opaque metal layer includes a first non-reactive metal layer and a wire metal layer of an aluminum material. A resist pattern(500a) is formed on the wire metal layer using a half-tone exposure process. The resist pattern has a first region of a relative thick thickness, a second region of a relative thin thickness, and a third region of an opening part. In the resist pattern, the first region is used for remaining the wire metal layer, and the second region is used for removing the opaque metal layer and remaining the transparent electrode layer. The wire metal layer and the fist non-reactive metal layer are selectively etched by using the resist pattern as an etching mask. A second non-reactive metal layer(N2) is formed on lateral walls of the etched wire metal layer and the etched first non-reactive metal layer using electroless plating. The transparent electrode layer is selectively etched by using the resist pattern and the second non-reactive metal layer as an etching mask. An ashing process is performed on the resist pattern to remove the second region of the resist pattern. The wire metal layer and the first and second non-reactive metal layers are selectively etched by using the remaining resist pattern as an etching mask. The remaining resist pattern is removed.

Description

Manufacturing method of array substrate of liquid crystal display device {METHOD OF MANUFACTURING ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY}

1 and 2 are cross-sectional views illustrating array substrates of a conventional FFS mode liquid crystal display device.

3A and 3D are cross-sectional views illustrating a method of manufacturing an array substrate of an FFS mode liquid crystal display device using a halftone mask according to the prior art.

4A to 4G are cross-sectional views illustrating processes of manufacturing an array substrate of an FFS mode liquid crystal display device according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

41 substrate 42a polycrystalline ITO

42: counter electrode 43b: wiring metal film

43a: etched wiring metal film 43: gate line

44: common electrode line N1b: unreactive first metal film

N1a: unetched unreacted first metal film N1: reetched unreacted first metal film

N2: unreactive second metal film 500a: resist pattern

500: etched resist pattern

The present invention relates to a method for manufacturing a liquid crystal display device, and more particularly, to a method for manufacturing an array substrate of a fringe field switching mode liquid crystal display device which can reduce the number of photolithography processes.

A fringe field switching (FFS) mode liquid crystal display operated by a fringe field is proposed to improve the low aperture ratio and transmittance of an in plain switching mode liquid crystal display. The application was filed in Korean Patent Application No. 98-9243.

In the FFS mode liquid crystal display, the counter electrode and the pixel electrode are formed of a transparent conductor, and the gap between the counter electrode and the pixel electrode is formed to be narrower than the gap (cell gap) between the upper and lower substrates. By forming a fringe field at, all of the liquid crystal molecules present on the electrodes are operated.

FIG. 1 is a cross-sectional view illustrating an array substrate of a conventional FFS mode liquid crystal display device.

As shown, a polycrystalline Indium Tin Oxide (ITO) film is deposited on a transparent insulating substrate 1 such as a glass substrate, and then the ITO film is patterned by a first photo process to form a plate type relative. The electrode 2 is formed. Subsequently, a predetermined opaque metal film, for example, a metal film for wiring such as Mo / Al or Mo / Al / Mo is deposited on the entire surface of the substrate 1 on which the counter electrode 2 is formed, and the second photo process is used for the wiring. The metal film is patterned to form the gate line 3 and the common electrode line 4.

Next, a gate insulating film 5 is deposited on the entire surface of the substrate 1 on which the gate line 3 and the common electrode line 4 are formed, and an undoped amorphous silicon film is formed on the gate insulating film 5. After the doped amorphous silicon film is deposited in sequence, the doped amorphous silicon film and the undoped amorphous silicon film are patterned by a third photo process to form an ohmic contact layer 7 and a channel layer 6.

Next, in a state in which a metal film for data lines is deposited on the resultant, the metal film for data lines is patterned by a fourth photo process to form a data line (not shown) including the source / drain electrodes 8. As a result, a thin film transistor (hereinafter referred to as TFT) is formed in a predetermined portion of the substrate 1.

Subsequently, in order to protect the TFT, a protective film 9 made of, for example, a SiN film is applied on the entire surface of the resultant, and a portion of the protective film is selectively etched by a fifth photo process to obtain a source of the TFT. The contact hole 10 exposing the drain electrode 8 is formed.

Subsequently, in a state in which an ITO film is deposited on the protective film 9, the ITO film is patterned by a sixth photo process to form a slit type pixel electrode 11.

However, in order to form the array substrate of the conventional FFS mode liquid crystal display device as described above, as described above, six photo processes are required. As is well known, the photo process is performed through resist coating, exposure and development processes. Since it includes a resist pattern forming process, an etching process using the resist pattern as a mask, and a removal process of the resist pattern, a long time for performing one photo process is required, and thus six photo processes are included. Since it takes a very long time to manufacture the FFS mode liquid crystal display device, there is a limit to the improvement of the productivity, and there is a difficulty in reducing the manufacturing cost.

Recently, the counter electrode, the gate line, and the common electrode line are formed using one half-tone mask to reduce the number of masks and simplify the process when forming the array substrate of the conventional FFS mode liquid crystal display. A technique has been proposed. Hereinafter, a technique of using the halftone mask will be described in detail.

2 is a cross-sectional view of an array substrate of an FFS mode liquid crystal display device formed using a halftone mask, and FIGS. 3A to 3D illustrate a method of forming a counter electrode, a gate line, and a common electrode line using a halftone mask. It is a process cross section. Here, the manufacturing method of the FFS mode liquid crystal display device using the halftone mask is different from the conventional method, only the process of forming the counter electrode and the gate line common electrode line is different, and other processes Since it is the same, the same part as FIG. 1 is represented with the same reference numeral.

As shown in FIG. 2, a first photo process is performed by sequentially depositing a metal film for a counter electrode such as an amorphous ITO film and a metal film for wiring such as Mo / Al or Mo / Al / Mo on the substrate 1. The wiring metal film and the ITO film are patterned to form the counter electrode 2, the gate line 3, and the common electrode line 4a.

More specifically, as shown in FIG. 3A, in a state in which an amorphous ITO film 2a and a wiring metal film 3a such as Mo / Al or Mo / Al / Mo are sequentially deposited on the substrate 1. And applying a resist on the wiring metal film 3a, and performing an exposure process using the halftone mask 30 to allow partial exposure of a desired portion of the resist, and then exposing the resist. Is developed to form a resist pattern 20a. In this case, the portion of the resist pattern 20a that covers the region where the gate line and the common electrode line are to be formed maintains the coating thickness, while in the region where the counter electrode is to be formed, some thickness remains due to partial exposure. .

Subsequently, as illustrated in FIG. 3B, the laminated metal film is dry-etched by a first etching process using the resist pattern as an etching mask to form a gate line 3 and a common electrode line 4. At this time, the resist pattern 20b remains on the gate line 3 and the common electrode line 4, and the wiring metal film 3a having a predetermined thickness remains in the region where the counter electrode is to be formed.

Next, as shown in FIG. 3C, in the second etching process using the remaining resist pattern 20b and the wiring metal film 3a as an etching mask, the ITO film is wet-etched to form the counter electrode 2. After that, as shown in FIG. 3D, the formation of the counter electrode 2, the gate line 3, and the common electrode line 4 is performed by removing the resist pattern and the wiring metal film remaining in the dry strip process. To complete.

Subsequently, a gate insulating film 5 is deposited on the entire surface of the substrate 1 on which the gate line 3 and the common electrode line 4 are formed, and an undoped amorphous silicon film is formed on the gate insulating film 5. After the doped amorphous silicon film is deposited in sequence, the doped amorphous silicon film and the undoped amorphous silicon film are patterned by a second photo process to form an ohmic contact layer 7 and a channel layer 6.

Next, in a state in which a metal film for data lines is deposited on the resultant, the metal film for data lines is patterned by a third photo process so that a TFT is formed on a predetermined portion of the substrate 1, so that a source / drain electrode ( Form a data line (not shown) including 7).

Next, a protective film 9 for protecting the TFT is deposited on the entire surface of the resultant product, and a predetermined portion of the protective film is selectively etched by a fourth photo process to remove the source / drain electrodes 8 of the TFT. A contact hole 10 for exposing is formed.

Subsequently, in a state in which an ITO metal film is deposited on the passivation layer 9, the ITO metal film is patterned by a fifth photo process to form the pixel electrode 11.

As described above, the manufacturing method of the FFS mode liquid crystal display using the halftone mask 30 simplifies the manufacturing process by forming the counter electrode 2, the gate line 3, and the common electrode line 4 as one mask. You can.

However, the manufacturing method of the array substrate of the FFS mode liquid crystal display device using the conventional halftone mask 30 described above has the following problems.

In the conventional method of manufacturing the FFS mode liquid crystal display using the halftone mask 30 described above, since the wiring metal film and the ITO film are etched in sequence using one resist pattern 20a as an etching mask, the FFS mode liquid crystal display device is etched during the etching of the ITO film. The etching conditions must be adjusted so that the wiring metal layers (gate lines and common electrode lines) are not damaged, but the control of such etching conditions is not easy.

In more detail, in the halftone mask application technology, if the conventional polycrystalline ITO film is used as the counter electrode conductive film as it is, the wiring metal film portion is considerably damaged by the etchant of the polycrystalline ITO film, so that it is more selective than the polycrystalline ITO film. An amorphous ITO film that can be easily etched should be used as the conductive film for the counter electrode.

However, even in the case of using the amorphous ITO film, the selective etching of the amorphous ITO film is not perfect at present, causing a problem that some of the ITO film remains, and a new etchant must be developed to solve this problem. do. However, the development of a new etchant is not only technically easy, but the application of the new etchant may cause additional problems in equipment and processes, thus making it difficult to apply the amorphous ITO film itself. .

As described above, due to the problem that the selective etching between the counter electrode conductive film and the wiring metal film is not easy, it is not easy to realize the process simplification using the halftone mask.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the FFS mode liquid crystal that can facilitate the selective etching of the conductive film for the counter electrode when the halftone mask is applied to simplify the process using the halftone mask It is an object of the present invention to provide a method for manufacturing an array substrate of a display device.

A method of manufacturing an array substrate of a liquid crystal display device of the present invention for achieving the above object, a liquid crystal display comprising a step of patterning a transparent electrode film, such as ITO and a opaque metal film of Al material by a batch etch in succession A method of manufacturing an array substrate of an apparatus, comprising the steps of: sequentially stacking an opaque metal film comprising a transparent electrode film of polycrystalline ITO material and an unreactive first metal film and a wiring metal film of Al material on a substrate; By using a halftone exposure process on the wiring metal film, the first region to leave the wiring metal film has a relatively thick thickness, and the second region to remove the opaque metal film and leave only the transparent electrode film has a relatively thin thickness. Forming a resist pattern having openings in third regions other than the first and second regions; Etching the metal film for wiring in the third region and the unreactive first metal film using the resist pattern as an etching mask; Forming an unreacted second metal film on the sidewalls of the etched wiring metal film and the unreactive first metal film by an electroless plating method; Etching the transparent electrode film using the resist pattern and the unreactive second metal film as an etching mask; Performing an etching process on the resist pattern so that the resist pattern of the second region is removed; Etching the wiring metal film, the unreacted first metal film, and the unreacted second metal film in the second region using the remaining resist pattern as an etching mask; And removing the remaining resist pattern.

Here, the unreactive first metal film and the unreactive second metal film are formed of any one material selected from Mo, Cu, Au, Ag, Pt, and a combination thereof.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4A through 4G are cross-sectional views illustrating processes of manufacturing an array substrate of an FFS mode liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4A, a polycrystalline ITO film 42a for a counter electrode corresponding to a transparent electrode is formed on a transparent insulating substrate 41 such as a glass substrate, and an unreactive agent is formed on the polycrystalline ITO film 42a. An opaque metal film including the one metal film N1 and the wiring metal film 43b is sequentially stacked.

Here, the unreactive first metal film N1b is formed of a noble metal material such as Au, Ag, Pt, etc., Mo, Cu, or any one selected from a combination of the metals. These metals are chemically stable and hardly react with the etchant during subsequent etching of the polycrystalline ITO film 42a. Therefore, the unreactive first metal film N1b serves to prevent damage to the wiring metal film 43b during the subsequent etching of the polycrystalline ITO film 42a.

On the other hand, the wiring metal film 43b is formed of an Al film or a laminated film of Al / Mo.

Then, using the halftone exposure process described above on the wiring metal film 43b, the first portion covering the region where the gate line and the common electrode line are to be formed (the region where the opaque metal film will remain) is relatively thick. The second portion having a lean thickness, the opaque metal film is removed, and only the polycrystalline ITO film remains to cover the region where the counter electrode is to be formed, has a relatively thin thickness, and the remaining portion other than the first and second portions (third portion Section) forms a resist pattern 500a having a removed shape.

Referring to FIG. 4B, the wiring metal film and the unreactive first metal film are etched by wet etching using the resist pattern 500a as an etching mask. Here, reference numerals of the etched wiring metal film and the etched unreactive first metal film are referred to as 43a and N1a, respectively.

Referring to FIG. 4C, an unreactive second metal film N2 is selectively formed on sidewalls of the etched wiring metal film 43a and the etched unreactive first metal film N1a.

Here, the unreactive second metal film N2 is formed of a noble metal or Cu in the same manner as the unreacted first metal film N1b, and has been etched with the etched metal film 43a having excellent conductivity. It is formed by electroless plating so as to be selectively formed only on the sidewall of the first metal film N1a. At this time, electroless plating is not performed on the portion of the polycrystalline ITO film 42a having relatively poor conductivity.

Referring to FIG. 4D, the polycrystalline ITO film is etched using the resist pattern 500a and the unreactive second metal film N2 as an etching mask to form a counter electrode 42 made of ITO. At this time, the etched polycrystalline ITO film 42 'also remains in the gate line forming region.

Here, the etching of the polycrystalline ITO film is performed using an existing etchant for removing polycrystalline ITO, and at this time, the etched wiring metal film 43a is not etched with the unreacted first metal film N1a. Since it is wrapped with the reactive second metal film N2, it is preserved without being damaged.

Referring to FIG. 4E, an ashing process is performed on the resist pattern 500a to remove the second portion of the resist pattern. The etching process selectively isotropically etches only the resist pattern, whereby only the first portion having a thick thickness corresponding to the gate line and the common electrode line forming region remains and the second portion having a relatively thin thickness is removed. Reference numeral 500 denotes a resist pattern remaining.

Referring to FIG. 4F, the wiring metal film 43a etched using the remaining resist pattern 500 as an etching mask, the unreacted first metal film N1a and the unreacted second metal film N2 are etched. Is etched to form the gate line 43 and the common electrode line 44. Here, reference numeral N1 denotes an unreacted first metal film which has been re-etched.

Thereafter, the remaining resist pattern is stripped to fabricate an array structure, as shown in FIG. 4G, and then, although not shown, a subsequent known process is sequentially performed to sequentially perform the FFS mode liquid crystal display of the present invention. The array substrate for a device is manufactured.

As described above, according to the present invention, an unreactive metal film is formed on the lower side and the sidewall of the wiring metal film, thereby preventing the problem that the wiring metal film is damaged by the ITO removal etchant when the ITO film is removed.

Therefore, in the present invention, since the conventional polycrystalline ITO film can be used as the conductive film for the counter electrode instead of the amorphous ITO film, an etchant for removing ITO is also used as an existing etchant for removing the polycrystalline ITO film. Therefore, in the present invention, when the halftone mask is applied, the development of a new etchant according to the use of the conventional amorphous ITO film and the problems thereof are not caused.

As described above, the present invention prevents damage of the wiring metal film to the unreactive metal film when applying the halftone mask, thereby facilitating selective etching of the conductive film for the counter electrode, thereby developing a new etchant and problems in process and equipment. The counter electrode, the gate line and the common electrode line can be formed without causing.

Therefore, according to the method of the present invention, it is possible to more easily realize the process simplification using a halftone mask when manufacturing the array substrate of the FFS mode liquid crystal display.

On the other hand, in the above-described embodiment of the present invention has been shown and described with respect to the manufacturing of the array substrate of the FFS mode liquid crystal display device, the present invention is not limited to this, the method of the present invention is a TN (Twist Nematic) mode liquid crystal display device The same applies to the case where the ITO pixel electrode is formed before the source / drain formation in manufacturing the array substrate.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention is an unreactive metal film formed on the lower and sidewalls of the metal film for the wiring (gate line and common electrode line) to prevent damage to the wiring metal film by the ITO removal etchant when the ITO film is removed. Since it can be prevented at the source, the array substrate for the FFS mode liquid crystal display device can be manufactured without any problems caused by the difficulty of selective etching between the ITO film and the wiring metal film.

Accordingly, the present invention can more easily realize the process simplification using a halftone mask when manufacturing the array substrate of the FFS mode liquid crystal display device, thereby reducing the manufacturing cost and manufacturing time of the array substrate and improving its productivity. .

Claims (2)

In the method of manufacturing an array substrate of a liquid crystal display device comprising the step of patterning a transparent electrode film such as ITO and a opaque metal film made of Al with a batch etch in succession, Sequentially stacking an opaque metal film including a transparent electrode film made of a polycrystalline ITO material and an unreactive first metal film and an wiring metal film made of Al material on a substrate; By using a halftone exposure process on the wiring metal film, the first region to leave the wiring metal film has a relatively thick thickness, and the second region to remove the opaque metal film and leave only the transparent electrode film has a relatively thin thickness. Forming a resist pattern having openings in third regions other than the first and second regions; Etching the metal film for wiring in the third region and the unreactive first metal film using the resist pattern as an etching mask; Forming an unreacted second metal film on the sidewalls of the etched wiring metal film and the unreactive first metal film by an electroless plating method; Etching the transparent electrode film using the resist pattern and the unreactive second metal film as an etching mask; Performing an etching process on the resist pattern so that the resist pattern of the second region is removed; Etching the wiring metal film, the unreacted first metal film, and the unreacted second metal film of the second region using the remaining resist pattern as an etching mask; And Removing the remaining resist pattern; Method of manufacturing an array substrate of the liquid crystal display device comprising a. The method of claim 1, The unreactive first metal film and the unreactive second metal film are formed of any one material selected from Mo, Cu, Au, Ag, Pt, and a combination thereof. .

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