JP2002280880A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop circuit, with which a set/reset function can be provided with a little number transistors. SOLUTION: In the flip-flop circuit having a master circuit 1 and a slave circuit 2, only the master circuit 1 is provided with a transistor TNR for reset and has a function for stopping a clock signal CK1 during a period for resetting or setting, and the driving ability of the transistor TNR is higher than that of a transistor TP3 provided for holding the data of the master circuit 1. Thus, only by adding one transistor, the set/reset function can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit having a master section and a slave section.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional flip-flop is provided with a reset or set transistor in each of a master circuit 11 and a slave circuit 12, and supplies a reset or set signal to initialize the flip-flop.

More specifically, in order to reset the master circuit 11, an NMOS transistor N3 and PM
An OS transistor P3 is provided. In addition, an NMOS transistor N9 and a PMOS transistor P9 are provided to reset the slave circuit 12, and the reset signal R is set to low level to initialize the flip-flop circuit.

FIG. 6 shows an input signal D of the master circuit 11,
FIG. 3 shows a signal waveform diagram of an output signal Q of the slave circuit 12, a reset signal R input to gates of an NMOS transistor N3, a PMOS transistor P3, an NMOS transistor N9, and a PMOS transistor P9.

[0005]

However, the conventional flip-flop comprises a master circuit 11 and a slave circuit 1.
2 to initialize each circuit (NM
OS transistor N3 and PMOS transistor P3
In addition, since the NMOS transistor N9 and the PMOS transistor P9) are provided, the number of transistors constituting the flip-flop circuit is increased, and there is a problem that a chip area and a manufacturing cost increase in manufacturing a semiconductor integrated circuit. Further, there is a problem that the power consumption increases as the number of transistors constituting the transistor increases.

An object of the present invention is to provide a flip-flop circuit capable of realizing a set / reset function with a small number of transistors.

[0007]

In order to solve the above problems, in a flip-flop circuit having a master circuit and a slave circuit, only one of a set and reset transistor is provided only in the master circuit.
A function to stop a clock signal supplied to a master circuit and a slave circuit during a reset or a set period, and to drive a transistor provided for holding a data of the master circuit by a set transistor and a reset transistor. It is characterized by greater than ability.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) An embodiment of the present invention will be described with reference to FIGS. The input signal to the master circuit 1 is D1, the output signal of the slave circuit 2 is Q1, the clock signal is CK1, and the inverted clock signal is N.
CK1 and the reset signal are R1.

First, the state of the signal when the reset signal is L will be described.

At a timing t1 shown in FIG. 2, the clock signal CK1 becomes High (hereinafter referred to as H), the inverted clock signal NCK1 becomes Low (hereinafter referred to as L), and TP1 and TN1 are turned on. At this time, the node B has a value (here, L) obtained by inverting the signal of the input signal D1.

Next, at the falling timing (t2) of the clock CK1, the clock signal CK1 goes low, the clock inverted signal NCK1 goes high, and TP1 and TN1 turn off. On the other hand, TP5 and TN5 are turned on, and the output signal of Q1 becomes a value obtained by inverting the value of the node B (here, H).

Next, the state of the signal at the time of resetting will be described.

First, at the timing of t3, the data (High) before resetting is taken into the master circuit 1. When resetting the clock signal CK
1 is held at a low level, the inverted clock signal NCK1 is held at a high level, and the transistors TP1 and TN1 for taking data into the master circuit 1 are turned off. At this time, the transistors TP4 and TN4 hold the data (H) of the master circuit in the ON state, and the transistors TP5 and TN5
In the ON state, the master data is transmitted to the slave circuit, the transistors TP8 and TN8 are in the OFF state, and data (H) is output from Q1.

In this state, when the reset signal R1 is set to H (t4), the NMOS transistor TNR is turned on. The driving capability of the transistor TP3 is designed to be larger than that of the transistor TP3.
Goes low, the inverter composed of TP2 and TN2 and the inverter composed of TP3 and TN3 are inverted, and the master circuit is initialized. At this time, since the transistors TP5 and TN5 that transmit the data of the master circuit to the slave circuit are in the ON state, the initialized master data (at this time, L) is output from Q1.

Next, the operation for releasing the reset will be described.

Next, when reset is released, the reset signal R1 is set to L while the clock signal CK1 is held at L and NCK1 is held at H (t5), the transistor TNR is turned off, and CK1 is set to H and NCK1 is set to L. (T6). Then, the transistors TN1 and TP1 are turned on, and D
1 is taken into the master circuit. At this time, the transistors TN5 and TP5 are turned off, and the transistor TN5 is turned off.
8 and TP8 are in the ON state, so that the slave circuit holds the state initialized by the reset signal. Next, when the clock signal changes and CK1 is set to L and NCK1 is set to H (t7), the transistors TN1 and TP1 are turned off, and the transistors TN4 and TP4 are turned on. At this time, since the transistors TN5 and TP5 are in the ON state, the data of D1 taken into the master circuit is output from Q1 and the operation as a flip-flop is performed.

According to the present embodiment, set / reset can be performed only by providing a set circuit.

Although the embodiment of the present invention has been described using an NMOS transistor, it can also be realized by a PMOS transistor.

Although the present invention is shown in FIGS. 3 and 4 with respect to an example of the reset circuit, the same effect as the reset circuit can be obtained.

[0021]

According to the present invention, as described above, the set / reset function can be realized by providing at least one of the reset circuit and the set circuit of the slave circuit constituting the flip-flop. Alternatively, the setting circuit can be constituted by only one NMOS transistor or PMOS transistor, so that the number of flip-flop transistors can be reduced and the chip area can be reduced when designing an integrated circuit. Further, power consumption can be reduced in reducing the number of transistors in the reset circuit, which is effective for a low power integrated circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a flip-flop circuit of the present invention.

FIG. 2 is a timing chart of the flip-flop circuit of the present invention.

FIG. 3 is a diagram showing a configuration of a flip-flop circuit of the present invention.

FIG. 4 is a timing chart of the flip-flop circuit of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional flip-flop circuit.

FIG. 6 is a timing chart of a conventional flip-flop circuit.

[Explanation of symbols]

 1 master circuit 2 slave circuit D1 data input signal R1 reset signal CK1 clock signal NCK1 inverted clock signal

Claims (1)

[Claims] 1. A flip-flop circuit having a master circuit and a slave circuit, wherein one of a set transistor and a reset transistor is provided only in the master circuit, and the reset or set period is applied to the master circuit and the slave circuit. A flip-flop having a function of stopping a clock signal to be supplied, wherein the set transistor and the reset transistor have a greater driving capability than a transistor provided for holding data of the master circuit; circuit.