JP3019761B2 - CMOS integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS integrated circuit having a CMOS gate and a latch circuit for transferring data to an input terminal of the CMOS gate by clock control.

[0002]

2. Description of the Related Art In a CMOS inverter as a CMOS gate, when an output potential changes from "H" level to "L" level or from "L" level to "H" level, a PMOS transistor and an NMOS transistor are switched. At the same time, the through current flows from the power supply terminal to the ground terminal. In particular, large current capacity C used for output buffers, etc.
In a MOS inverter, this through current is large, and there is a problem of an increase in current consumption and noise of an integrated circuit.

In order to reduce the through current of the CMOS inverter, gate control may be performed so that the PMOS transistor and the NMOS transistor are not turned on at the same time. Various proposals have been made from this point of view (for example, see JP-A-2-123826 and JP-A-4-20).
No. 7225, JP-A-2-62113, JP-A-6-13
No. 2806).

[0004]

SUMMARY OF THE INVENTION Among the conventionally proposed methods for reducing the through current, Japanese Unexamined Patent Publication No.
JP-A-4-207225 and JP-A-6-132806 both disclose a PMO which is originally commonly connected and serves as an input terminal.
The gates of the S transistor and the NMOS transistor are separated and controlled separately. That is, circuit elements such as a delay element and a switch element are inserted between the gates of the PMOS transistor and the NMOS transistor and the input terminal. Since these circuit elements enter the input signal path of the CMOS inverter, it is necessary to provide these circuit elements for each CMOS inverter in order to perform the same control with a plurality of CMOS inverters.

[0005] Japanese Unexamined Patent Publication No. 2-62113 discloses a PMO
Although the gates of the S transistor and the NMOS transistor are commonly connected, circuit elements are also arranged between the signal input terminal and each gate in order to shift the timing of turning them on, and this circuit element is also used as another CMOS inverter. Cannot be shared with As described above, in the conventional method, when there are a large number of CMOS inverters, circuit elements for preventing a through current are required for each of the CMOS inverters, which makes it difficult to achieve high integration of the integrated circuit.

An object of the present invention is to provide a CMOS integrated circuit capable of suppressing a through current without hindering high integration.

[0007]

According to the present invention, at least one CMOS gate in which the gates of a PMOS transistor and an NMOS transistor are commonly connected to an input terminal, and data is transferred to the input terminal of the CMOS gate by clock control. In a CMOS integrated circuit having a latch circuit, the CMOS gate has auxiliary P
A predetermined time during which the output potential of the CMOS gate changes when the auxiliary PMOS transistor and the auxiliary NMOS transistor are not interposed based on a reference clock. It is characterized by having a timing control circuit for generating a control clock for keeping the transistor and the auxiliary NMOS transistor off.

In the present invention, preferably, the timing control circuit delays a reference clock by a predetermined time to generate a first control clock for controlling the latch circuit; Based on the auxiliary PMOS transistor and the auxiliary NMOS
A second control clock generation circuit for generating a second control clock for keeping the auxiliary PMOS transistor and the auxiliary NMOS transistor off for a predetermined time during which the output potential of the CMOS gate changes when no transistor is inserted. Is done. In the present invention, preferably, one timing control circuit is provided commonly for a plurality of CMOS gates.

According to the present invention, the CMOS gate PM
An auxiliary PMOS transistor and an auxiliary NMOS transistor are inserted into the OS transistor and the NMOS transistor, respectively, and the time period during which a through current flows by the timing control circuit is limited to these auxiliary PMOS transistor and N.
The MOS transistor is turned off. That is, the through current is suppressed by turning on and off the through current path itself, instead of the conventionally proposed control on the gate side. Therefore, in the present invention, since the gates of the MOS transistors constituting the CMOS gate are commonly connected to the input terminal as usual, the timing control circuit can be provided independently of each CMOS gate. In other words, multiple CMOs
One timing control circuit can be provided in common for the S gate. This makes it possible to suppress a through current in the CMOS gate without hindering high integration.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a CMOS integrated circuit according to one embodiment of the present invention. In this embodiment, two CMOS inverters 11 and 12 are shown. The CMOS inverter 11 includes a PMOS transistor QP11 and a NMOS transistor QP11 whose gates are commonly connected to an input terminal Na.
The OS transistor QN11 is a main component. An auxiliary PMO is provided between the output terminal and the PMOS transistor QP11.
S transistor QP12 is inserted, output terminal and NMOS
An auxiliary NMOS transistor QN12 is interposed between the transistors QN11.

Similarly, the other CMOS inverter 12 has a PMOS having a gate connected to the input terminal Nb in common.
It has a transistor QP21 and an NMOS transistor QN21. An auxiliary PMOS transistor QP22 is interposed between the output terminal and the PMOS transistor QP21, and an auxiliary NMOS transistor QN22 is interposed between the output terminal and the NMOS transistor QN21.

Data is transferred to the input terminals Na and Nb of these CMOS inverters 11 and 12 via latch circuits 13 and 14 which are clock-controlled, respectively. In order to control data transfer to the CMOS inverters 11 and 12 and to control through current of the CMOS inverters 11 and 12, these CMOS inverters 11 and 1 are controlled.
2 is provided with a timing control circuit 15 shared by the two.

The timing control circuit 15 generates a first control clock φ1 for controlling the latch circuits 13 and 14 based on the reference clock φ0. Similarly, the timing control circuit 15 generates a first control clock φ1 based on the reference clock φ0. The second control clock generation circuit 19 generates a second control clock φ2 for performing the through current control. First
Control clock generation circuit 16 sets the reference clock φ0 to τ1
This is a delay circuit for delaying only by The second control clock generation circuit 19 includes, for example, an odd-numbered inverter chain (three stages in FIG. 1), inverts the phase of the reference clock φ0 and delays it by τ2, and its delay output φ3. NAN to which reference clock φ0 is input
It is constituted by a D gate 18. However, τ1 <τ2.

The second control clock φ2 obtained from the second control clock generation circuit 19 is a clock which becomes “L” level during the delay time τ2 of the delay circuit 17 from the rise of the reference clock φ0. This second control clock φ2
Are supplied directly to the gates of the auxiliary NMOS transistors QN12 and QN22 of the CMOS inverters 11 and 12, and are supplied to the gates of the auxiliary PMOS transistors QP12 and QP22 by being inverted via the inverters I1 and I2, respectively.

The operation of the CMOS circuit thus configured will be described with reference to FIG. As shown, the first control clock φ lags behind the reference clock φ0 by τ1.
1 is generated, whereby the latch circuits 13 and 14 are controlled, and the held data is transferred to the input terminals Na and Nb of the CMOS inverter. The transfer data causes the potentials at the input terminals Na and Nb to transition, so that the CMOS inverters 11 and 12 are driven.

On the other hand, as shown in FIG. 2, with the timing at which the potentials of the input terminals Na and Nb transition, the second control clock φ2 goes to the “L” level for a time τ2. While the second control clock φ2 is at the “L” level, the CMOS
Auxiliary PMOS transistor Q in inverters 11 and 12
P12, QP22 and the auxiliary NMOS transistor QN12,
QN22 is all kept off.

In the following, the CMOS inverter 11 will be described.
If the "L" level period of the second control clock φ2 is set so as to cover the time zone of the output potential transition when the transistors QP11 and QN11 are simultaneously turned on, a through current flows in the CMOS inverter 11 during that period. Absent.
Then, after either the PMOS transistor QP11 or the NMOS transistor QN11 is sufficiently turned off in accordance with the transferred data, the auxiliary PMOS transistor QP12 and the auxiliary NMOS transistor QN12 are turned on, and the original CMOS inverter operation is performed. Charging and discharging of the load is performed. The same applies to the CMOS inverter 12.

As described above, according to this embodiment, the CMO
By turning on and off the through current path itself of the S inverter, it is possible to suppress the through current at the time of output data transition. According to this embodiment, since no circuit element is inserted in the input signal path of the CMOS inverter, one timing control circuit can be provided in common for a large number of CMOS inverters. Without hindering the power consumption and noise of the CMOS integrated circuit.

Not only an inverter, but also a NAND gate or N
The present invention can be similarly applied to an OR gate. FIG. 3 shows an embodiment applied to a two-input NAND gate. Two PMOS transistors QP31 and QP32 whose gates are respectively connected to the input terminals A and B are provided in parallel on the power supply VDD side, and two NMOS transistors QN31 and QN3 whose gates are also connected to the input terminals A and B, respectively.
2 are provided in series on the ground side to form a NAND gate.

As in the case of the inverter, an auxiliary PMOS transistor QP33 is interposed on the drain side of the PMOS transistors QP31 and QP32,
An auxiliary NMOS transistor QN33 is interposed on the drain side of N31. The control terminal C is directly connected to the gate of the auxiliary PMOS transistor QP33 via the inverter I3 and directly to the gate of the auxiliary NMOS transistor QN33.

FIG. 4 shows an embodiment applied to a two-input NOR gate. Two PMOS transistors QP41 and QP42 whose gates are connected to the input terminals A and B, respectively,
Two NMOS transistors QN41 and QN4 which are provided in series on the DD side and whose gates are connected to input terminals A and B, respectively.
2 are provided in parallel on the ground side to form a NOR gate. An auxiliary PMOS transistor QP43 is inserted on the drain side of the PMOS transistor QP42, and an auxiliary NMOS transistor QN43 is inserted on the drain side of the NMOS transistors QN41 and QN42. The control terminal C is directly connected to the gate of the auxiliary PMOS transistor QP43 via the inverter I4 and to the gate of the auxiliary NMOS transistor QN43 as in FIG.

In the embodiment shown in FIGS. 3 and 4, as in the previous embodiment, the auxiliary PM
The same effect can be obtained by controlling the OS transistor and the auxiliary NMOS transistor. The present invention is not limited to the above embodiment. For example, in the embodiment, an auxiliary PMOS transistor and an auxiliary NM for suppressing a through current are provided.
Although the OS transistor is inserted on the drain side of the main PMOS transistor and the main NMOS transistor, that is, on the output terminal side, these may be inserted on the source side. Further, the through current can be suppressed even if one of the auxiliary PMOS transistor and the auxiliary NMOS transistor is omitted.

[0023]

As explained above, according to the present invention,
The through current path of the CMOS gate can be turned on / off to suppress the through current at the time of output data transition. According to the present invention, since no circuit element is inserted into the input signal path of the CMOS gate, the timing control circuit can be shared by a large number of CMOS gates, so that high integration of the CMOS integrated circuit is not hindered.

[Brief description of the drawings]

FIG. 1 shows a configuration of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 2 shows an operation timing chart of the embodiment.

FIG. 3 shows an embodiment in which the present invention is applied to a NAND gate.

FIG. 4 shows an embodiment in which the present invention is applied to a NOR gate.

[Explanation of symbols]

11, 12 CMOS inverters, 13, 14 latch circuits, 15 timing control circuits, 16 first control clock generation circuits, 19 second control clock generation circuits.
QP12, QP22 ... Auxiliary PMOS transistor, QN12,
QN22 ... Auxiliary NMOS transistor.

Claims (3)

(57) [Claims] 1. A CMOS integrated circuit having at least one CMOS gate having gates of a PMOS transistor and an NMOS transistor commonly connected to an input terminal, and a latch circuit for transferring data to the input terminal of the CMOS gate by clock control. In the above, the CMOS gate is connected to a PMOS transistor side and N
An auxiliary PMOS transistor and an auxiliary NMOS transistor are inserted on the MOS transistor side, respectively, and the output potential of the CMOS gate changes when the auxiliary PMOS transistor and the auxiliary NMOS transistor are not inserted based on a reference clock. A CMOS integrated circuit comprising a timing control circuit for generating a control clock for keeping the auxiliary PMOS transistor and the auxiliary NMOS transistor off for a time. 2. A timing control circuit comprising: a first control clock generating circuit for delaying a reference clock by a predetermined time to generate a first control clock for controlling the latch circuit; A second control clock generation circuit for generating a second control clock for keeping the auxiliary PMOS transistor and the auxiliary NMOS transistor off for a predetermined time during which the output potential of the CMOS gate changes when the PMOS transistor and the auxiliary NMOS transistor are not interposed 2. The CMOS integrated circuit according to claim 1, comprising: 3. The second control clock generation circuit includes: a delay circuit including an odd number of stages of inverter chains for inverting and delaying the reference clock; and a NAND to which an output of the delay circuit and the reference clock are input. 3. The CMOS integrated circuit according to claim 2, further comprising a gate.