JP2002280478A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2002280478A
JP2002280478A JP2001077152A JP2001077152A JP2002280478A JP 2002280478 A JP2002280478 A JP 2002280478A JP 2001077152 A JP2001077152 A JP 2001077152A JP 2001077152 A JP2001077152 A JP 2001077152A JP 2002280478 A JP2002280478 A JP 2002280478A
Authority
JP
Japan
Prior art keywords
metal plate
layer
semiconductor device
external connection
insulating resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001077152A
Other languages
Japanese (ja)
Inventor
Yoshitaka Okugawa
良隆 奥川
Shinichiro Ito
真一郎 伊藤
Kensuke Nakamura
謙介 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP2001077152A priority Critical patent/JP2002280478A/en
Publication of JP2002280478A publication Critical patent/JP2002280478A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, and its manufacturing method, in which fine wiring can be formed, the entire device is made flat even after flip-chip connection of a semiconductor element, and an external connection terminal can be formed easily. SOLUTION: A metal plate is arranged on the periphery of columnar metal electrode terminals arrange at specified positions to penetrate an insulating resin layer, a multilayer wiring layer is formed on the insulating resin layer and a semiconductor element is mounted on the uppermost layer of the wiring layer through flip-chip connection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、外部接続端子層を
有する多層配線板上に半導体素子が搭載されている半導
体装置に関するものである。
The present invention relates to a semiconductor device having a semiconductor element mounted on a multilayer wiring board having an external connection terminal layer.

【0002】[0002]

【従来の技術】近年の電子機器の高機能化、並びに軽薄
短小化の要求に伴い、電子部品の高密度集積化、さらに
は高密度実装化が進んできており、これらの電子機器に
使用される半導体パッケージは、従来にも増して、益
々、小型化且つ多ピン化が進んでいる。
2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages have become smaller and have more pins than ever before.

【0003】これらの小型化したパッケージを電気的に
接続する方法として、絶縁樹脂層に整列された導体端子
電極を埋め込んだ接続用の部材を用いて、電気接続を行
う方法が知られている。このような電気接続部材とし
て、特開昭63−86322号公報には、柱状導電体が
所定の配列で埋め込まれた導電異方性接着剤シートが提
案されているが、柱状導電体が所定の配列で予め絶縁層
に埋め込まれているので、目的とする電極同士を正確に
接続することが出来る。
As a method of electrically connecting these miniaturized packages, there is known a method of making electrical connection using a connection member in which conductor terminal electrodes arranged in an insulating resin layer are embedded. As such an electrical connection member, Japanese Patent Application Laid-Open No. 63-86322 proposes a conductive anisotropic adhesive sheet in which columnar conductors are embedded in a predetermined arrangement. Since the electrodes are embedded in the insulating layer in advance, the target electrodes can be accurately connected to each other.

【0004】また、特開平2−49385号公報には、
金属シート上に感光性ポリイミドをスピンコートして、
フォトエッチングによって、貫通孔を形成した後、電解
金めっきを行って導電部材を形成し、最後に金属シート
をエッチングして除去することによって、ポリイミド樹
脂層に導電部材が埋め込まれた異方導電性接続部材を得
る方法が提案されている。こうして得られた異方導電性
接続部材を用いれば、フォトエッチングによって、微細
な導電部材が形成されているので、目的とする電極同士
を正確に接続することが出来る。また、絶縁層となる感
光性ポリイミドが、予め形成されているので、導電部材
の先端に塗布された樹脂を、後から除去する必要も生じ
ない。さらに、接続する電極のピッチよりも細かなピッ
チで導電部材を形成することによって、接続する電極と
異方導電性接続部材の相対的な位置合わせをしなくても
接続することが出来る。
[0004] Japanese Patent Application Laid-Open No. 2-49385 discloses that
Spin-coat photosensitive polyimide on a metal sheet,
After forming through-holes by photo-etching, electrolytic gold plating is performed to form a conductive member, and finally, the metal sheet is etched and removed, so that the conductive member is embedded in the polyimide resin layer. A method for obtaining a connecting member has been proposed. When the anisotropic conductive connecting member thus obtained is used, since the fine conductive member is formed by photoetching, the target electrodes can be accurately connected to each other. Further, since the photosensitive polyimide serving as the insulating layer is formed in advance, there is no need to remove the resin applied to the tip of the conductive member later. Furthermore, by forming the conductive members at a finer pitch than the pitch of the electrodes to be connected, the connection can be performed without relative positioning between the electrodes to be connected and the anisotropic conductive connection members.

【0005】しかし、これらの半導体装置では、高密度
化のため半導体素子搭載部分の周辺にも回路が配置され
るので、半導体装置全体が大きくなり、充分な強度を保
つことが出来なくなって平坦性を保つことが困難になっ
ている。そこで、半導体素子が搭載されていない部分に
補強板を貼りつけて、反りを低減する対策が行われてい
る。これら補強板には、銅板や合金などの金属板が用い
られており、通常熱圧着タイプの接着剤や、常温接着型
の接着剤を用いて、接着されている。しかし、熱圧着タ
イプの接着剤を用いた場合には、接着時に高温に加熱す
る為、基板が反ってしまう。また、常温接着型の接着剤
は、耐熱性が良くないため、半導体装置を基板に搭載す
る際の半田リフロー時に補強板がはがれてしまうという
問題点があった。
However, in these semiconductor devices, circuits are also arranged around the semiconductor element mounting portion for high density, so that the entire semiconductor device becomes large, and sufficient strength cannot be maintained, and flatness is reduced. It has become difficult to keep. Therefore, measures have been taken to reduce warpage by attaching a reinforcing plate to a portion where the semiconductor element is not mounted. A metal plate such as a copper plate or an alloy is used for the reinforcing plate, and is usually bonded using a thermocompression bonding type adhesive or a room temperature bonding type adhesive. However, when a thermocompression bonding agent is used, the substrate is warped because it is heated to a high temperature during bonding. Further, since the room-temperature adhesive is not good in heat resistance, there is a problem that the reinforcing plate is peeled off at the time of solder reflow when the semiconductor device is mounted on the substrate.

【0006】[0006]

【発明が解決しようとする課題】本発明は、半導体装置
における、上記のような現状の問題点に鑑み、微細配線
が形成でき、外部接続端子の周辺に金属板を配置するこ
とによって装置全体が平坦になり、外部との接続が容易
に形成できる半導体装置を提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in a semiconductor device, and allows fine wiring to be formed. By arranging a metal plate around an external connection terminal, the entire device can be manufactured. It is an object to provide a semiconductor device which is flat and can be easily connected to the outside.

【0007】[0007]

【課題を解決するための手段】即ち、本発明は、外部接
続端子を有する多層配線板上に、半導体素子が搭載され
ており、該外部接続端子が、絶縁樹脂層の表裏を貫通す
るように所定の位置に整列された柱状の金属電極端子か
らなり、該絶縁樹脂層中、該外部接続端子の周辺に金属
板が埋め込まれて配置されていることを特徴とする半導
体装置である。
That is, according to the present invention, a semiconductor element is mounted on a multilayer wiring board having external connection terminals, and the external connection terminals pass through the front and back of the insulating resin layer. A semiconductor device comprising a columnar metal electrode terminal arranged at a predetermined position, wherein a metal plate is embedded in the insulating resin layer around the external connection terminal.

【0008】[0008]

【発明の実施の形態】本発明の半導体装置は、絶縁樹脂
層の表裏を貫通するように所定の位置に整列した柱状の
金属電極端子の周辺に金属板が配置されており、該絶縁
樹脂層の上に複数の層からなる配線層が積層されてお
り、該配線層の最上層に半導体素子が搭載されているこ
とを特徴とする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a metal plate is arranged around columnar metal electrode terminals aligned at predetermined positions so as to penetrate the front and back of an insulating resin layer. A wiring layer composed of a plurality of layers, and a semiconductor element is mounted on the uppermost layer of the wiring layer.

【0009】本発明において、まず、絶縁樹脂層の表裏
を貫通するように所定の位置に整列した柱状の金属電極
端子と、絶縁樹脂層中金属電極端子の周辺に金属板を配
置する方法としては、金属板の一方の面に保護膜を形成
し、他方の面からエッチングによって金属電極端子と周
辺の金属板を同時に形成し、この上に絶縁樹脂フィルム
を積層圧着する方法が使用できる。また、一方の面に銅
箔が絶縁樹脂を介して貼りつけられている金属板を用い
て、該金属板の金属電極端子に対応する位置には、あら
かじめ金属電極よりも大きな穴を形成しておき、この金
属板上に絶縁樹脂層を形成することによって穴の内部に
樹脂を充填し、次いで樹脂で充填された前記穴の内部に
金属電極端子の大きさの穴を形成して、銅箔を電極とし
て電気めっきによって穴の内部を金属で充填して電極端
子を得る方法が使用できる。
In the present invention, first, a columnar metal electrode terminal aligned at a predetermined position so as to penetrate the front and back of the insulating resin layer and a method of disposing a metal plate around the metal electrode terminal in the insulating resin layer are as follows. A method can be used in which a protective film is formed on one surface of a metal plate, a metal electrode terminal and a peripheral metal plate are simultaneously formed from the other surface by etching, and an insulating resin film is laminated and pressed thereon. Also, using a metal plate on one side of which a copper foil is adhered via an insulating resin, a hole larger than the metal electrode is formed in advance at a position corresponding to the metal electrode terminal of the metal plate. And filling the inside of the hole with resin by forming an insulating resin layer on this metal plate, and then forming a hole of the size of a metal electrode terminal inside the hole filled with resin, and forming a copper foil. Can be used as an electrode by filling the inside of the hole with metal by electroplating to obtain an electrode terminal.

【0010】絶縁樹脂層は、絶縁樹脂フィルムをロール
ラミネータや真空ラミネータなどで熱圧着する方法や、
液状の絶縁樹脂を金属板上に流延塗布し、続いて乾燥さ
せる方法などにより形成できる。
The insulating resin layer can be formed by thermocompression bonding of the insulating resin film using a roll laminator or a vacuum laminator.
A liquid insulating resin can be formed by a method of casting and coating on a metal plate, followed by drying.

【0011】金属電極端子の大きさの穴を形成する方法
には,レーザーやプラズマなどの物理的方法や、強アル
カリなどの薬液による化学的な方法が使用出来る。レー
ザーにる方法は、微細な穴が精度良く形成できるので好
適である。レーザーには、炭酸ガスレーザー、UVレー
ザー、エキシマレーザーなどが使用できる。
As a method of forming a hole having the size of a metal electrode terminal, a physical method such as laser or plasma, or a chemical method using a chemical such as a strong alkali can be used. The method using a laser is preferable because fine holes can be formed with high accuracy. As the laser, a carbon dioxide laser, a UV laser, an excimer laser, or the like can be used.

【0012】次いで、このようにして得られた、周辺に
金属板を有する金属電極端子が表裏を貫通した絶縁樹脂
層上に、配線層を形成する。配線層は、銅張り積層板に
回路をエッチングで形成したものを積層する方法や、該
絶縁樹脂層上に、直接一層ずつ、めっきによって形成す
る方法や、第2の金属板上に電気めっきによって形成し
た回路上に絶縁フィルムを積層したものを該絶縁樹脂層
上に積層した後に第2の金属板を除去する方法によって
得ることが出来る。特に、第2の金属板上に電気めっき
によって形成した回路を積層する方法では、微細回路が
容易に形成でき、また、絶縁フィルムを積層した後に、
第2の金属板を電極として層間接続用のバンプ状の金属
電極を、電気めっきで形成することが出来るので、多層
配線を容易に形成することができ、本発明の半導体装置
に好適である。
Next, a wiring layer is formed on the insulating resin layer thus obtained, in which the metal electrode terminals having a metal plate on the periphery penetrate the front and back. The wiring layer is formed by laminating a circuit formed by etching a circuit on a copper-clad laminate, by directly plating one layer on the insulating resin layer, or by electroplating on a second metal plate. It can be obtained by a method in which an insulating film is laminated on the formed circuit, the second metal plate is removed after the insulating film is laminated on the insulating resin layer. In particular, in a method of laminating a circuit formed by electroplating on a second metal plate, a fine circuit can be easily formed, and after laminating an insulating film,
Since a bump-shaped metal electrode for interlayer connection can be formed by electroplating using the second metal plate as an electrode, multilayer wiring can be easily formed, which is suitable for the semiconductor device of the present invention.

【0013】本発明の半導体装置の外部接続端子層に使
用する絶縁樹脂としては、熱可塑性樹脂でも熱硬化性樹
脂でも使用できる。熱可塑性樹脂としては、ポリアミ
ド、ポリイミド、ポリアミドイミド、ポリエーテルイミ
ド、ポリエステルイミド、ポリエーテルエーテルケト
ン、ポリフェニレンサルフィド、ポリキノリン、ポリノ
ルボルネン、液晶ポリマーなどが広く使用できる。熱硬
化性樹脂としては、フェノール樹脂、エポキシ樹脂、ビ
スマレイミド、ビスマレイミド・トリアジン、トリアゾ
ール、シアネート、ポリシアヌレート、イソシアネー
ト、ポリイソシアヌレート、ベンゾシクロブテン、それ
らの変性品などが使用できる。
As the insulating resin used for the external connection terminal layer of the semiconductor device of the present invention, either a thermoplastic resin or a thermosetting resin can be used. As the thermoplastic resin, polyamide, polyimide, polyamide imide, polyether imide, polyester imide, polyether ether ketone, polyphenylene sulfide, polyquinoline, polynorbornene, liquid crystal polymer and the like can be widely used. As the thermosetting resin, phenol resin, epoxy resin, bismaleimide, bismaleimide triazine, triazole, cyanate, polycyanurate, isocyanate, polyisocyanurate, benzocyclobutene, and modified products thereof can be used.

【0014】本発明の半導体装置の外部接続端子層に使
用する金属板には、銅、アルミニウム、鉄、ニッケル、
銅合金、42合金、ステンレス、などが使用できる。金
属板は、フレーム形状に加工された枚葉のものを用いて
も良く、フープ状の連続形状のものを用いてもよい。特
に、フープ状の金属板を用いた場合、連続的に成形する
ことが出来、効率的に生産が可能であり好ましい。
The metal plate used for the external connection terminal layer of the semiconductor device of the present invention includes copper, aluminum, iron, nickel,
Copper alloy, 42 alloy, stainless steel, etc. can be used. As the metal plate, a single plate processed into a frame shape may be used, or a hoop-shaped continuous plate may be used. In particular, when a hoop-shaped metal plate is used, it can be formed continuously and can be efficiently produced, which is preferable.

【0015】金属板の所定位置に金属端子の外形よりも
大きな穴を開口する方法としては、酸やアルカリを用い
て化学的にエッチング除去する方法やレーザーによる方
法が、好適に用いることが出来る。化学的にエッチング
除去する方法では、金属板にレジストでパターンを形成
してもよい。
As a method of opening a hole larger than the outer shape of the metal terminal at a predetermined position on the metal plate, a method of chemically removing the metal terminal with an acid or an alkali or a method of using a laser can be suitably used. In the method of chemically removing by etching, a pattern may be formed on a metal plate with a resist.

【0016】次いで、最上層配線層に半導体素子の電極
に対応する接続用パッドを形成し、半導体搭載用基板を
得る。続いて、バンプ付き半導体素子のバンプを接続用
パッドに位置合わせして加熱圧着し、さらに外部接続用
端子に半田ボールを搭載して半導体装置を得ることがで
きる。
Next, connection pads corresponding to the electrodes of the semiconductor element are formed on the uppermost wiring layer to obtain a semiconductor mounting substrate. Subsequently, the semiconductor device can be obtained by positioning the bumps of the semiconductor element with bumps on the connection pads and heat-pressing them, and further mounting the solder balls on the external connection terminals.

【0017】[0017]

【実施例】以下、実施例に基づき本発明をさらに詳細に
説明するが、本発明はこれによって何ら限定されるもの
ではない。
EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto.

【0018】外部接続端子層に使用する金属板として、
厚さ150ミクロンの銅板1(古河電工製、EFTEC
64T)を用いた(図1(a))。
As a metal plate used for the external connection terminal layer,
150 micron thick copper plate 1 (EFTEC, manufactured by Furukawa Electric)
64T) (FIG. 1 (a)).

【0019】銅板1の表裏にエッチングレジストを形成
し、表裏両面からエッチングによって、0.5mmピッ
チで直径350μmの穴2を一片に50個づつ正方形状
に2500個形成した(図1(b))。
An etching resist was formed on the front and back surfaces of the copper plate 1, and 2,500 holes 2 each having a diameter of 350 μm and a pitch of 0.5 μm were formed in a square of 50 pieces on each side by etching from both the front and back surfaces (FIG. 1B). .

【0020】次に、70μm銅箔4上にシリコーン変性
ポリイミド樹脂層(住友ベークライト製 ITA−10
30)を50μm形成した樹脂付き銅箔3を金属板1の
一方の面から真空ラミネータで180℃で加熱圧着した
(図1(c))。さらに金属板の反対面から、同じシリ
コーン変性ポリイミドのN−メチル−2ピロリドンの溶
液ワニスを流延塗布し、150℃で30分、200℃で
10分、230℃で5分乾燥させて、金属板の両面と穴
の内部をシリコーン変性ポリイミド樹脂で覆った(図1
(d))。
Next, a silicone-modified polyimide resin layer (ITA-10 manufactured by Sumitomo Bakelite) is formed on the 70 μm copper foil 4.
The resin-coated copper foil 3 on which 30) was formed by 50 μm was heat-pressed at 180 ° C. from one surface of the metal plate 1 with a vacuum laminator (FIG. 1C). Further, from the opposite surface of the metal plate, a solution varnish of the same silicone-modified polyimide N-methyl-2-pyrrolidone was cast and applied, and dried at 150 ° C. for 30 minutes, 200 ° C. for 10 minutes, and 230 ° C. for 5 minutes. Both sides of the plate and the inside of the holes were covered with silicone-modified polyimide resin (Fig. 1
(D)).

【0021】次いで、UV−YAGレーザを用いて、先
に形成した350μmの穴と同心円状に200μmの金
属電極用穴5を形成した。穴5はテーパー形状になり、
穴径は、レーザー照射側が200μm、反対側は150
μmであった(図1(e))。
Then, using a UV-YAG laser, a 200 μm metal electrode hole 5 was formed concentrically with the 350 μm hole previously formed. Hole 5 is tapered,
The hole diameter was 200 μm on the laser irradiation side and 150 μm on the opposite side.
μm (FIG. 1 (e)).

【0022】70μmの銅箔4を電極として、穴5の内
部に電解めっきによって、まず金を1μm厚みで層を形
成した後、銅を充填して金属電極6を形成し、外部接続
用端子層7を得た(図1(f))。
Using a 70 μm copper foil 4 as an electrode, a layer of gold is formed to a thickness of 1 μm by electrolytic plating inside the hole 5, and then filled with copper to form a metal electrode 6, and a terminal layer for external connection is formed. 7 was obtained (FIG. 1 (f)).

【0023】前記外部接続端子層7の上に積層する回路
として、バンプ付き回路板20を準備した。バンプ付き
回路板20は、第2の金属板21上に電解めっきによっ
て微細回路22を形成し、回路上にシリコーン変性ポリ
イミドの絶縁フィルム23を真空ラミネータによって加
熱圧着したのち、所定位置にUV−YAGレーザでバン
プ用の穴を形成して、再度第2の金属板21を電極とし
て穴の内部を銅で充填し、得られた銅バンプ24の先端
に半田めっき25をおこなった(図1(g))。
A circuit board 20 with bumps was prepared as a circuit to be laminated on the external connection terminal layer 7. The circuit board 20 with bumps is formed by forming a fine circuit 22 on a second metal plate 21 by electrolytic plating, heating and compressing an insulating film 23 of silicone-modified polyimide on the circuit by a vacuum laminator, and then pressing the UV-YAG Holes for bumps were formed by laser, the insides of the holes were filled with copper again using the second metal plate 21 as an electrode, and solder plating 25 was applied to the tip of the obtained copper bump 24 (FIG. 1 (g)). )).

【0024】次に、外部接続用端子層7上にバンプ付き
回路板20を位置合わせして重ね合わせて、真空プレス
を用いて、250℃で10分、200Nで加熱圧着した
(図2(h))。第2の金属板21をエッチングによっ
て除去した後、同様にして別のバンプ付き回路板を加熱
圧着することを繰り返した。最上層の回路には半導体素
子の電極位置に対応する接続用パッド10を形成した
(図2(i))。外部接続端子層7の反対面に形成され
ている70μm銅箔4をエッチングして除去し、除去後
の表面にソルダーレジスト8(太陽インク製PSR−4
000)を形成し、外部接続用端子11を露出して半導
体装置用基板12を得た(図2(j))。
Next, the circuit board 20 with bumps was positioned on the external connection terminal layer 7 and superimposed, and then heat-pressed at 250 ° C. for 10 minutes at 200 N using a vacuum press (FIG. 2 (h)). )). After removing the second metal plate 21 by etching, heating and pressing another circuit board with bumps in the same manner were repeated. The connection pads 10 corresponding to the positions of the electrodes of the semiconductor element were formed on the uppermost circuit (FIG. 2 (i)). The 70 μm copper foil 4 formed on the opposite surface of the external connection terminal layer 7 is removed by etching, and a solder resist 8 (PSR-4 manufactured by Taiyo Ink) is formed on the surface after the removal.
000), and the external connection terminals 11 were exposed to obtain a semiconductor device substrate 12 (FIG. 2 (j)).

【0025】バンプ付き半導体素子13のバンプを接続
用パッド10に位置合わせして加熱圧着した。外部接続
用端子11に半田ボール14を搭載して半導体装置30
を得た(図3)。
The bumps of the semiconductor element 13 with bumps were positioned on the connection pads 10 and pressed under heat. The semiconductor ball 30 is mounted by mounting the solder balls 14 on the external connection terminals 11.
Was obtained (FIG. 3).

【0026】[0026]

【発明の効果】本発明の半導体装置によれば、所定の位
置に整列した金属電極端子からなる外部接続用端子が絶
縁樹脂層の表裏を貫通するように埋め込まれており、該
外部接続用端子の周辺には金属板が配置されているの
で、半導体素子をフリップチップ接続した後にも平坦な
半導体装置を得ることが出来る。
According to the semiconductor device of the present invention, the external connection terminals composed of metal electrode terminals arranged at predetermined positions are embedded so as to penetrate the front and back of the insulating resin layer. Since a metal plate is arranged around the semiconductor device, a flat semiconductor device can be obtained even after the semiconductor elements are flip-chip connected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例による半導体装置用基板の製造
過程を示す断面図である。
FIG. 1 is a cross-sectional view illustrating a process of manufacturing a semiconductor device substrate according to an embodiment of the present invention.

【図2】本発明の実施例による半導体装置用基板の製造
過程を示す断面図である(図1の続き)。
FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device substrate according to the embodiment of the present invention (continuation of FIG. 1).

【図3】本発明の半導体装置の構造例を示す断面図であ
る。
FIG. 3 is a cross-sectional view illustrating a structural example of a semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1 金属板 2 穴 3 樹脂付き銅箔 4 銅箔 5 金属電極用の穴 6 銅 7 外部接続用端子層 8 ソルダーレジスト 10 接続用パッド 11 外部接続用端子 12 半導体装置用基板 13 バンプ付き半導体素子 14 半田ボール 20 バンプ付き回路板 21 第2の金属板 22 微細回路 23 絶縁フィルム 24 銅バンプ 25 半田めっき 30 半導体装置 DESCRIPTION OF SYMBOLS 1 Metal plate 2 Hole 3 Copper foil with resin 4 Copper foil 5 Hole for metal electrode 6 Copper 7 External connection terminal layer 8 Solder resist 10 Connection pad 11 External connection terminal 12 Semiconductor device substrate 13 Semiconductor element with bump 14 Solder ball 20 Bumped circuit board 21 Second metal plate 22 Microcircuit 23 Insulating film 24 Copper bump 25 Solder plating 30 Semiconductor device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 外部接続端子層を有する多層配線板上
に、半導体素子が搭載されており、該外部接続端子が、
絶縁樹脂層の表裏を貫通するように所定の位置に整列さ
れた柱状の金属電極端子からなり、該絶縁樹脂層中、該
外部接続端子の周辺に金属板が埋め込まれて配置されて
いることを特徴とする半導体装置。
A semiconductor element is mounted on a multilayer wiring board having an external connection terminal layer, and the external connection terminal is
It is composed of pillar-shaped metal electrode terminals arranged in a predetermined position so as to penetrate the front and back of the insulating resin layer, and that a metal plate is embedded and arranged around the external connection terminal in the insulating resin layer. Characteristic semiconductor device.
JP2001077152A 2001-03-16 2001-03-16 Semiconductor device Pending JP2002280478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001077152A JP2002280478A (en) 2001-03-16 2001-03-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001077152A JP2002280478A (en) 2001-03-16 2001-03-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2002280478A true JP2002280478A (en) 2002-09-27

Family

ID=18933952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001077152A Pending JP2002280478A (en) 2001-03-16 2001-03-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2002280478A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227214A1 (en) * 2010-03-18 2011-09-22 Shinko Electric Industries Co., Ltd. Wiring board and method of manufacturing the same, and semiconductor device and method of manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188572A (en) * 1992-12-18 1994-07-08 Sumitomo Bakelite Co Ltd Printed wiring board having metallic core
JP2001007236A (en) * 1999-06-17 2001-01-12 Nitto Denko Corp Waferlike laminate and semiconductor element package and a method of manufacturing waferlike laminate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06188572A (en) * 1992-12-18 1994-07-08 Sumitomo Bakelite Co Ltd Printed wiring board having metallic core
JP2001007236A (en) * 1999-06-17 2001-01-12 Nitto Denko Corp Waferlike laminate and semiconductor element package and a method of manufacturing waferlike laminate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110227214A1 (en) * 2010-03-18 2011-09-22 Shinko Electric Industries Co., Ltd. Wiring board and method of manufacturing the same, and semiconductor device and method of manufacturing the same
JP2011198878A (en) * 2010-03-18 2011-10-06 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same, and semiconductor apparatus and method of manufacturing the same
US8901725B2 (en) 2010-03-18 2014-12-02 Shinko Electric Industries Co., Ltd. Wiring board and method of manufacturing the same, and semiconductor device and method of manufacturing the same

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