JP3800215B2 - Printed wiring board, semiconductor device, and manufacturing method thereof - Google Patents

Description

  The present invention relates to a printed wiring board, a semiconductor device, and a manufacturing method thereof, and particularly has good adhesion between a pad for a semiconductor element and a conductor wiring, and reliability when the semiconductor element is flip-chip mounted on the printed wiring board. The present invention relates to a high printed wiring board, a semiconductor device, and a manufacturing method thereof.

  In a conventional printed wiring board (semiconductor device package), a semiconductor element in which one side of a multilayer substrate body in which conductor wiring is formed in multiple layers via an insulating resin layer is connected to an electrode terminal of the mounted semiconductor element In the package for a semiconductor device, which is a semiconductor element mounting surface on which a pad is formed and the other surface side of the multilayer substrate body is an external connection terminal mounting surface on which an external connection terminal pad is formed, the external connection terminal mounting surface Is bonded to an insulating metal plate subjected to insulation treatment on the entire surface including the inner wall surface of the through hole formed so as to correspond to each of the pads for external connection terminals, and on the semiconductor element mounting surface, There is one in which a metal frame is joined (see Patent Document 1). According to such a configuration, the mounting surface on which the semiconductor element is mounted can be made as flat as possible and the thickness can be made as thin as possible, and warpage due to a difference in thermal expansion between the constituent members can be prevented. is there.

JP 2003-142617 A

  However, the conventional printed wiring board has insufficient adhesion between solder serving as a pad for a semiconductor element and copper plating serving as a conductor wiring. Therefore, when a semiconductor element is mounted on a printed wiring board, if there is a difference in thermal expansion between the semiconductor element and the printed wiring board, the stress generated by the difference in thermal expansion is transmitted to the semiconductor element pad, and the semiconductor element pad And cracks were likely to occur between the wiring and the wiring.

  Further, as the spacing between the semiconductor element pads on the printed wiring board becomes fine pitch (less than 200 μm), short-circuiting between the respective semiconductor element pads is likely to occur, and bump formation on each semiconductor element pad (screen printing, etc.) ) Has become difficult.

  Further, in order to prevent warping of the printed wiring board, if the metal frame (metal plate) joined to the printed wiring board is left as it is as a reinforcing plate (stiffener), the portion in which the semiconductor element is accommodated is recessed. Therefore, it is difficult to form a bump (screen printing or the like) at an accurate position in the region of the concave portion.

  A first object of the present invention is to provide a printed wiring board, a semiconductor device, and a semiconductor device having good adhesion between a semiconductor element pad and a conductor wiring and having high reliability when the semiconductor element is flip-chip mounted on the printed wiring board. It is to provide a manufacturing method.

  A second object of the present invention is to provide a printed wiring board, a semiconductor device, and a manufacturing method thereof, in which bumps are formed at accurate positions of the pads for semiconductor elements.

  In the printed wiring board of the present invention, it is preferable that the conductive layer is made of a conductive copper paste.

  In the printed wiring board of the present invention, it is preferable that the first conductive pad is made of at least one metal selected from the group consisting of gold, tin, and solder, or an alloy thereof.

  In the printed wiring board of the present invention, it is preferable that the second conductive pad includes two layers of a nickel plating layer and a gold plating layer in order from the wiring layer side.

  In the printed wiring board of the present invention, it is preferable that the printed wiring board includes a metal plate that is laminated on the first surface and has a through opening for housing the semiconductor element.

  In the printed wiring board of the present invention, it is preferable that the metal plate is made of at least one metal selected from the group consisting of stainless steel, iron, nickel, copper, and aluminum, or an alloy thereof.

In the first view point of the present invention, in the method of manufacturing a printed wiring board, forming a first insulating layer by pasting the resin coated copper foil on one surface of the metal plate, then the Forming a plurality of openings exposing the metal plate in the first insulating layer, and then forming a concave portion by etching a portion of the metal plate exposed from the opening; Next, a step of forming a first conductive pad made of solder for mounting a semiconductor element on the concave portion by a method of electrolytic solder plating or a method of printing and reflowing a solder paste ; Forming a conductive layer serving as a cushion for absorbing stress with a conductive copper paste in which copper fine particles are dispersed in an insulating resin on the surface of the first conductive pad; and the first insulation including the conductive layer. On the surface of the layer A step of forming a multilayer wiring layer in which a plurality of wiring layers and insulating layers are alternately stacked and via connection is made between the wiring layers, and then from an opening formed in the uppermost insulating layer in the multilayer wiring layer Forming a second conductive pad electrically connected to the corresponding first conductive pad via at least the conductive layer and the wiring layer on the surface of the exposed wiring layer; And exposing the first conductive pad by etching at least a region where the first conductive pad is formed on the metal plate.

  In the method for manufacturing a printed wiring board of the present invention, it is preferable that in the step of forming the second conductive pad, a nickel plating layer and a gold plating layer are formed in order from the wiring layer side.

  In the method for manufacturing a printed wiring board according to the present invention, an opening for housing a semiconductor element is formed in the metal plate so as to include a region where the first conductive pad is formed, Preferably, the method includes a step of exposing one conductive pad and the first insulating layer.

According to a second aspect of the present invention, in the method for manufacturing a semiconductor device, a semiconductor element is connected to a first conductive pad of the printed wiring board manufactured by the method for manufacturing a printed wiring board.

According to the present invention, the conductive layer made of conductive paste or conductive polymer in which conductive fine particles are dispersed in the insulating resin is interposed between the first conductive pad and the wiring layer. The adhesiveness between the conductive pad (semiconductor element pad) 1 and the wiring layer (conductor wiring) is improved, and the reliability when the semiconductor element is flip-chip mounted on the printed wiring board is increased. In addition, even when there is a difference in thermal expansion coefficient between the semiconductor element and the printed wiring board, the conductive layer absorbs stress caused by the difference in thermal expansion coefficient, and the first conductive pad and the wiring layer are And the occurrence of cracks at other parts of the printed wiring board can be prevented. Thereby, a decrease in the yield of the semiconductor device can be suppressed.

  In addition, according to the present invention, the first conductive pad (semiconductor element pad) protruding from the multilayer wiring layer (the first surface thereof) can be used as a bump (solder ball). It can be said that bumps (solder balls) are formed at accurate positions of the pads.

(Embodiment 1)
A semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 1A is a perspective view from the front surface side, FIG. 1B is a perspective view from the back surface side, and FIG. is there. The semiconductor device according to the first embodiment applies a flip chip ball grid array (FCBGA).

  Referring to FIG. 1A, the semiconductor device 1 includes a printed wiring board 10 and a semiconductor element 30. The printed wiring board 10 includes a metal plate 11 and a multilayer wiring layer 21. The metal plate 11 is stacked on the multilayer wiring layer 21 and has a through opening 11 a for accommodating the semiconductor element 30. The multilayer wiring layer 21 is a build-up layer without a substrate serving as a core, and a plurality of wiring layers and insulating layers are alternately stacked, and the wiring layers are via-connected. The multilayer wiring layer 21 can be formed by a build-up method such as a known subtractive method, semi-additive method or full-additive method. The semiconductor element 30 is accommodated in the opening 11 a of the metal plate 11 and mounted on the multilayer wiring layer 21.

  Referring to FIG. 1B, the first bump 20 is mounted on the surface (back surface) opposite to the surface (front surface) on which the metal plate 11 is disposed in the multilayer wiring layer 21.

  Referring to FIG. 1C, the semiconductor device 1 includes a metal plate 11, a first insulating layer 12, a first conductive pad 13, a conductive layer 14, a first wiring layer 15, and a second insulating layer 16. , Second wiring layer 17, third insulating layer 18, second conductive pad 19, first bump 20, semiconductor element 30, second bump 31, and sealing resin 40. The layer in which the first insulating layer 12, the first wiring layer 15, the second insulating layer 16, the second wiring layer 17, and the third insulating layer 18 are stacked is a multilayer wiring layer 21 in FIG. Corresponding to

  The metal plate 11 is a frame-shaped reinforcing plate (stiffener) in which an opening 11a penetrating in the center is formed. Further, since the metal plate 11 is made of metal, it can have a function as the ground of the outermost layer. A semiconductor element 30 is accommodated in the opening 11 a of the metal plate 11. For the metal plate 11, for example, at least one metal selected from the group consisting of stainless steel, iron, nickel, copper and aluminum can be used, and an alloy thereof can be used. If so, copper is optimal. Moreover, the thickness of the metal plate 11 can be 0.1-1.5 mm, for example.

  The first insulating layer 12 is an insulating resin layer that is bonded to the metal plate 11. The first insulating layer 12 has an opening at a position corresponding to the electrode terminal of the semiconductor element 30. In the opening of the first insulating layer 12, at least a first conductive pad 13 and a conductive layer 14 are disposed. As the first insulating layer 12, for example, epoxy resin, epoxy acrylate resin, urethane acrylate resin, polyester resin, phenol resin, polyimide resin, bismaleimide triazine resin, polyphenylene ether resin, fluorine resin, benzocyclobutene resin, liquid crystal polymer, etc. 1 type or 2 or more types of insulating resins selected from these insulating resins may be used, and may be a thermosetting resin or a photosensitive resin. For example, a photosensitive solder resist (manufactured by Taiyo Ink Manufacturing Co., Ltd.) PSR4000 NAS-90-TY, Tamura Kaken DSR 2200 BGX-8, etc.) can be used. In order to increase the substrate strength, a glass cloth, a glass nonwoven fabric, an aramid nonwoven fabric, an aramid film, a polyimide film, or the like may be laminated on the insulating resin as a reinforcing material. In addition, a resin film or a copper foil with resin (RCC) can be used for the first insulating layer 12, and a copper foil with resin is optimal from the viewpoint of buildup.

  The first conductive pad 13 is a conductive medium for electrically connecting to the electrode terminal of the semiconductor element 30. The first conductive pad 13 is disposed for each opening of the first insulating layer 12. For the first conductive pad 13, for example, at least one metal selected from gold, tin, and solder, or an alloy thereof can be used, and a conductive paste or a conductive material mixed with solder powder can be used. Pastes can also be used. When using a conductive paste or a conductive paste mixed with solder powder, the second bumps 31 of the semiconductor element 30 are preferably Au stud bumps. The first conductive pad 13 is optimally solder from the viewpoint of handling.

  The conductive layer 14 is a conductive medium that improves adhesion compared to the case where the first conductive pad 13 and the first wiring layer 15 are directly bonded. For each opening of the first insulating layer 12, It is interposed between one conductive pad 13 and the first wiring layer 15. For the conductive layer 14, a material is selected that has higher adhesion than when the first conductive pad 13 and the first wiring layer 15 are directly joined. For example, an insulating resin such as an epoxy resin or a silicon resin is used as a metal. (Copper, silver, gold, solder, etc.), one or more conductive pastes dispersed with conductive fine particles such as carbon, polypyrrole, polyacetylene, polyaniline, polyarylene, polyarylene vinylene, polythiophene, poly- A conductive polymer such as 3-alkylthiophene can be used, and a conductive copper paste is optimal from the viewpoint of cost. The conductive layer 14 serves as a cushion that absorbs stress transmitted to the printed wiring board via the first conductive pad 13.

  The first wiring layer 15 is a conductive layer in which a wiring pattern is formed on the surface of the first insulating layer 12 including the conductive layer 14. For the first wiring layer 15, for example, at least one metal selected from gold, silver, copper, nickel, or the like by electroless plating, electrolytic plating, or the like can be used, from the viewpoint of cost, Copper is optimal.

  The second insulating layer 16 is an insulating resin layer formed on the surface of the first insulating layer 12 including the first wiring layer 15. The second insulating layer 16 has an opening (via) that communicates with the first wiring layer 15. The second insulating layer 16 can be made of the same material as that of the first insulating layer 12 and may be made of a material different from that of the first insulating layer 12, but from the viewpoint of build-up, resin-coated copper Foil is optimal.

  The second wiring layer 17 is a conductive layer patterned on the surface of the second insulating layer 16 and is electrically connected to the first wiring layer 15 through the opening of the second insulating layer 16 (via connection). ) The second wiring layer 17 may further be formed in multiple layers via the second insulating layer 16 to connect the layers with vias. The second wiring layer 17 can be made of the same material as that of the first wiring layer 15, and copper is optimal from the viewpoint of cost.

  The third insulating layer 18 is an insulating resin layer formed on the surface of the second insulating layer 16 including the second wiring layer 17. The third insulating layer 18 has an opening that communicates with the second wiring layer 17. A second conductive pad 19 is disposed in the opening of the third insulating layer 18. The third insulating layer 18 can be made of the same material as that of the first insulating layer 12 and may be made of a material different from that of the first insulating layer 12 and the second insulating layer 16. Considering that it is the surface layer of the layer, a solder resist is optimal.

  The second conductive pad 19 is a conductive medium formed on the surface of the second wiring layer 17 in the opening of the third insulating layer 18. The second conductive pad 19 is electrically connected to the corresponding first conductive pad 13 through at least the second wiring layer 17, the first wiring layer 15, and the conductive layer 14. For the second conductive pad 19, for example, at least one metal selected from gold, tin, nickel, and solder by electroless plating, electrolytic plating, or the like can be used, and an alloy thereof can be used. it can. The second conductive pad 19 may have not only a single layer structure but also two or more layers. If the adhesiveness between the second conductive pad 19 and the second wiring layer 17 is considered, the second conductive pad 19 A two-layer structure of a nickel plating layer and a gold plating layer is optimal in order from the wiring layer 17 side.

  The first bump 20 is a conductive protrusion medium that is formed on the surface of the second conductive pad 19 and is electrically connected to an external electronic component (not shown). The first bump 20 is coated with a metal material on the surface of a metal material such as gold, silver, copper, solder (Sn—Pb eutectic solder, Sn—Ag—Cu solder, etc.), a conductive resin, or a resin member. A composite material can be used, and solder balls are optimal from the viewpoint of handling and the like.

  The semiconductor element 30 is a semiconductor chip such as an LSI, for example, and the electrode terminal of the semiconductor element 30 is connected to the first conductive pad 13 via the corresponding second bump 31. A material similar to that of the first bump 20 can be used for the second bump 31, and solder is optimal from the viewpoint of handling and the like.

  The sealing resin 40 is an insulating resin that seals a gap between the semiconductor element 30 and the first insulating layer 12. A known sealing material (for example, epoxy resin) can be selected and used for the sealing resin 40 according to the required characteristics.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 1 of the present invention will be described with reference to the drawings. 2 and 3 are partial cross-sectional views schematically showing the cross-section of the printed wiring board according to Embodiment 1 of the present invention in the order of the steps in the main manufacturing process. 2 and 3 are simply separated for the convenience of drawing.

  First, after forming the first insulating layer 12 on one side of the surface of the metal plate 11, an opening 12a exposing the metal plate 11 is formed at a predetermined position of the first insulating layer 12 (step A1; FIG. 2 (A)). Here, the first insulating layer 12 may be formed by, for example, (1) a method in which a resin film is attached and the opening 12a is formed by a laser beam such as a YAG laser or a carbon dioxide gas laser. A method of removing the unnecessary copper foil by attaching copper foil (RCC), etching the copper foil of the opening 12a, forming the opening 12a by plasma, and (3) printing, coating, etc. A method of forming the opening 12a with a laser beam such as a YAG laser or a carbon dioxide gas laser, and (4) a photolithography method in which a photosensitive resin is printed, applied, and cured as the first insulating layer 12. From the viewpoint of buildup, a method using a resin-coated copper foil is optimal. Here, no holes are formed in the metal plate 11. In addition, when the opening 12a is formed by laser light, it is preferable to wash with a permanganic acid solution in order to remove contamination attached to the wall surface of the opening 12a.

  Next, the first conductive pad 13 is formed on the bottom surface of the opening 12a of the first insulating layer 12 (step A2; see FIG. 2B). Here, the first conductive pad 13 (for example, solder) is formed by, for example, (1) a method of forming by electrolytic solder plating, (2) filling (printing, etc.) solder paste and reflowing. There is a method of forming.

  Next, the conductive layer 14 is formed on the surface of the first conductive pad 13 (step A3; see FIG. 2C). Here, the conductive layer 14 (for example, conductive copper paste) can be formed by printing such as an inkjet method or a screen method.

  Next, a first wiring layer 15, a second insulating layer 16, a second wiring layer 17, and a third insulating layer 18 are formed in this order on the surface of the first insulating layer 12 including the conductive layer 14. Then, the multilayer wiring layer 21 in which the wiring layers are via-connected is formed (step A4; see FIG. 2D). Here, the first wiring layer 15 (for example, copper plating) performs, for example, chemical roughening (desmearing, resin roughening, etc.) on the surface of the first insulating layer 12, and then the assembly surface (via). After the seed layer is formed by electroless copper plating on the bottom (including the bottom), a circuit-forming dry film is laminated to the substrate, mask exposure and development processes are performed, and a desired wiring pattern is formed, followed by electrolytic plating. The wiring pattern can be formed by the method, the dry film is peeled off, and then the seed layer is removed by etching. The second wiring layer 17 (for example, copper plating) can also be formed by the same method as that for the first wiring layer 15. The second insulating layer 16 (for example, copper foil with resin) can be formed by the same method as the first insulating layer 12 (for example, method using a copper foil with resin). Note that a plurality of wiring layers and insulating layers may be formed on the second wiring layer 17 and the layers may be via-connected. The third insulating layer 18 can be formed by a method similar to that of the first insulating layer 12 (for example, a method using a photosensitive resin (solder resist)). An opening 18 a that exposes the second wiring layer 17 is formed at a predetermined position of the third insulating layer 18.

  Next, a second conductive pad 19 is formed on the surface of the second wiring layer 17 exposed from the opening formed in the third insulating layer 18 (step A5; see FIG. 3A). Here, the second conductive pad 19 (for example, a laminated structure of a nickel plating layer and a gold plating layer) can be formed by, for example, an electrolytic plating method.

  Next, an opening 11a for accommodating the semiconductor element is formed in the metal plate 11 so as to include a region where the first conductive pad 13 is formed, and the first conductive pad 13 and the first conductive pad 13 are formed. The insulating layer 12 is exposed (step A6; see FIG. 3B). Here, the opening 11a forms an etching resist 22 having an opening on the surface of the metal plate 11 on the surface opposite to the surface on which the multilayer wiring layer is disposed, and then the etching resist 22 is used as a mask. The portion of the metal plate 11 exposed from the opening of the etching resist 22 can be formed by etching until the first conductive pad 13 and the first insulating layer 12 are exposed. In the etching, an etching resist may be formed on the surface of the third insulating layer 18 including the second conductive pad 19 to protect the second conductive pad 19. The formation method of the etching resist 22 includes (1) a method of laminating the etching resist 22 by a spin coating method, a die coating method, a curtain coating method, a printing method or the like when the etching resist 22 is in a liquid state, and (2) the etching resist 22 In the case of a dry film, the etching resist 22 is laminated by a laminating method or the like, and then the etching resist 22 is hardened by performing a treatment such as drying. (3) If the etching resist 22 is photosensitive, the etching resist 22 is photolithographic method or the like. And (4) a method of patterning the etching resist 22 by a laser processing method or the like when the etching resist 22 is non-photosensitive. For etching, an etchant such as an alkaline etchant is used, for example, in which the metal plate 11 (eg, copper) is eluted and the first conductive pad (eg, solder) is not eluted. After the opening 11a is formed, the etching resist 22 is removed.

  Next, the semiconductor element 30 is flip-chip connected to the first conductive pad 13 by the second bump 31, and the sealing resin 40 is poured into the space between the semiconductor element 30 and the first insulating layer 12 and cured. (Step A7; see FIG. 3C).

  Finally, the first bump 20 is mounted on the second conductive pad 19 (step A8; see FIG. 3D).

  According to the printed wiring board configured as described above, since the multilayer wiring layer 21 is provided on the flat metal plate 11, the flatness of the multilayer wiring layer 21 is good. In the semiconductor device, since the semiconductor element 30 is housed in the opening of the metal plate 11 and connected to the outermost surface of the flat multilayer wiring layer 21 without warping, the connection between the multilayer wiring layer 21 and the semiconductor element 30 is performed. The part is stable and reliable. Furthermore, since the conductive layer 14 is interposed between the first conductive pad 13 and the first wiring layer 15, the adhesion between the first conductive pad 13 and the first wiring layer 15 is improved. Further, when the semiconductor element 30 is mounted on the printed wiring board 10, even if a stress due to a difference in thermal expansion coefficient is generated between the semiconductor element 30 and the printed wiring board 10, the first connected to the semiconductor element 30. The stress transmitted by the conductive pad 13 is absorbed by the conductive layer 14, and the occurrence of cracks between the first conductive pad 13 and the first wiring layer 15 can be prevented, and the semiconductor element 30 is printed. The reliability when flip-chip mounting on the wiring board 10 is further increased.

(Embodiment 2)
A semiconductor device and a printed wiring board according to Embodiment 2 of the present invention will be described with reference to the drawings. 4A is a perspective view from the front surface side, FIG. 4B is a perspective view from the back surface side, and FIG. 4C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. is there. The semiconductor device according to the second embodiment also uses a flip chip ball grid array (FCBGA). The semiconductor device according to the second embodiment and the semiconductor device according to the first embodiment are substantially the same except for the configuration of the first conductive pad, but the shape of the first conductive pad is different.

  Referring to FIG. 4C, the first conductive pad 13 is a conductive medium for electrically connecting to the electrode terminal of the semiconductor element 30, and has a protruding shape protruding from the surface of the first insulating layer. It is a pad. The first conductive pad 13 is arranged for each opening of the first insulating layer 12 and is flip-chip connected to the semiconductor element 30 via the second bump 31. For the first conductive pad 13, for example, at least one metal selected from gold, tin and solder can be used, and an alloy thereof can be used. Solder is optimal. In addition, if the 1st conductive pad 13 is formed with solder, the 1st conductive pad 13 can be used as a bump (solder ball). Further, if the first conductive pad 13 is a bump (solder ball), the second bump 31 may not be formed.

  Next, a method for manufacturing a semiconductor device and a printed wiring board according to Embodiment 2 of the present invention will be described with reference to the drawings. 5 and 6 are partial cross-sectional views schematically showing the cross-section of the printed wiring board according to Embodiment 2 of the present invention in the order of the steps in the main manufacturing process. 5 and 6 are simply separated for convenience of drawing.

  First, after the first insulating layer 12 is formed on one side of the surface of the metal plate 11, a plurality of openings for exposing the metal plate 11 are formed in the first insulating layer 12, and then, from the openings A concave portion 11b is formed in the exposed portion of the metal plate 11 (step B1; see FIG. 5A). Here, as a method for forming the concave portion 11b, for example, (1) a resin film is attached, an opening is formed in the first insulating layer 12 by laser light such as YAG laser or carbon dioxide laser, A method of etching the metal plate 11 exposed from the opening of the insulating layer 12 to form the concave portion 11b, and (2) a copper foil with resin (RCC) is pasted and the copper in the opening of the first insulating layer 12 The foil is etched, an opening is formed in the first insulating layer 12 by plasma, unnecessary copper foil is removed, and the metal plate 11 exposed from the opening of the first insulating layer 12 is etched to form the concave portion 11b. (3) A thermosetting resin is printed, applied, etc., cured, and an opening is formed in the first insulating layer 12 by a laser beam such as a YAG laser or a carbon dioxide gas laser, and an unnecessary copper foil is formed. The opening of the first insulating layer 12 is removed (4) The first insulating layer 12 is cured by printing, applying, or the like with a photosensitive resin, and the first insulating layer 12 is cured by photolithography. There is a method of forming an opening in the layer 12, removing unnecessary copper foil, etching the metal plate 11 exposed from the opening of the first insulating layer 12 to form the concave portion 11 b, etc. From the viewpoint, the method using a copper foil with resin is optimal. Further, when the opening is formed in the first insulating layer 12 by laser light, it is preferable to wash with a permanganate solution in order to remove the contamination attached to the wall surface of the opening.

  Next, the first conductive pad 13 is formed in the recessed portion 11b of the metal plate 11 and the opening of the first insulating layer 12 (step B2; see FIG. 5B). Here, the first conductive pad 13 (for example, solder) is formed by, for example, (1) a method of forming by electrolytic solder plating, (2) filling (printing, etc.) solder paste and reflowing There is a method of forming.

  The step of forming the conductive layer 14 performed after Step B2 (Step B3; see FIG. 5C), the step of forming the multilayer wiring layer 21 (Step B4; see FIG. 5D), the second conductive Forming the conductive pad 19 (step B5; see FIG. 6A), forming the opening 11a in the metal plate 11 (step B6; see FIG. 6B), and flip-chip connecting the semiconductor element 30. The steps of pouring and curing the sealing resin 40 (step B7; see FIG. 6C) and the step of attaching the first bump 20 (step B8; see FIG. 6D) are the embodiments. Steps A <b> 3 to A <b> 8 related to Step 1 are the same.

  According to the printed wiring board configured as described above, since the multilayer wiring layer 21 is provided on the flat metal plate 11 as in the first embodiment, the flatness of the multilayer wiring layer 21 is good. In the semiconductor device, the semiconductor element 30 is accommodated in the opening of the metal plate 11 and connected to the outermost surface of the flat multilayer wiring layer 21 without warping. The part is stable and highly reliable. Furthermore, since the conductive layer 14 is interposed between the first conductive pad 13 and the first wiring layer 15, the adhesion between the first conductive pad 13 and the first wiring layer 15 is improved. The reliability when the semiconductor element 30 is flip-chip mounted on the printed wiring board 10 is further increased. In addition, by forming the first conductive pad 13 protruding from the first insulating layer 12 in advance by the concave portion 11b formed in the metal plate 11, an accurate corresponding to the second bump 31 of the semiconductor element 30 is obtained. Bumps (solder balls) can be formed at the positions.

1A is a perspective view from the front surface side, FIG. 2B is a perspective view from the back surface side, and FIG. 2C is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. It is the 1st partial sectional view showing typically the section of the printed wiring board concerning Embodiment 1 of the present invention in order of the process about the main manufacturing process. It is the 2nd partial sectional view showing typically the section of the printed wiring board concerning Embodiment 1 of the present invention in order of the process about the main manufacturing process. FIG. 5A is a perspective view from the front surface side, (B) a perspective view from the back surface side, and (C) a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. It is the 1st partial sectional view showing typically the section of the printed wiring board concerning Embodiment 2 of the present invention in order of the process about the main manufacturing process. It is the 2nd partial sectional view showing typically the section of the printed wiring board concerning Embodiment 2 of the present invention in order of the process about the main manufacturing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Printed wiring board 11 Metal plate 11a Opening part 11b Recessed part 12 1st insulating layer 12a Opening part 13 1st electroconductive pad 14 Conductive layer 15 1st wiring layer 16 2nd insulating layer 17 2nd Wiring layer 18 third insulating layer 18a opening 19 second conductive pad 20 first bump 21 multilayer wiring layer 22 etching resist 30 semiconductor element 31 second bump 40 sealing resin

Claims (4)

Forming a first insulating layer by affixing a copper foil with resin on one side of the surface of the metal plate;
Next, forming a plurality of openings exposing the metal plate in the first insulating layer;
Next, a step of forming a concave portion by etching a portion of the metal plate exposed from the opening,
Next, a step of forming a first conductive pad made of solder for mounting a semiconductor element on the concave portion by a method of electrolytic solder plating or a method of printing and reflowing a solder paste ;
Next, forming a conductive layer serving as a cushion for absorbing stress with a conductive copper paste in which copper fine particles are dispersed in an insulating resin on the surface of the first conductive pad;
Forming a multilayer wiring layer in which a plurality of wiring layers and insulating layers are alternately stacked on the surface of the first insulating layer including the conductive layer, and the wiring layers are via-connected;
Next, on the surface of the wiring layer exposed from the opening formed in the uppermost insulating layer in the multilayer wiring layer, at least the first conductive pad and the electric corresponding to the surface through the wiring layer and the wiring layer. Forming a second conductive pad to be electrically connected;
Next, the step of exposing the first conductive pad by etching at least a region of the metal plate where the first conductive pad is formed;
A printed wiring board manufacturing method comprising: In said second conductive forming a pad, in order from the wiring layer side, a manufacturing method of claim 1 printed wiring board, wherein the forming a nickel plating layer and a gold plating layer. An opening for accommodating a semiconductor element is formed in the metal plate so as to include a region where the first conductive pad is formed, and the first conductive pad and the first insulating layer are formed. claim 1 or 2 method of manufacturing a printed wiring board according to comprising the step of exposing the. The method of manufacturing a semiconductor device characterized by connecting the semiconductor element to the first conductive pad of the printed wiring board manufactured by the method according to any one of claims 1 to 3.

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