JP2002271207A - Data conversion device, data compression device and data extension device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for data conversion, data compression and data extension, capable of expressing a wide dynamic range with little distortion. SOLUTION: The peak levels of 24-bit input data are decided, and a flag associated with each peak level is made to correspond. A flag for input levels between 0 through 2 is set to 0, and the data is compressed by a fixed point system, thereby the data portion corresponding to 11 bits is assigned as data of fixed point system. Also, a flag for input levels between 11 through 18 is set 0, and the data is compressed by the fixed point method. A flag for levels between 3 through 10 is set to 1, and the data is compression processed by a floating point system. When Singbit continues consecutively for four or more from MSB in the fixed point system, the data is set to data of 11 bits in the fixed point system which is shifted to the right by 8 bits. Accordingly, when an input is smaller than -66 dB, the data is treated as data of fixed point data and the level of noise floor will not change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion device, a data compression device and a data expansion device for compressing and expanding waveform data such as audio data.

[0002]

2. Description of the Related Art There are various methods for compressing and decompressing audio data. As a method for compressing and decompressing only one data, a fixed-point method of simply extracting a required number of bits from upper bits is used. Techniques, floating-point techniques that assign data like mantissa and exponent,
There is a method of performing a polygonal line approximation on the data itself.

Here, these methods will be described below by taking as an example a method of compressing 24-bit data, often used as audio data, to 12 bits.

First, Table 1 (FIG. 4) shows the relationship between input data and 24-bit input data expressed in two's complement. Here, S indicates Signbit (sign bit), SN indicates an inverted value of Signbit (sign bit), and * indicates a value of 0 or 1 which is arbitrary data. In this way, the 24-bit data can always be applied to any of the levels in Table 1. By the way, positive full scale is
0111 1111 1111 1111 1111
1111, negative full scale is 1000 0000
Since it is 0000 0000 0000 0000, it is applied to level 0. For the sake of simplicity, the quantization noise per bit is 6 dB and is shown as an input level on the right side of Table 1. The dynamic range of 24 bits is 24 bits × 6 dB = 144 dB.

Fixed-point method: Table 2 (FIG. 5) and Table 1
An example in which such 24-bit data is compressed by a 12-bit fixed point method is shown, and Table 3 (FIG. 6) shows the data configuration after compression. As can be seen from Tables 2 and 3, in the case of the fixed-point system, only the upper 12 bits are extracted as they are. In this case, the effective bit length at full scale (0 dB) is 12 bits, and S / N + D is about 72 bits.
The dynamic range is also 72 dB. Note that S
/ N + D are the effective value of the signal (S: Signal) and the effective value of all the spectral components on the measurement band other than the signal (N + D).
D: N is the ratio of Noise, and D is the ratio of Distortion). This fixed-point method is characterized in that the circuit is very simple and S / N + D equal to the dynamic range can be obtained.

Floating point method: 24 bi as shown in Table 1
Table 4 (FIG. 7) shows an example of a case where the t data is compressed by a floating-point method in which the mantissa part is 8 bits and the exponent part is 4 bits.
Table 5 (FIG. 8) shows the data configuration after compression to 2 bits.
The data of the exponent part is the MS of the data to be taken in during compression.
It corresponds to the shift amount from B. In this compression, a dynamic range of 138 dB (corresponding to 23 bits) can be obtained, but since the mantissa is only 8 bits, the S / N + D at 0 dB is only about 48 dB, and the input level drops to −24 dB (level 4). The same S / N + D as in the fixed-point system can be obtained. This floating point method is characterized in that a wide dynamic range can be obtained with a small data length.

[0007] A broken-line approximation method: This method is a method in which when the signal level is high, the quantization step is made coarse and when the signal level is low, the quantization step is made fine. It is not necessary to have an exponent area, and the S / N + D and the dynamic range can be improved as compared with the floating point method.

[0008]

However, the above fixed point method has a problem that a wide dynamic range cannot be obtained because the dynamic range is determined by the data length.

In the floating point method, since an exponent area is required, the effective bit length is reduced accordingly. Therefore, there is a problem that S / N + D becomes worse and quantization noise changes depending on the level of the signal level.

Further, in the polygonal line approximation method, it is necessary to change the compression gradient in accordance with the data, so that the configuration becomes complicated in hardware, and it is not possible to improve S / N + D when the input level is large. Can not.

An object of the present invention is to solve the above problems and to compress input data into fixed-point data or floating-point data comprising a mantissa part and an exponent part by a simple method. By a simple method,
A data converter that can express a wide dynamic range with little distortion even when the level of input data is large.
A data compression device and a data decompression device are provided.

[0012]

According to a first aspect of the present invention, there is provided a data conversion apparatus for converting floating-point data comprising a mantissa part having a sign bit and an exponent part into data of a fixed-point representation. Means for level-shifting the data of the mantissa part based on the data of the part, and means for inserting the sign bit into lower-order bits of the level-shifted data.

According to the first aspect of the present invention, a positive range and a negative range are different in a two's complement display in which a positive or negative value is displayed by adding a sign bit.
To 127, whereas negative values represent -1 to -128). When the data is level-shifted and changed to the fixed-point display based on this data (because it is a multiple of 2), the difference between the widths of the positive range and the negative range increases, and an offset occurs. According to the first aspect of the present invention, a positive sign bit “0” is inserted in the case of a positive value, and a negative sign bit “1” is inserted in the case of a negative value. Moves to the positive side, reducing the offset.

According to a second aspect of the present invention, there is provided a data conversion device for converting floating-point data represented by a mantissa part having a sign bit and an exponent part into data of a fixed-point representation, based on the data of the exponent part. Means for level-shifting the data of the mantissa and means for inserting a random number into lower-order bits of the level-shifted data.

The conventional conversion from floating-point representation to fixed-point representation is simply a level shift.
For example, when changing the floating-point representation consisting of an 8-bit mantissa part and a 4-bit exponent part to a 24-bit fixed-point representation, the lower bits of the bit-shifted data are "0". In the case of a large number, only the upper 8 bits fluctuate, so the possible values are large discrete values, which change in a large step-like manner. That is, the waveform has a large harmonic. According to the second aspect of the present invention, since a random number is inserted into the lower bits, a waveform with less harmonics can be output.

A third aspect of the present invention is a data compression apparatus for compressing data of a fixed-point display, wherein data of a predetermined range of the data of the fixed-point display is converted into data of a floating-point display. Converting means for converting, data for changing the data other than the level in a predetermined range of the data of the fixed decimal point display to data of a fixed decimal point display having a predetermined number of bits, the converting means and the changing means Means for generating a flag bit for discriminating whether the data obtained by the above is a floating-point representation or a fixed-point representation.

According to a fourth aspect of the present invention, in the third aspect, the most significant bit of the mantissa part of the data of the floating-point representation is omitted.

According to a fifth aspect of the present invention, in the fourth aspect, the most significant bit of the mantissa part is omitted, so that a flag bit for identifying that the newly most significant bit is a floating point representation. It is characterized by being.

According to a sixth aspect of the present invention, in the third aspect, the changing means has a value which is level-shifted by a predetermined bit in accordance with the number of consecutive bits of the same code from the most significant bit. The change is performed.

A seventh aspect of the present invention is a data decompression device for decompressing data in which floating-point data and fixed-point data consisting of a mantissa part having a sign bit and an exponent part are mixed. If the data to be decompressed is floating-point data based on a flag bit that identifies whether the data to be displayed is in floating-point notation or fixed-point notation, a fixed-point number of a predetermined number of bits is used. Means for converting the data to display data, and, if the data to be decompressed based on the flag bit is data of fixed decimal point display, means for changing to data of a fixed point display having a predetermined number of bits. It is characterized by having.

According to an eighth aspect of the present invention, in the seventh aspect, the converting means includes an identifying means for identifying a floating-point representation based on the most significant bit of the data to be decompressed; Means for generating an inverted bit of the most significant bit based on the identification result to generate a sign bit of the data to be expanded, and means for generating mantissa data and exponent data from the data to be expanded and the code bit And means for generating the fixed-point data of the predetermined number of bits from the mantissa part data and the exponent part data.

According to a ninth aspect of the present invention, in the ninth aspect, the changing means shifts the level by a predetermined number of bits in accordance with the number of consecutive bits of the same code from the most significant bit.

According to a tenth aspect of the present invention, in any one of the seventh, eighth and ninth aspects, there is provided means for inserting a sign bit or a random number into lower bits of data generated based on the data to be decompressed. It is characterized by.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an audio DSP (Digital Signal Process) to which the present invention is applied.
FIG.

In FIG. 1, 1 is a microcomputer interface, 2 is a control register for setting various states via the microcomputer interface 1 (in the present invention, the values of Tables 16, 17 and 18 are set). 3 is D
A program RAM (which may be stored as a ROM from the beginning) for storing the operation procedure of the SP; 4 an arithmetic processing circuit for performing arithmetic and logical operations such as multiplication and addition;
Is the RAM (coefficient RAM, DA
TA RAM and the like correspond to this), 16 is an input / output data interface, 18 is a DSP control circuit for controlling a clock and the like, 17 is a data bus, which is an instruction command output from the program RAM, , And control lines output from the DSP control circuit are omitted. 20
Is a microcomputer in the main body of a data processing device or the like incorporating the DSP. Note that the basic configuration shown in this figure can be applied to the DSP 6 shown in FIG. For data to be compressed, there is a data processing device (not shown) (for example, a device that performs sound field processing of an audio signal using the audio DSP of FIG. 1), which reproduces a movie source recorded on a DVD or the like, for example. Then, the audio information is processed as a sound field, which is known as an AV amplifier.

(Embodiment 1) First, an example in which 24-bit data is compressed to 12 bits using the configuration of FIG. 1 will be described below.

Table 6 (FIG. 9) shows one of the compressions according to the first embodiment.
Here is an example. In this case, the audio DSP of FIG. 1 compresses the 24-bit data (Table 1) as follows.

(1) Determine the level of the input 24-bit data.

First, the peak level of the 24-bit data input to the audio DSP of FIG. 1 is determined. A flag bit is prepared by 1 bit. When the flag bit is 0, the fixed-point method is used. When the flag bit is 1, the floating-point method is used.
The reverse is also possible. That is, the definition of the flag may be reversed. ), As shown in Table 6, a flag corresponding to each input level is associated.

Here, the flag is set to 0 when the input level is from 0 to 2, and compression processing is performed by a fixed point method. In this way, 11 bi1 is allocated as fixed-point data. The flag is set to 0 even when the input level is from 11 to 18, and the compression processing is performed by the fixed point method.

Next, the flag of eight levels from level 3 to level 10 is set to 1 and compression processing is performed by the floating point method. In this case, since the exponent part requires 3 bits, the mantissa part is 8b
it. However, as can be seen from Table 6, since S, SN,... Always follow at the floating point, only SN is taken as data, and S is generated by inverting SN at the time of decompression. This makes the mantissa part the same as having nine bits of data.

(2) In the case of performing the compression processing by the fixed point method, the input data is converted from MSB (most significant bit) to S (Si
gnbit) continues four or more times.

That is, when looking at the data structure of the fixed-point system in which the input level is from 0 to 2, the MSB (most significant b
It), S (Signbit) is up to three consecutive,
It turns out that four or more do not continue. On the other hand, when the input signal whose input level is 11 to 18 is very small, the data changes only in the lower bit, and the upper bit is Signbi.
t will be continuous. Therefore, in the example of Table 6,
8b when S (Signbit) continues 4 or more consecutively
It is assumed to be 11-bit fixed-point data shifted to the right of it. As a result, when the input is smaller than -66 dB, it is treated as fixed point data and the level of the noise floor does not change.

The compressed data is temporarily stored in an internal or external memory (RAM) together with flag data indicating whether the data has been compressed by the fixed point method or the floating point method.

In the example of Table 6, the dynamic range is 11
S / N + D (distortion) of 4 dB, input level 0 dB is about 66
dB (corresponding to 11 bits) is obtained. Although the dynamic range is slightly lower than the dynamic range 138 dB of the floating-point method shown in Table 4, it is rarely required so far in practical use. This is for good. An example of realizing a dynamic range of 138 dB will be described later.

Table 7 (FIG. 10) shows an example of the data structure when the data is compressed by the method of Table 6 using the structure of FIG. The data of the exponent part indicates the shift amount from the MSB of the data taken in at the time of compression, and the order is not necessarily required since it is only necessary to be able to distinguish 8 bits (for example, 00
0,001, ..., 110,111).

Next, processing for expanding data compressed to 12 bits using the audio DSP of FIG. 1 will be described.

First, it is determined from the flag bit (FIG. 9) in the memory whether the compressed data is compressed by the fixed point method or the floating point method. In the case of the fixed point method, the upper 4 bits Sign are used. It is determined whether or not the flag continues, and if the upper 4-bit Sign flag continues, it is determined that the signal level is a minute signal level, and an 8-bit right shift (LSB side) operation is performed. Otherwise, no shift operation is performed.

In the case of the floating point system, the MSB data is inverted to generate a sign bit, and a necessary right shift operation is performed based on the data of the exponent part.

Regarding the lower bits in which no data after decompression exists, after the shift, the sign bit of the data (Table 8:
11) or a random number generated by an M sequence or the like (see Table 9: FIG. 12). When Signbit is inserted, suppression of offset and even-order harmonics can be expected, and when random numbers are inserted, suppression of the whole harmonics can be expected although the noise level is slightly worse. These may be switched according to the situation.

According to the present invention, it is possible to change the dynamic range and the effective bit length of data according to how to take a flag and how to take an exponent part. Some examples are given below.

(Embodiment 2) Using the configuration of FIG.
An example in which bit data is compressed to 12 bits will be described below.

Table 10 (FIG. 13) shows an example of compression according to the second embodiment. As shown in Table 10, in this example,
Using a flag of 2 bits, 01 corresponds to input level 0, 0 corresponds to input levels 1 to 3 and 12 to 19, and 11 corresponds to input levels 4 to 11. Flags 01 and 0 are of the fixed-point type, and flag 11 is of the floating-point type. The exponent part is 3 bits and indicates the shift amount of the data taken in at the time of compression from the MSB in the case of the floating point method. In the case of the fixed-point method, the input data is large input (levels 1 to 3) or small input (levels 12 to 1).
The determination as to 9) is made based on whether or not the number of consecutive Signbits from the MSB of the input data is 4 or more. That is, if the number is four or more, it is determined that the input is a minute input, and the data shifted by 9 bits from the MSB is fetched.
The shift amount of the captured data from the MSB in the case of the fixed point method is 1 bit for input levels 0 to 3, and
The input levels 12 to 19 are 9 bits.

Under the above conditions, 24-bit data can be compressed in the same manner as in the first embodiment using the audio DSP having the configuration shown in FIG. Table 11
FIG. 14 shows the data structure after compression.

In this example, the input level is 0 to -6 dB
Except for (input level 0), an effective bit length equal to or longer than that of the fixed-point method can be obtained.

The operation at the time of decompression is the same as that of the first embodiment. The value of the flag bit and the sign bit from the MSB are
Can be easily extended by referring to the continuous number of

(Embodiment 3) Using the configuration of FIG.
An example in which bit data is compressed to 12 bits will be described below.

Table 12 (FIG. 15) shows an example of compression according to the third embodiment. As shown in Table 12, in this example,
Flags 3 bits are used, 0 corresponds to input levels 0 to 1 and 14 to 22, 001 corresponds to input levels 2 to 3, 101 corresponds to input levels 4 to 5, and 11 corresponds to input levels 6 to 13. Corresponded to. Flags other than 11 are of a fixed-point type, and flags 11 are of a floating-point type. The exponent part is 3 bits and indicates the shift amount of the data taken in at the time of compression from the MSB in the case of the floating point method. When the fixed-point method is applied, the input data is large input (level 0 to 1) or small input (level 14).
To 22) is determined by the M of the input data.
The determination is performed based on whether the number of consecutive bits from SB to Signbit is 3 or more. That is, in the case of three or more, it is determined that the input is a minute input, and data shifted by 12 bits from the MSB is fetched. In addition, M of the captured data in the case of the fixed point method
The shift amount from the SB is 0 for input levels 0 to 1, 2 bits for input levels 2 to 3, input level 4
4 to 4 bits, and input levels 14 to 22 are 12 bits.

Under the above conditions, 24-bit data can be compressed in the same manner as in the first embodiment by using the audio DSP having the configuration shown in FIG. Table 13
FIG. 16 shows the data structure after compression. In this example,
Effective when the input level is 0, 1, 2, 4, and 14, while maintaining the dynamic range of 138 dB as in the case of the floating-point operation data of the exponent part 8 bits and the mantissa part 4 bits.
It can be seen that the it length has won. The operation at the time of decompression is the same as that of the first embodiment.
The extension can be easily performed by referring to the number of consecutive Signbits.

(Embodiment 4) Using the configuration of FIG.
The following describes an example in which bit data is compressed to 16 bits.

Table 14 (FIG. 17) shows an example of compression according to the fourth embodiment. As shown in Table 14, in this example,
Flag 2 bits are used, 0 corresponds to input levels 0 to 2 and 10 to 12, and 01 corresponds to input levels 3 to 5.
11 corresponds to the input levels 6 to 9 and 0
1 corresponds to the input levels 13 to 23. Flags other than 11 are of a fixed-point type, and flags 11 are of a floating-point type. The exponent part is 2 bits and indicates the shift amount of the data taken in at the time of compression from the MSB in the case of the floating point method. When the fixed-point method is applied and the flag is 0, whether the input data is a large input (from level 0 to 2) or a small input (from level 10 to 12) is determined by the input data. The determination is made based on whether the number of consecutive Signbits from the MSB is 4 or more. That is, if the number is four or more, it is determined that the input is small, and the data shifted by 7 bits from the MSB is fetched. In the case of the fixed-point method, the shift amount of the captured data from the MSB is the input level 0.
No 2 to 4 and 4bi for input levels 3 to 5
t, the input levels 13 to 23 are 10 bits.

Under the above conditions, 24-bit data can be compressed in the same manner as in the first embodiment by using the audio DSP having the configuration shown in FIG. Table 15
FIG. 18 shows the data structure after compression. When an input data format as shown in Table 15 is used, the dynamic range can be easily extended to 24 bits.
Switching of conventional 16-bit fixed data is possible by mode setting or the like.

The operation at the time of decompression is the same as that of the first embodiment. The value of the flag bit and the sign bit from the MSB are read.
Can be easily extended by referring to the continuous number of

Embodiments 1 to 4 described above can also be executed by dedicated hardware (FIG. 2) as described below.

As a specific example of the use of the present invention, there is a possibility of the new format described in the fourth embodiment. However, the most effective use is as follows. This is a case where data is compressed and written, and expanded and read.

In sound field processing using a DSP, data processing is often performed after delaying audio data, but the memory capacity at that time increases in proportion to the required delay amount. On the other hand, the delay data itself is rarely output as it is, and is often used after being processed with the original audio data or other audio data, so that the compression can be performed. At this time, if an advanced compression method such as MPEG is used, the circuit itself becomes complicated, and the compression effect cannot be obtained depending on the memory size.
The present invention is effective in such a case.

FIG. 2 shows a 96 kb audio DSP.
It shows a case in which an SRAM of "it" is mounted. The compression and decompression methods are the same as those described in the first embodiment (Tables 6 to 9). This is a DSP for 24-bit audio
6 is connected via a 24-bit data bus to a compression / decompression circuit 7 (to be described in detail later) of the present invention, and from there to a 96-bit SRAM 8. These configurations are:
For example, it is assumed that a signal to be described later, which is used by being incorporated in a data processing device such as the above-described AV amplifier, other than audio data, is generated by a control circuit in the data processing device.

The configuration of the 96 kbit SRAM 8 can be divided into four types in Table 16 according to the mode. These mode signals are input to a selector in the SRAM described later, and one of the operations is selected.

[0059]

[Table 1]

Audio data is often used in 24 bits, and is compressed by half, 12 bits.
All RAMs are 12 bits as shown in MODE1 in Table 16.
, The RAM capacity can be doubled. Depending on the data processing, it may be better to store the data in the memory as 24-bit data.
It is convenient to be able to use both 24-bit and 12-bit like ODE3. In the case of 12 bits,
CMP_N (Table 17) and S1GN_N as control signals
(Table 18) is prepared, and depending on the setting, ON / OFF of compression / expansion, Signbit at the time of expansion, and insertion of random numbers can be switched. These control signals are input to a control circuit in a compression / decompression circuit described later.

[0061]

[Table 2]

[0062]

[Table 3]

FIG. 3 shows a peripheral circuit including the compression / expansion circuit 7 of the present invention.

The peak detection circuit 9 for detecting the peak of the 24-bit data includes a DSP 6 for 24-bit audio.
In many cases, when the function is included, a portion surrounded by a dotted line becomes a configuration of a compression / expansion circuit 7.
0, left and right 15-bit barrel shifter 11 (this barrel shifter shifts to the left when compressed and shifts to the right when decompressed. Also, when it is 24 bits, the shift is 0 when CMP_N),
And a data processing circuit 12 (the data processing circuit includes a left and right 1-bit shifter, an M-sequence generation circuit, and a data selector). The barrel shifter 11 is connected to a 24-bit DBUS, and exchanges data with the outside. The barrel shifter 11 is also connected to the data processing circuit 12 via a 24-bit X bus. The data processing circuit 12 further outputs the first one of the 24-bit data.
Two bits are connected to the MBUS which is a 12-bit data bus, and the lower 12 bits are connected to the LBUS which is a 12-bit data bus. A 12-bit data SRAM is connected to the MBUS and the LBUS. 24b
In the case of the it data, it is selected that the SRAM is connected to each of the MBUS and the LBUS, and 24 bits are stored in the SRAM.
Bit data can be stored. Therefore, the SRAM 8 shown in FIG. 3 (corresponding to one in FIG. 2)
Has a memory section 8A and a selector section 8B (selects the data bus on the LSB side in response to a control signal from a control line at the time of 24 bits).

First, the circuit operation at the time of compression will be described. The peak detection circuit 9 calculates a peak detection value shown in Table 6 from the upper 16 bits of the 24-bit data bus, and sends this value to the compression / expansion circuit 7.

Control circuit 10 of compression / decompression circuit 7
Is MODE [1: 0] obtained from the control line.
When compression is performed in response to the values of (Table 16) and CMP_N (Table 17), the peak value (input level 0 to 1 in Table 6)
The value of the barrel shifter 11 is controlled so that the shift amount shown in Table 6 is obtained according to 8), and a left shift (shift to the MSB side) is performed. If compression is not performed, no shift operation is performed. In the case of compressing with floating point data and recording it in the SRAM, the SN is placed at the most significant bit, so it is necessary to shift left by 1 bit more than the shift amount shown in Table 6, but this barrel shifter 11 does not perform this operation and the next stage This is performed by the data processing circuit 12. This is because it is easier to control. The data processing circuit 12 inserts flag bits for fixed-point data, and inserts exponent part data and flag bits for floating-point data after shifting left by 1 bit.

Thus, the upper 12bi of the 24-bit data
t is written to the SRAM through MBUS [11: 0] (Table 7).

At the time of decompression, 12-bit data MBUS
[11: 0] is taken into the data processing circuit, and M
BUS [11: 8] 4 bits and MBUS [3: 0] 4
The bit is taken into the data control circuit 10. In the data control circuit 10, as shown in FIG.
If the flag of MBUS [0] is 0, it is recognized as fixed point data, and X [23: 1] is passed through the data processing circuit.
3], 11-bit data excluding the flag 1 bit (MBUS [0]) is sent to X [12: 0].
If N is 0, Signbit (ie, MBUS
[11]), if SIGN_N is 1, random number data is entered.

The control circuit 10 controls the MBUS
[11: 8] The value of 4 bits is 1111 or 0000
, It is determined to be a small signal, and the 24-bit data X [2
3: 0] is shifted right by 8 bits by the barrel shifter 11 (LS
(Shift to B side). The sign bit is inserted into the data on the MSB side that is lost due to the right shift.

The value of 4 bits of MBUS [11: 8] is 11
If it is other than 11 or 0000, it is determined that the signal has a large amplitude, and the barrel shifter 11 does not shift the 24-bit data X [23: 0].

When the flag of MBUS [0] is 1, FIG.
As indicated by B in FIG. 9, the data processing circuit 12 inverts the bit of MBUS [11] to generate a Sign bit, enters X [23: 0], and sets the signal to MBUS [l1]. : 4] 8 bit data of 1 bit
Shift right and enter X [22:15]. X [14:
0] has S1GN_N equal to 0 as in the fixed-point data.
In the case of (1), the Sign bit is entered, and when S1GN_N is 1, random number data is entered.

Further, MBUS [3:
1] is read, the right shift amount of the barrel shifter is determined from the value, and X [23: 0] is shifted. The data on the MSB side missing due to the right shift
Insert gnbit (Tables 8 and 9).

The exchange of LBUS [11: 0] is 24
It is used when reading / writing to SRAM as bit data. In that case, the selector of the SRAM unit selects the LSB side.

When processing is performed by software, the method described above may be described by a program.

[0075]

As described above, according to the present invention,
It is possible to provide a data conversion, compression, and expansion device capable of expressing a wider dynamic range with less distortion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a data compression / decompression device of the present invention.

FIG. 2 is a block diagram showing another example of the data compression / decompression device of the present invention.

FIG. 3 is a detailed block diagram of the data compression / decompression device.

FIG. 4 is a diagram showing a relationship between 24-bit data and input levels.

FIG. 5 is a diagram showing a data structure in a case where 24-bit data is compressed by a 12-bit fixed point method.

FIG. 6 is a diagram showing a data structure after compressing 24-bit data by a 12-bit fixed point method.

FIG. 7 shows a 24-bit data having a mantissa part of 8 bits and an exponent part of 4 bits.
FIG. 3 is a diagram illustrating a data structure in a case where data is compressed by a bit floating-point method.

FIG. 8 shows a 24-bit data having an 8-bit mantissa and an exponent 4
FIG. 4 is a diagram showing a data structure after compression by a bit floating-point method.

FIG. 9 is a diagram showing a data structure according to the first embodiment of the present invention.

FIG. 10 illustrates a data structure after compression according to the first embodiment.

FIG. 11 is a diagram illustrating an example of a data structure after decompression according to the first embodiment.

FIG. 12 is a diagram illustrating another example of the data structure after decompression in the first embodiment.

FIG. 13 is a diagram illustrating a data structure according to a second embodiment of the present invention.

FIG. 14 illustrates a data structure after compression according to the second embodiment.

FIG. 15 is a diagram illustrating a data structure according to a third embodiment of the present invention.

FIG. 16 is a diagram illustrating a data structure after compression according to the third embodiment.

FIG. 17 is a diagram illustrating a data structure according to a fourth embodiment of the present invention.

FIG. 18 is a diagram illustrating a data structure after compression according to the fourth embodiment.

FIG. 19 is a diagram showing X [23: 0] at the time of extension.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 4 I / O 5 bus 6 24-bit audio DSP 7 compression and expansion circuit 8 SRAM 9 peak detection circuit 10 control circuit 11 barrel shifter 12 data processing circuit

Claims (10)

[Claims] 1. A data conversion apparatus for converting floating-point representation data consisting of a mantissa part having a sign bit and an exponent part into data of a fixed-point representation, wherein the data of the mantissa part is based on the data of the exponent part. And a means for inserting the sign bit into lower bits of the level-shifted data. 2. A data conversion device for converting floating-point representation data comprising a mantissa part having a sign bit and an exponent part into data of a fixed-point representation, wherein the data of the mantissa part is based on the data of the exponent part. And a means for inserting a random number into lower-order bits of the level-shifted data. 3. A data compression apparatus for compressing data of a fixed-point representation, wherein said conversion means converts data of a predetermined range of the data of the fixed-point representation into data of a floating-point representation. Changing means for changing data other than a predetermined range of levels in the data of the fixed-point representation to data of a fixed-point representation having a predetermined number of bits; and data obtained by the conversion means and the changing means. Means for generating a flag bit for identifying whether the data is in floating-point representation or fixed-point representation. 4. The data compression device according to claim 3, wherein the most significant bit of the mantissa part of the data of the floating-point representation is omitted. 5. The data compression device according to claim 4, wherein the most significant bit of the mantissa is omitted, so that a flag bit for identifying that the new most significant bit is a floating-point representation. A data compression device, comprising: 6. The data compression apparatus according to claim 3, wherein the changing unit sets the value to a value that is level-shifted by a predetermined bit according to the number of consecutive bits of the same code from the most significant bit. A data compression device for performing a change. 7. A data decompression device for decompressing data in which floating-point data and fixed-point data consisting of a mantissa part and an exponent part having a sign bit are mixed, wherein the data to be decompressed is floating-point data. If the data to be decompressed is floating-point data, the data is converted to fixed-point data having a predetermined number of bits, based on a flag bit that identifies whether the data is to be displayed in decimal or fixed-point format. Means for performing, when the data to be expanded based on the flag bit is data of a fixed-point representation, a means for changing to data of a fixed-point representation of a predetermined number of bits, Data decompression device. 8. The data decompression device according to claim 7, wherein said conversion means includes: identification means for identifying a floating-point representation based on the most significant bit of the data to be expanded; and identification of the identification means. Means for generating a sign bit of the data to be decompressed by generating an inverted bit of the most significant bit based on the result; means for generating mantissa data and exponent data from the data to be decompressed and the sign bit Means for generating the fixed-point data having the predetermined number of bits from the mantissa part data and the exponent part data. 9. The data decompression device according to claim 7, wherein said changing means shifts the level by a predetermined number of bits in accordance with the number of consecutive bits of the same code from the most significant bit. apparatus. 10. The data decompression device according to claim 7, further comprising means for inserting a sign bit or a random number into lower bits of data generated based on the data to be decompressed. Characteristic data decompression device.