JPH02137022A - Data type converting circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of a data type conversion circuit by sharing a production means for complement of '2' and a digit carrying means and performing the mutual conversion between the floating point number and the fixed point number. CONSTITUTION:A production means 111 for complement of '2' performs a conversion process into a complement of '2' based on the code of the input data. Based on the output of the means 111, a 2nd digit shift number production means 122 produces a 2nd digit shift number for the conversion of the fixed decimal point number into the floating point number. While a 1st digit carrying number production means 121 produces a 1st digit carrying number for conversion of the floating point number into the fixed point number. A selection means 132 selects the 1st or 2nd digit carrying number. Based on this selection output, the digit carrying process is carried out for the output of the means 111 via a digit carrying means 131. At the same time, an exponent part production means 141 produces an exponent part for the floating point number based on the 2nd digit carrying number. Thus the means 111 and 131 are shared, and the mutual conversion is attained between both decimal point numbers.

Description

[Detailed Description of the Invention] [Summary] For example, regarding a data type conversion circuit in digital signal processing, the purpose of reducing the circuit scale is to convert human data into two's complement according to the sign of input data. a two's complement generation means for generating a first digit shift number when converting a floating point number into a fixed point number based on input data; and an output of the two's complement generation means. Select either a second digit shift number generation means for generating a second digit shift number when converting a fixed-point number to a floating point number based on , and a first digit shift number or a second digit shift number. digit shifting means for performing digit shifting processing on the output of the two's complement generating means based on the output of the selecting means;
and exponent part generation means for generating an exponent part of a floating point number based on the second digit shift number.

[Industrial Field of Application] The present invention relates to a data type conversion circuit in, for example, digital signal processing.

In this specification, a floating-point number consisting of a mantissa and an exponent is referred to as a floating-point number. Furthermore, a fixed-point type numerical value is called a fixed-point number.

[Conventional technology]

In devices that perform digital signal processing, both fixed-point and floating-point types are used as representation methods (data types) for numerical data.

From now on, fixed-point numerical data will be converted to FIX data.

Floating point type numerical data is called FLP data.

An apparatus using such FIX data and FLP data requires a data type conversion circuit that converts FIX data to FLP data and FLP data to FIX data.

FIG. 4(a) shows a conventional conversion circuit from FIX data to FLP data.

In Figure 4(a), the introduced FIX data is 2
The complement generation circuit 411 converts the two's complement type into the absolute value type. Based on the output data of this two's complement generation circuit 411, a priority encoder (PE) 413
The number of digit shifts when converting FIX data to FLP data is generated.

The shift circuit 412 shifts (shifts) the output data of the two's complement generation circuit 411 by the number of digit shifts to generate the mantissa part of the FLP data.
Based on the output of , the adder circuit 414 generates the exponent part of the F LP data.

FIG. 4(b) shows a conventional conversion circuit from FLP data to FIX data.

In FIG. 4, the exponent part of the FLP data is introduced into an adder circuit 422, and the mantissa part is introduced into a shift circuit 421. Based on the exponent part of the FLP data, the adder circuit 422 generates the number of digit shifts when converting FLP data to FIX data, and based on this number of digit shifts,
The mantissa part of the FLP data is shifted by the shift circuit 421 to obtain absolute value type FIX data. If the introduced FLP data is a negative number, this absolute value type FIX data is converted into a two's complement generation surface Flf! I423
FIX data can be obtained by converting to two's complement type.

[Problems to be Solved by the Invention] By the way, in the conventional method described above, the conversion from FIX data to FLP data and the conversion from FLP data to FIX data are performed by separate circuits. .

Therefore, since each conversion circuit is provided with a two's complement generation circuit and a shift circuit, there is a problem that the circuit scale is large.

The present invention was created in view of these points, and an object of the present invention is to provide a data type conversion circuit whose circuit scale is reduced.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of a data type conversion circuit of the present invention.

In the figure, two's complement generation means 111 converts input data into two's complement according to the sign of the input data.

The first digit shift number generating means 121 generates a first digit shift number when converting a floating point number into a fixed point number based on input data.

The second digit movement number generation means 122 is the two's complement generation means 11
Based on the output of 1, a second digit shift number is generated when converting a fixed point number to a floating point number.

The selection means 132 selects either the first digit movement number or the second digit movement number.

The digit shifting means 131 performs digit shifting processing on the output of the two's complement generation means 111 based on the output of the selection means 132.

The exponent part generating means 141 generates the exponent part of the floating point number based on the second digit shift number.

[For production]

Two's complement generation means 111 based on the sign of input data
The input data is converted into a two's complement number. Based on the output of the two's complement generation means 111, the second digit shift number generation means 122 generates the second digit shift number when converting a fixed point number into a floating point number.

Also, based on the input data, the first digit movement number generating means 1
21 generates the first digit shift number when converting a floating point number into a fixed point number, and the selection means 132 selects either the first digit shift number or the second digit shift number.

For example, in the case of conversion from a floating point number to a fixed point number, the selection means 132 selects the first digit shift number. On the other hand, in the case of conversion from a fixed point number to a floating point number, the selection means 132 selects the second digit shift number.

Based on the output of this selection means 132, the digit moving means 13
1 performs digit shift processing on the output of the two's complement generation means 111.

Also, based on the number of second digit movements, the exponent part generation means 141
generates the exponent part of a floating point number.

In the present invention, a floating point number introduced as input data is converted into a fixed point number by being shifted by the first digit shift number by the digit shift means 131. On the other hand, the fixed decimal point number is converted into a mantissa part of a floating point number by shifting the digits by the second digit shift number by the digit shift means 131, and the exponent part is converted by the exponent part generation means 141 based on the second digit shift number. generated.

In this way, the two's complement generating means 111 and the digit moving means 13
1 can be used to mutually convert floating point numbers and fixed point numbers.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a data type conversion circuit in one embodiment of the present invention.

Here, the correspondence relationship between the embodiment of the present invention and FIG. 1 will be shown.

The two's complement generation means 111 corresponds to the two's complement generation circuit 211.

The first digit movement number generation means 121 corresponds to the addition circuit 221.

The second digit movement number generation means 122 corresponds to a priority encoder (PE) 222.

The digit moving means 131 corresponds to the shift circuit 231.

The selection means 132 corresponds to the selector 232.

The exponent part generation means 141 corresponds to the addition circuit 241.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■-] Hikiken Noboru In FIG. 2, the data type conversion circuit according to the embodiment includes a two's complement generation circuit 211 that converts the introduced numerical data into a two's complement, and a two's complement generation circuit 211 that converts the introduced numerical data into a two's complement. An addition circuit 221 that generates a 1-digit shift number, a priority encoder (PE) 222 that generates a 2-digit shift number based on the output of the 2's complement generation circuit 211, and a 1st-digit shift number and a 2nd-digit shift number. a selector 232 for selecting one of the
and the two's complement generation circuit 2 according to the output of the selector 232.
11, and an adder circuit 241 that generates an exponent part of a floating point number based on the second digit shift number.

FIG. 3 shows an example of numerical data (32 bits).

As shown in Figure 3(a), fixed-point numerical data (FIX data) consists of a sign bit (31st bit) and a 2nd bit.
It is composed of complement type numerical data (0th bit to 30th bit).

On the other hand, as shown in Figure 3(b), floating point type numerical data (FLP data) consists of a sign bit (31st bit), an exponent part (23rd bit to 30th bit), and an absolute value type. The mantissa part (0th bit to 22nd bit) of

The adder circuit 221 in FIG. 2 has a part (23rd bit to 30th bit) corresponding to the exponent part of the FLP data of the 32-bit input data, and the 2's complement generator 211 has a part corresponding to the exponent part of the FLP data. The 0th bit to the 31st focus are introduced.

Further, a switching signal S is supplied to the selector 232 and the two's complement generation circuit 211 by a control section (not shown). This switching signal S corresponds to the data type of the input data. For example, when the switching signal S is 1", it corresponds to the case where the input data is FLP data, and on the other hand, when it is "0'°, it corresponds to the case where the input data is FLP data. This corresponds to the case where the data is FIX data.

When the switching signal S is 1'', the selector 232 selects the first
The number of digit shifts is selected, and when it is '°0°°, the second digit shift number is selected.

Further, the two's complement generation circuit 211 is configured so that the switching signal S is
“1°” means 2 for the 0th bit to the 22nd bit.
When the value is "0'', the conversion process is performed on the Oth bit to the 30th bit.

, JLl Case 4 side ■ Work Below, the operation of the data type conversion circuit according to the embodiment shown in FIG. 2 is explained as the conversion operation from FLP data to F
The operation of converting IX data to FLP data will be explained separately.

i From FLP data to FIX data When converting FLP data to FIX data,
The above-mentioned switching signal S is ``''l''°.

At this time, the two's complement generation circuit 211 refers to the sign bit of the input data, and if it is a negative number, converts the mantissa part (0th bit to 22nd bit) of the input data into a two's complement number.

On the other hand, the adder circuit 221 adds the exponent part (the 23rd
The first digit shift number is generated by adding a predetermined numerical value to the bits (bit to 30th bit).

Since the switching signal S is "1", the selector 232 selects this first digit shift number and supplies it to the shift circuit 231.

The shift circuit 231 shifts the output of the two's complement generation circuit 211 by the number of first digit shifts and outputs it as the Oth bit to the 30th bit of the FIX data.

In this way, after the 2's complement generation circuit 211 converts the mantissa part of the input data into a 2's complement, the shift circuit 231 shifts it by the number of first digit shifts. Just like circuits, FLP data can be converted to FIX data.

1i Operation from FIX"-"- to FLP data When converting FIX data to FLP data, the switching signal S is 0°'.

At this time, in the two's complement generation circuit 211, based on the sign bit of the input data, if the number is negative,
The 0th to 30th bits are converted into two's complement numbers and converted into absolute value type.

The PE 222 first detects the most significant bit that is not 0'0' from the bit string output from the 2's complement generation circuit 211. Next, the PE 222 generates a second digit shift number such that the most significant bit that is not '0'' becomes the most significant bit (for example, the 22nd bit) of the mantissa part of the FLP data.

Since the switching signal S is “O++,” this second digit shift number is selected by the selector 232 and supplied to the shift circuit 231.

The shift circuit 231 shifts the output of the two's complement generation circuit 211 by the number of second digit shifts, and the 0th to 22nd bits as a result of this shift are output as the mantissa part of the FLP data.

On the other hand, the adder circuit 241 adds a predetermined number to the output of the PE 222 to generate an exponent part of the FLP data.

■ Stop of - As mentioned above, the selector 232
selects either the first digit movement number or the second digit movement number. Further, the shift circuit 231 shifts the result of the conversion process into a two's complement number by the two's complement generation circuit 211 according to the output of the selector 232.

In this way, whether the input data is FIX data or
By switching the operation of the circuit based on whether the data is LP data or not, it is possible to mutually convert FLP data and FIx data.

This makes it possible to share the two's complement generation circuit and the shift circuit, which were duplicated in the conventional system, so that the circuit scale can be reduced.

For example, when the numerical data has a configuration as shown in FIG. 3, the circuit size of the embodiment is approximately two-thirds that of the conventional circuit.

Note that in the embodiment of the present invention described above, a case was considered in which the data type was mutually converted between a 32-bit floating point number and a fixed point number, but the number of bits of numerical data There are no restrictions. Furthermore, the number of bits allocated to the exponent and mantissa parts of a floating point number is not limited.

Furthermore, in "correspondence between rI, Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been explained, those skilled in the art can easily imagine that the present invention is not limited to this and that there are various modifications. .

〔Effect of the invention〕

As described above, according to the present invention, it is possible to mutually convert floating point numbers and fixed point numbers by sharing the two's complement generating means and the digit shifting means, thereby reducing the circuit scale. This is very useful in practical terms.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a data type conversion circuit according to the present invention, Fig. 2 is a configuration diagram of a data type conversion circuit according to an embodiment of the present invention, Fig. 3 is a diagram showing an example of numerical data, and Fig. 4 is an explanatory diagram of a conventional data type conversion circuit. E), 231, 412 and 421 are shift circuits, and 232 is a selector. In the figure, 111 is a two's complement generation means, 121 is a first digit movement number generation means, 122 is a second digit movement number generation means, 131 is a digit movement means, 132 is a selection means, 141 is an exponent part generation means, 211 .411, 423 are two's complement generation circuits, 221.
241,414.422 is an adder circuit, 222.413 is a priority encoder (P(a) (b) 1.1 □□□ Lecture on the third example

Claims (1)

[Claims] (1) Two's complement generation means (
111), first digit shift number generation means (121) for generating a first digit shift number when converting a floating point number into a fixed point number based on the input data, and the two's complement generation means (111); 111), a second digit shift number generating means (122) that generates a second digit shift number when converting a fixed point number to a floating point number; a selection means (132) for selecting either one of the number of digit movements and a digit movement number; and a digit movement means (132) for performing digit movement processing on the output of the two's complement generation means (111) based on the output of the selection means (132). 131); and exponent part generation means (141) for generating an exponent part of a floating point number based on the second digit shift number.