JPH0448327A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To attain an arithmetic operation at a high speed by controlling the decimal carry with only a carry signal received from a 4-bit arithmetic and logic unit and corresponding to a hexadecimal number when the decimal data expressed in a form of a complement of 10 into the decimal data expressed in the absolute value. CONSTITUTION:A 4-bit arithmetic and logic unit ALU 1 is provided together with an inverter INV, and a +10 adder circuit ADD. In such a constitution, the decimal carry can be controlled with only a carry signal received from the ALU 1 and corresponding to a hexadecimal number when the ALU 1 carries out the addition processing in order to convert the decimal data expressed in a form of a complement of 10 into the decimal data expressed in the absolute value. Thus the computing speed is extremely increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to an arithmetic device that performs decimal arithmetic using a plurality of 4-bit arithmetic units provided corresponding to each digit of a decimal number.

[Summary of the Invention] This invention corrects the data to be added when performing an addition process using a 4-bit arithmetic unit to convert lO base number data expressed in 10's complement format to decimal number data expressed in absolute value. By inputting a hexadecimal number, a carry signal corresponding to a hexadecimal number is always obtained from a 4-bit arithmetic unit when the addition result of the original addition target data is 10 or more. This is an environment in which decimal carry can be controlled with , and high-speed calculations have been achieved.

[Prior art] When performing calculations on multiple digits of lO-base data expressed in binary coded decimal numbers, multiple 4-bit calculation units corresponding to each digit are used. The subtraction result is output in the form of 10's complement.

For example, when subtracting "30-60", 1
An operation result of "70" expressed in zero's complement form is obtained. However, since the complement representation is difficult for the user to understand, the above calculation result is converted to the normal form, that is, '30'' and 60°.

A negative sign may be added to '30'' which is the difference (absolute value) between the two and output.

By the way, the conversion to the absolute value is realized by adding "1" to the 9's complement of the arithmetic result expressed in the form of the 10's complement. In other words, in the above example, adding "1" to "29", which is the nine's complement of "70", gives 30°
The absolute value is obtained.

However, this addition process (addition process of decimal numbers) is
When using a bit arithmetic unit, it is necessary to perform a carry when the addition result of each digit is 10 or more, but the above 4-bit arithmetic unit carries only when the addition result is 16 or more. Generate a signal. Therefore, it is necessary to determine whether the addition result by the 4-bit arithmetic unit is 10 or more, and if it is 10 or more, to generate a carry signal again, and it takes time to generate the necessary carry signal. Compared to the case of adding base data, the calculation speed is lower and the circuit is more complicated.

[Problem to be Solved by the Invention] As mentioned above, this problem cannot be solved with only the carry signal corresponding to hexadecimal numbers from the 4-bit arithmetic unit, and it is necessary to generate another carry signal corresponding to decimal numbers. to cause.

As a result of various studies, we found that if we add "6" to the 9's complement in advance and then add "1", the result of adding the 9's complement, which is the original data to be added, and the "1" becomes 10 or more. In this case, a carry signal will always be output, and 4
I got the idea that it would be possible to deal with only the carry signal corresponding to hexadecimal numbers from the bit arithmetic unit, and
Since adding "6" is equivalent to finding a 1's complement number obtained by simply inverting each bit, it was predicted that the circuit for adding "6" would be simple.

The problem of this invention is to convert the hexadecimal number from the 4-bit arithmetic unit into a 4-bit arithmetic unit when performing an addition process to convert decimal data expressed in 10's complement format into decimal data expressed in absolute value. The purpose is to enable decimal carry to be controlled using only the corresponding carry signal.

[Means to solve the problem] The means of this invention are as follows.

This arithmetic unit has a plurality of 4-bit arithmetic units provided corresponding to each digit of a decimal number, and propagates the carry signal generated by each 4-bit arithmetic unit to the 4-bit arithmetic unit corresponding to the upper digit. It also performs decimal arithmetic, and is equipped with the following circuit.

(1) Correction circuit: When converting decimal data expressed in 10's complement format to decimal data expressed in absolute value, the above 1.
The 4-bit data components corresponding to each digit of decimal data expressed in 0's complement format are inverted and corrected.

(2) Output time R: The 4-bit correction data of “0°°” and the corresponding digit corrected by the correction circuit are input to each of the 4-bit arithmetic units, and then the 4-bit correction data corresponding to the 1st digit is input. When a carry signal is input to a 4-bit arithmetic unit and an addition instruction is issued, for the digit for which a carry signal is generated by addition processing based on this addition instruction, the value of the addition result is output, and the carry signal is For digits where no signal is generated, a value obtained by subtracting "6" from the addition result is output.

[Work] The operation of the means of this invention is as follows.

For example, assume that the calculation result "70" expressed in 10's complement form is converted into absolute value expression.

In this case, the correction circuit outputs "0" in the first digit of "70",
The digit "7", that is, "0000" and "0111" are respectively inverted and corrected as "1]11" and "1000".

The first digit correction data “1111” corrected in this way
, the second digit correction data "1000" are respectively input to the 4-bit arithmetic unit of the corresponding digit.

Furthermore, "0000" is input to each of the 4-bit arithmetic units corresponding to the first and second digits as the other data to be added. Then, a carry signal is further input to the 4-bit arithmetic unit corresponding to the first digit to instruct addition processing.

Output circuit 4'' When the addition process is executed based on this instruction, the value of the addition result is output for the digit where a carry signal was generated, and the value of the addition result is output for the digit where a carry signal was not generated. Outputs the value obtained by subtracting "6'' from

For example, in the above example, in the 1st digit 4-bit arithmetic unit, the data to be added are (1], 1 ], ), (000
In addition to 0), a carry signal was input, so (<11
11)+(0000)+"]") addition processing is performed. In this case, logically the addition result is (10000
), but since a 4-bit arithmetic unit can only obtain arithmetic results up to 4 bits, a carry signal is generated based on the 5th bit "1", resulting in a bit content of <0000).

In this way, when a carry signal is generated, it matches the first digit of ``30'', which is the conversion result when ``70'' expressed in 10's complement form is converted to absolute value expression. Therefore, Operation result of 4-bit arithmetic unit corresponding to 1st digit <00
00) is output as is.

In the above example, in addition to the addition target data (1000) and (0000), the carry signal generated by the 4-bit arithmetic unit in the first digit is input to the 4-bit arithmetic unit in the second digit. + <1000>+ (0000) + "'1") is performed. In this case, the addition result is 1001)
Since it is 9" which is less than 16 which can be expressed with 4 bits, no carry signal is output.

At this time, the calculation result of the 4-bit arithmetic unit is °“9′
is larger by 6 degrees than the second digit 3' degrees of 30, which is the conversion result when converting 70 to absolute value representation. Therefore, the output circuit is
By subtracting "6" from °'9", which is the operation result of the bit arithmetic unit, we obtain the logically correct °'3", that is, (001
1) is output as the second digit conversion result.

Therefore, when a 4-bit arithmetic unit performs addition processing to convert decimal data expressed in 10's complement format to decimal data expressed in absolute value, a carry signal corresponding to a hexadecimal number from the 4-bit arithmetic unit is required. You can control decimal carry with just

[Example] Hereinafter, an example will be described with reference to FIGS. 1 to 5.

FIG. 1 is a block configuration diagram of an arithmetic device according to a first embodiment.

This arithmetic device has four 4-bit arithmetic units ALU1, and each 4-bit arithmetic unit ALUI is connected to an inversion circuit INV and a +10 addition circuit BADD, respectively.

This arithmetic unit performs various arithmetic operations such as addition, subtraction, multiplication, and division on decimal data expressed in binary coded decimal code (BCD code) based on instructions from C P [J, etc. (not shown) Each 4-bit
The node operator A L L, + 1 has a one-to-one correspondence with each digit of the decimal number data to be operated on.9 In other words, the decimal number data is divided into four bib ■ - data components corresponding to each digit. divided into corresponding 4-bit arithmetic units AL[
J] are distributed and input.

Note that when converting decimal data expressed in 10's complement format to decimal data expressed in absolute value, each digit of the decimal data expressed in 10's complement format, which is the target of conversion, is converted into a corresponding digit. After being inverted by the inverting circuit INV, the signal is input to the 4-bit arithmetic unit ALU1 of the corresponding digit. in this case,
“°0” is commonly input to each 4-bit arithmetic unit ALU1 as the other data to be calculated. Then, the carry signal is input only to the 4-bit arithmetic unit ALU1 corresponding to the first digit, and an addition command is given.

The above reversal processing has the following significance.

In other words, the above conversion to absolute value expression is achieved by adding "1" to the 9's complement of the data to be converted (decimal number), but when performing this decimal addition, if the addition result is 10 or more, If so, be sure to use 4-bit arithmetic unit AL
This is performed as preprocessing so that a hexadecimal carry signal is generated from U1 so that decimal carry can be performed only with the hexadecimal carry signal.

In other words, in order to ensure that a carry signal corresponding to a hexadecimal number is generated from the 4-bit arithmetic unit ALU1 when the addition result is 10 or more, the difference in the radix between the hexadecimal system and the decimal system must be This can be achieved by adding ``6'' to the data to be added in advance, but adding ``6'' to the above 9's complement is nothing but finding the complement of ``1'', so this ``1'' We decided to perform inversion processing to find the complement of , and essentially add 6'' to the complement of 9.

As a result of the +10 addition circuit ADD performing addition processing using the 9's complement number increased by +6, in the digit where no carry signal is generated, the addition result by the 4-bit arithmetic unit ALU1 is only °°6"° higher than the logical operation value. Therefore, if a carry signal is not generated, a circuit that adds °10" ° (equivalent to subtracting '°6" in hexadecimal) to the addition result in 4-bit arithmetic unit ALU1 and corrects it correctly. It is.

This +10 addition circuit ADD outputs the addition result of the 4-bit arithmetic unit ALU1 as is when a carry signal is generated.

Note that when calculating decimal data of 54 digits or more, four 4-bit calculating units ALU1 etc. are used cyclically.9For example, when calculating 8-digit decimal data, the first to fourth digits are The calculations up to the 4-bit calculation unit ALUI for the corresponding digit are performed, and then the calculations for the 5th, 6th, and 7th digits are performed.
The operations on the digits and the 8th digit are performed by the 4-bit arithmetic units ALUI on the 1st, 2nd, 3rd, and 4th digits, respectively. In this case, the carry signal generated in the 4-bit arithmetic unit ALU1 of the 4th digit when performing the calculation from the 1st to the 4th digit is The data is input to the 4-bit arithmetic unit ALU1 corresponding to the first digit to be calculated.

Next, the conversion operation to absolute value representation will be explained using a specific example.

For example, the decimal data "9" expressed in 10's complement format is
778” as decimal data “’02” in absolute value representation.
When converting to 22", each number of digits "9'° "'7""7" and "8" of '9778' to be converted is input to the inversion port 1INV of the corresponding digit and inverted, '6' is the inversion result.

"8°, 8"°'7° are respectively input to the 4-bit arithmetic unit ALUI of the corresponding digit (see FIG. 2).

In this case, °'ooo'' is commonly input to each 4-bit arithmetic unit ALLJ1 as the other calculation data, and 1
A carry signal is also input to the 4-bit arithmetic unit ALU1 of the digit. When an addition command is given, the 4-bit arithmetic unit ALU1 in the first digit handles 1'' in addition to the above input data as addition target data based on the input carry signal (see Figure 2). ), as a result, the addition results in each 4-bit arithmetic unit ALU1 are ``
6", '8", "8", "'8" (Fig. 2■
reference).

In this case, since each addition result is all 16 or less, none of the 4-bit arithmetic units ALU1 generates a carry signal, and the above addition result is a logically correct conversion result."02
Compared to 22'', it is larger by +6 correction.

Therefore, the ``-10 addition circuit ADD corresponding to each digit adds ``10'' to the above addition result to effectively re-correct by -6 (see Figure 2 ■), and the re-correction result is ``'0.
", "2", ", "2" are output as absolute value expression data (see Figure 2 ■) In this way, decimal carry is executed based only on the carry signal from the 4-bit arithmetic unit ALUI. Therefore, as in the past, even if a carry signal is not generated, it is checked each time whether the addition result in each 4-bit arithmetic unit ALU1 is 10 or more.
In the above case, there is no need to generate another carry signal again, and the calculation speed can be increased.

Furthermore, the purpose can be achieved simply by adding an inverter for inverting input, and there is almost no effect on cost.

Next, a second embodiment will be described with reference to FIGS. 3 to 5.

FIG. 3 is a block diagram of the arithmetic device according to the second embodiment. The configuration and functions of this second embodiment have many parts in common with the first embodiment, so only the differences will be briefly explained.

The difference from the first embodiment is that each 4-bit arithmetic unit ALU2
has a carry lookahead function, and the carry generation circuit 3
are provided, and high-speed carry is performed by these.

That is, each 4-bit arithmetic unit ALU2 has a carry look-ahead section LAC consisting of a gate array as shown in FIG. The carry lookahead unit LAC generates a signal G and a signal P based on the two input data to be added, and outputs them to the carry generation circuit 3. The output of these signals is
Each digit is performed at the same time. Here, the signal G indicates a carry when a carry signal is generated simply by adding the data to be operated on even if there is no carry signal from the lower digit, and is called a generated carry. Further, the signal P corresponds to the case where a carry signal is generated when there is a carry signal from a lower digit.

The carry generation circuit B3 is composed of a gate array as shown in FIG.
Carry signals C1 to C4 for each digit are generated based on the signal G, signal P, etc. from the look-ahead unit LAC for the upper digit number, respectively.
It is output to the +10 adder circuit ADD2 of the corresponding digit. That is, as is clear from Fig. 5, C1=GO+PO-CO- (1) C2
=G1+Pl・C1−・・・・・・・(2)C3=G
2+P2・C2・・・・・・・・・(3)C4=G3+
P3・C3-...It is determined by the logical formula (4). "'PO・CO°'PaP1・C]Pa' in each formula
P2.C2"P3.C3" indicates a carry performed when there is a carry signal from a lower digit, and is called a propagation carry.

These carry signals C1 to C4 are also generated and output at the same time. That is, the carry signals C2 to C4 for the second and subsequent digits are also generated simultaneously with the carry signal C1 for the first digit.

Therefore, the addition results for the second and subsequent digits are determined at the same time as the addition results for the first digit, and there is no need to determine them sequentially as in the case of the first embodiment, further speeding up the process. be done.

The present invention is not limited to the above-mentioned embodiments, but can also be applied to, for example, an arithmetic device equipped with four or more 4-bit arithmetic units.

"Effects of the Invention" According to the present invention, when performing addition processing for converting decimal data expressed in 10's complement form into decimal data expressed in absolute value form using a 4-bit arithmetic unit, 4-bit operation is possible. Decimal carry can be controlled without a carry signal corresponding to hexadecimal numbers from the device, making it possible to greatly increase calculation speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first embodiment, Fig. 2 is a diagram specifically explaining the addition operation, Fig. 3 is a block diagram of the second embodiment, and Fig. 1 is a block diagram of the first embodiment. 3 is a block diagram of the carry lookahead section in FIG. 3, and FIG. 5 is a block diagram of the carry generation circuit in FIG. 3. ALU 1. ALU2...4-bit arithmetic unit, NV...inversion circuit, ADD...+10 addition circuit.

Claims (1)

[Scope of Claims] A plurality of 4-bit arithmetic units are provided corresponding to each digit of a decimal number, and a carry signal generated by each 4-bit arithmetic unit is propagated to a 4-bit arithmetic unit corresponding to an upper digit. When converting decimal data expressed in 10's complement format to decimal data expressed in absolute value in an arithmetic device that performs decimal arithmetic, the above 1.
a correction circuit that respectively inverts and corrects 4-bit data components corresponding to each digit of decimal data expressed in 0's complement format; and a 0 in each of the 4-bit arithmetic units, and the correction circuit. When the 4-bit corrected data of the corresponding digit corrected by For the digits for which a carry signal is generated by addition processing based on , the value of the addition result is output,
An arithmetic device comprising: an output circuit that outputs a value obtained by subtracting "6" from the addition result for digits for which no carry signal is generated.