JP3591451B2 - Data processing device and data processing method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data processing device and a data processing method such as a digital compressor / limiter and an audio signal effect device (effector) for compressing or expanding a level value of an audio signal or a tone signal based on a non-linear gain characteristic.
[0002]
[Prior art]
Conventionally, compressor (compression) processing is performed when large amplitude is input to prevent overmodulation of broadcasting equipment, and small amplitude signals are extracted in digital compressors / limiters that perform limiter processing and music playback under background noise. 2. Description of the Related Art A data processing device that performs non-linear gain control according to an input signal level, such as an expander / noise gate that suppresses low-level noise while performing panda (expansion) processing, is known. FIG. 13 shows an example of input / output characteristics of this type of data processing device. In this figure, the horizontal axis is the logarithmic level of the input data value, the vertical axis is the logarithmic level of the signal after passing through the system, and the dotted line is the input / output relationship line when no compression / decompression is performed. FIG. 14 also shows the gain (multiplication coefficient) with respect to the input data value. FIG. 14 (a) shows the logarithmic gain and FIG. 14 (b) shows the linear multiplication coefficient.
[0003]
With this input / output characteristic, the gain of the system changes as follows according to the level of the input. (1) When a signal of an intermediate level (−24 to −84 dB) is input, the input / output gain is set to +12 dB to increase the volume. (2) When a signal of a high level (−24 dB or more) is input, a compression operation with an expansion rate of （(compression rate of 2) is started to prevent clipping with a large amplitude. (3) When a low-level signal (−84 dB or less) is input, the expansion operation is performed at an expansion rate of 2, but low-level noise when there is no signal is suppressed.
Conventionally, in order to obtain such non-linear gain characteristics, the characteristics are previously stored in a memory as gain data, the gain data is read from the memory in accordance with the amplitude level of the input data, and the read gain data is input. Multiplying data to generate output data has been performed.
[0004]
[Problems to be solved by the invention]
By the way, in a data processing device such as a mixer that applies various effects to a plurality of input data and mixes and outputs them, each data obtained by applying an effect to each input data by the above-described method is used. May be mixed to generate desired output data.
In such a data processing apparatus, if an attempt is made to provide desired gain characteristics to input data, the amount of gain data increases, and it is necessary to use a large-capacity memory. In particular, when trying to give different gain characteristics to a plurality of input data, the amount of gain data increases as the number of input data increases. On the other hand, depending on the type of input data, the required degree of gain characteristic accuracy may be different. For example, it is conceivable that the master-level compressor after mixing has a more accurate gain characteristic than the input-stage compressor inside the mixer.
[0005]
The present invention has been made in view of the above points, and an object of the present invention is to expand the degree of freedom of gain characteristics to be provided and increase the versatility of a data processing device under a fixed storage capacity. .
[0006]
[Means for Solving the Problems]
In order to solve the above problem, according to the invention described in claim 1, in a data processing device for giving various gain characteristics to input data, the data processing device is determined according to a processing mode indicating the accuracy of gain characteristics to be given. A data separation unit that separates higher-order bit data from control data obtained by performing predetermined processing on the input data according to the number of separated bits, and stores each gain data in each of the divided storage areas according to the processing mode. A storage unit for storing in advance, a read address generation unit for performing a process according to the processing mode on the upper bit data to generate a read address, and a gain address read from the storage unit based on the read address. And a data generator for performing a gain process on the input data to generate output data.
[0007]
According to the second aspect of the present invention, there is provided an amplitude data generating section for detecting an amplitude of an input signal based on the input data and generating amplitude data, and the amplitude data is given as the control data. It is characterized by the following.
In the invention according to claim 3, each of the gain data indicates a different gain characteristic.
[0008]
Further, in the invention according to claim 4, the data separation section separates the control data into the upper bit data and the lower bit data, and the data generation section reads the gain data read from the storage section. An interpolation unit that performs interpolation processing based on the lower-order bit data to generate interpolation gain data; anda multiplication unit that generates the output data by multiplying the interpolation gain data by the input data. Features.
[0009]
Further, in the invention according to claim 5, the read address generation unit generates an address indicating each storage area according to the processing mode, and combines the address with the upper bit data to generate the address. A read address is generated.
According to the invention described in claim 6, in a data processing method for assigning various gain characteristics to input data based on gain data stored in a rewritable storage unit, a gain characteristic to be assigned is provided. The storage area of the storage unit is divided according to a processing mode indicating accuracy, each gain data is stored in each divided storage area, and according to the number of separation bits determined according to the processing mode, from the control data. The upper bit data is separated, a read address is generated by performing processing according to the processing mode on the upper bit data, and based on the gain data read from the storage unit based on the read address, the input data is The output data is generated by performing a gain process.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
<1. Configuration of Embodiment>
<1-1: Overview of data processing device>
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a main configuration of a data processing device according to one embodiment of the present invention. This device includes an absolute value generation circuit 1, a logarithmic conversion circuit 2, a peak hold / time attenuation circuit 3, a data separation circuit 4, a gain table 5, a data interpolation circuit 6, a logarithmic inverse conversion circuit 7, a multiplication circuit 8, and a control circuit 9 It has.
[0011]
The input data Din of this device is a data string of a two's complement code and a 32-bit parallel format, and is supplied in synchronization with the reference clock signal CKref. The reference clock signal CKref is supplied from a clock signal generation circuit (not shown). The frequency is set to 256 fs when the sampling frequency of the music signal is fs. This device can process a maximum of 256 input data Din per sampling period.
[0012]
Further, in this device, gain characteristics can be given with a plurality of types of accuracy. In the following description, those modes are referred to as modes. The mode is automatically set by the control circuit 9 or set by an operator's instruction input. The control circuit 9 generates the mode signal Sm and various control signals. The mode signal Sm indicates the mode and specifies each page constituting the RAM 52 described later. Note that a page is a unit of each storage area obtained by dividing the RAM 52 constituting the gain table 5. Here, the number of modes is arbitrary, but in this example, it is assumed that the first mode to the third mode are prepared. The accuracy of the gain characteristic in the first mode is set to be low, the accuracy of the second mode is normal, and the accuracy of the third mode is set to be high.
[0013]
The mode signal Sm is 4-bit data. The upper two bits of the mode signal Sm indicate the mode. When the data value is "00", the first mode is set. When the data value is "01", the second mode is set. At 10 ", the third mode is designated. On the other hand, the lower two bits of the mode signal Sm indicate a page of the RAM 52. As described later, the RAM 52 is divided and used according to the mode. The number of divided pages is 4 in the first mode, the number of divided pages is 2 in the second mode, and the entire RAM 52 is used as one page without division in the third mode (see FIG. 8).
[0014]
First, when the upper two bits of the mode signal Sm are “00” (first mode), the first page is set when the lower two bits are “00”, and the second page is set when the lower two bits are “01”. The page indicates the third page when the lower two bits are "10", and the fourth page when the lower two bits are "11". Next, when the upper two bits of the mode signal Sm are “01” (second mode), the first page is set when the lower two bits are “00”, and the first page is set when the lower two bits are “01”. Specify each of the two pages. Next, when the upper two bits of the mode signal Sm are “10” (third mode), the lower two bits are uniquely “00”, and the entire RAM 52 is designated as one page.
[0015]
FIG. 2 is a timing chart showing an example of the relationship between the input data Din and the mode signal Sm. As shown in this figure, the data D1, D2,..., D256 and the mode signals Sm1 to Sm256 are synchronized with the reference clock signal CKref. The mode signal Sm1 corresponding to the data D1 is "0001". In this case, since the upper two bits of the mode signal Sm1 are "00", the data D1 is processed according to the first mode, and the lower two bits are "01", so that the second page is designated.
[0016]
<1-2: Control circuit>
First, the control circuit 9 generates various control signals for controlling the entire data processing device. FIG. 3 is a block diagram illustrating a main part of the control circuit 9. As shown in the figure, the control circuit 9 includes a program RAM 90 and an address counter 91. The program RAM 90 has 256 storage areas designated by addresses 0 to 255. Each of the storage areas has a mode signal Sm, a hold data HD for designating a hold time T1, and a second data for designating a first decay rate R1. A set of one attenuation rate data GDx, second attenuation rate data GDy indicating the second attenuation rate R2, and level switching data LD indicating the attenuation switching level L1 is stored. The hold time T1, the first decay rate R1, the second decay rate R2, and the decay switching level L1 are parameters of characteristics given to the input data Din in the peak hold / time decay circuit 3, which will be described later. Will be described later.
[0017]
These data are supplied from the outside, and when the data processing device is incorporated in a mixer and used, these data are loaded from a CPU that controls the entire mixer. . For example, when the user operates the operator of the mixer, the CPU detects this and generates a data set whose data value is changed according to the operation amount, and loads the data set into the program RAM 90. Therefore, the parameter of the characteristic given to the input data Din can be dynamically changed.
[0018]
The data set stored in the program RAM 90 is read according to the count value of the address counter 91. The address counter 91 is constituted by an 8-bit ring counter, and generates an address by counting the reference clock signal CKref. Therefore, the data sets stored in the program RAM 90 are sequentially read from address 0. Then, after the data set at the address 255 is read, returning to the address 0, the data set is read, and this is repeated. As described above, since the frequency of the reference clock signal CKref is 256 fs, it is possible to perform individual processing on each of the data D1 to D256 constituting the input data Din for one sampling period.
[0019]
<1-3: Absolute value generation circuit>
Next, the absolute value generation circuit 1 generates an absolute value of the input data Din. FIG. 4 is a block diagram illustrating a configuration example of the absolute value generation circuit. As shown in this drawing, the absolute value generation circuit 1 outputs 31 exclusive ORs of the most significant bit (MSB) B31 of the 32-bit input data Din and the other bits B0 to B30. If the input data Din is a positive value [if MSB (B63) = 0], B62 to B0 are output as they are, and the input data Din is a negative value. In a certain case [when MSB (B31) = 1], B30 to B0 are inverted and output, and MSB (Q31) is fixed to 0, thereby generating 32-bit absolute value data Dz.
[0020]
<1-4: Logarithmic conversion circuit>
Next, the logarithmic conversion circuit 2 shown in FIG. 1 is configured by a well-known circuit combining a selector and an OR gate, and converts 32-bit linear absolute value data Dz to 12-bit instantaneous logarithmic data DL. The logarithmic conversion circuit 2 is used for compressing the bit width of the data to reduce the circuit scale of the subsequent-stage peak hold / time attenuating circuit 3, gain table 5, data interpolation circuit 6, and the like, and to shorten the operation time thereof. Can be
[0021]
<1-5: Peak hold / time attenuation circuit>
Next, the 12-bit instantaneous logarithmic data DL is input to the peak hold / time attenuation circuit 3. The peak hold / time attenuating circuit 3 obtains a rough logarithmic envelope by subjecting the input instantaneous logarithmic data DL to peak holding and temporal attenuation processing, and obtains 12-bit envelope data De (amplitude data). Output.
[0022]
In this circuit, an approximate logarithmic envelope with peak hold / time attenuation shown in FIG. 9C is obtained. The “follow-up section” in the figure is a section where the envelope data increases as the level of the input sample value increases. The “hold section” is a section where the sample value of the signal decreases or takes a low value, but the envelope data keeps the previous value. This time is determined by a parameter (hold time T1) provided from the control circuit 9. In the “hold section”, since the envelope data is not updated unless the input newly exceeds the hold level, the valleys of the sine wave are masked. When the input newly exceeds the hold level, the envelope data is updated, and the “hold section” starts again from that point. Therefore, it can be said that the “follow-up section” is a section in which the output data is updated for each sample.
[0023]
When the “hold section” ends, the operation enters the “automatic decay section”. Here, this section is divided into two sections, “automatic decay section 1” and “automatic decay section 2”. Both are divided depending on whether the log level code is larger or smaller than a parameter (attenuation switching level L1) provided from the outside, and have different attenuation rates R1 and R2 in each section. These attenuation rates R1 and R2 are parameters provided from the control circuit 9. As described above, by using a signal in which the attenuation time constant and the like are adjusted instead of the accurate envelope of the instantaneous logarithmic data, a so-called breathing phenomenon in the compressor / limiter (noise or background sound in small increments according to signal fluctuations). (The unpleasant phenomenon of fluctuating the level of breathing and feeling breathing) can be effectively suppressed. Having an appropriate “hold section” is effective in preventing “breathing phenomena”, and switching the attenuation rate according to the signal level involves compression operation at a high signal level and expansion operation at a low signal level. This is because the appropriate attenuation rate differs in terms of hearing.
[0024]
FIG. 5 is a block diagram showing a specific configuration example of the peak hold / time attenuating circuit 3. The instantaneous log data DL is input to the down counter 31 and also to the comparator 32. The down counter 31 loads the input data in synchronization with the clock CK1 passing through the AND gate 33 based on the output of the comparator 32 indicating that the newly input data has exceeded the current output data. When the input data is smaller than the output data, the output of the comparator 32 becomes 0, so that the peak value is held in the down counter 31 and the input data has no effect.
[0025]
On the other hand, at the same time that the down counter 31 is loaded with new input data, the down counter 34 is also loaded with the preset hold time T1. The down counter 34 counts down by the clock CK2, and sets the output Z to 1 after counting down for the hold time T1. Thereby, one condition that the clock CK2 is input as the clock of the down counter 31 via the AND gate 35 is satisfied. The Z output is a signal for inhibiting countdown by the hold time T1 after the down counter 31 is updated with a new input.
[0026]
Another condition that the clock CK2 is input to the down counter 31 is an output of the frequency divider 38. That is, the output of the down counter 31 is compared with the attenuation switching level L1 in the comparator 36. The comparison output becomes the switching input signal SB of the selector 37. The selector 37 selectively outputs the attenuation rate R1 when the switching input signal SB is 0 (output> L1), and selectively outputs the attenuation rate R2 when the switching input signal SB is 1 (output <L1). The output of the selector 37 is supplied as the frequency division number N of the programmable frequency divider 38. The frequency divider 38 divides the frequency of the clock CK2 by N and outputs a clock having an N clock cycle to C. Therefore, a pulse having a cycle determined by the decay rate R1 or R2 is supplied from the AND gate 35 to the down counter 31, and the down counter speed of the down counter 31 changes in two stages. Then, the output data of the down counter 31 is output to the data separation circuit 4 as 12-bit envelope data De.
[0027]
The envelope data De indicates the amplitude level of the input data Din. Based on this, the gain characteristic finally given to the input data Din is controlled. In this sense, the envelope data De functions as control data for controlling the gain characteristics.
[0028]
<1-6: Data separation circuit>
Next, the data separation circuit 4 shown in FIG. 1 separates the 12-bit envelope data De into upper bit data Dx and lower bit data Dy based on the mode signal Sm.
[0029]
More specifically, the number of bits for separating the upper and lower bits from the most significant bit MSB of the envelope data De is predetermined according to the data value of the mode signal Sm. The separation circuit 4 operates according to this.
[0030]
FIG. 6 is a diagram illustrating an example of a separation mode according to a mode in the present embodiment. For example, when the data value of the upper two bits of the mode signal Sm is “00” and the first mode, as shown in FIG. 11A, the uppermost bit MSB to the fourth bit of the envelope data De are higher. Bit data Dx, and the remaining 8 bits become lower bit data Dy. When the data value of the upper two bits of the mode signal Sm is "01" and the mode is the second mode, as shown in FIG. 3B, the uppermost bit MSB to the fifth bit of the envelope data De are higher. Bit data Dx, and the remaining 7 bits become lower bit data Dy. Further, when the data value of the upper two bits of the mode signal Sm is "10" and the mode is the third mode, as shown in FIG. 3C, the uppermost bits MSB to the sixth bit of the envelope data De are higher. The bit data becomes Dx, and the remaining 6 bits become lower bit data Dy.
[0031]
<1-7: Gain table>
Next, the gain table 5 will be described. FIG. 7 is a block diagram showing a detailed configuration of the gain table 5. As shown in this figure, the gain table 5 includes a read address generation circuit 51 and a RAM 52.
[0032]
First, the read address generation circuit 51 generates a 6-bit read address RA based on the upper bit data Dx of 4 to 6 bits and the mode signal Sm. Since the data interpolation circuit 6 described later performs linear interpolation based on two consecutive gain data Dg and lower bit data Dy, the read address generation circuit 51 performs two interpolations for one upper bit data Dx. Is generated. In the following description, the read address RA directly generated from the upper bit data Dx is referred to as a first read address RAx, and an address obtained by incrementing the read address RA by "1" is referred to as a second read address RAy. However, when the first read address RAx is the maximum value, the increment is not performed and RAx = RAy.
[0033]
The read address circuit 51 generates the first read address RAx according to the following procedure. First, the mode is specified based on the upper two bits of the mode signal Sm. Second, a predetermined number of bits are separated from the least significant bit of the mode signal Sm based on the specified mode. In the first mode, the lower two bits, in the second mode, the lower one bit, and in the third mode, no separation is performed. The first read address RAx is generated by combining the third separated bit and the upper bit data Dx. In the first mode, a first read address RAx is generated by combining the separated lower 2 bits and 4-bit upper bit data Dx, and in the second mode, the separated lower 1 bit and 5-bit upper bit data Dx are combined. To generate the first read address RAx, and in the third mode, the 6-bit upper bit data Dx is used as it is as the first read address RAx.
[0034]
Next, the RAM 52 is a dual-port type storage device in which one word is 32 bits and has a storage capacity of 64 words, and can simultaneously execute writing and reading of data. When the write enable signal WE is active, the RAM 52 can write to the RAM 52, and writes the gain data Dg to the storage area specified by the write address WA. Then, when the read enable signal RE is active, reading becomes possible. The gain data Dg and the signals WE, WA and RE are supplied from the control circuit 9. Therefore, the storage contents of the RAM 52 can be rewritten as needed. For example, when the data processing device is incorporated in a mixer and used, when the user operates the operating element, the parameters are changed as described above. Although the change is performed, the content stored in the RAM 52 can be updated in conjunction with the change.
[0035]
The RAM 52 stores gain data Dg in which one word is composed of 32 bits, and is read as needed. Since the number of bits of the envelope data De is 12 bits, the storage capacity of the RAM 52 originally requires 4096 words. However, in the present embodiment, since the interpolation process is performed using the data interpolation circuit 6 described later, the storage capacity is greatly reduced.
[0036]
Further, the storage area of the RAM 52 is divided and used according to the mode. FIG. 8 is a conceptual diagram showing the relationship between the mode and the division of the storage area. In the first mode, the storage area of the RAM 52 is divided into four every 16 words, and the first gain data Dga is stored in the storage area 52A (first page) as shown in FIG. The second gain data Dgb is written in the second page, the third gain data Dgc is written in the storage area 52C (third page), and the fourth gain data Dgd is written in the storage area 52D (fourth page). . Each of the first to fourth gain data Dga to Dgd is composed of 16 data. Since 64 words of gain data Dg are stored in the RAM 52, a 6-bit read address RA is required to specify and read certain gain data Dg. In the read address RA of the first mode, the upper two bits specify the page number, while the lower four bits specify the address in the page.
[0037]
Next, in the second mode, the storage area of the RAM 52 is divided into two as shown in FIG. 4B, the fifth gain data Dge is stored in the storage areas 52A and 52B, and the sixth gain data is stored in the storage areas 52C and 52D. Gain data Dgf is written. The fifth gain data Dge and the sixth gain data Dgf are each composed of 32 data. In the read address RA of the second mode, the upper one bit specifies the page number, while the lower five bits specify the address in the page.
Next, in the third mode, the storage area of the RAM 52 is not divided as shown in FIG. 9C, and the seventh gain data Dgg is written to the storage areas 52A to 52D. The seventh gain data Dgg is composed of 64 data.
[0038]
Here, the number of words of the first to seventh gain data Dga to Dgg is such that the first to fourth gain data Dga to Dgd are each 16 words, and the fifth and sixth gain data Dge and Dgf are each 32 words. And the seventh gain data Dgg is 64 words. That is, in the order of the first mode, the second mode, and the third mode, the accuracy of the gain characteristic to be provided is improved, while the number of processable music data is reduced.
[0039]
The accuracy of the gain characteristic to be given may be required to be high, or may not be required to be very accurate. In this example, the manner in which the storage area of the RAM 52 is divided according to the mode is changed. Therefore, when accuracy is not so much required, the number of divisions of the RAM 52 can be increased to store a plurality of types of gain data Dg. When accuracy is required, the number of divisions of the RAM 52 can be reduced to store gain data Dg having a large data capacity.
[0040]
In the above configuration, when giving the gain characteristic to the input data Din, first, the control circuit 9 generates the gain data Dg and the write address WA corresponding to the mode, and supplies them to the gain table 5. Then, the gain data Dg is written into a predetermined storage area of the RAM 52 according to the write address WA, and the gain data Dg is read as needed.
[0041]
<1-8: Data interpolation circuit>
Next, the data interpolation circuit 6 shown in FIG. 1 performs linear interpolation based on two consecutive gain data Dg and lower-order bit data Dy read from the gain table 5 to generate interpolation gain data Dg ′. .
For example, in the case of the first mode (the lower bit data Dy is 8 bits), the values of the two read gain data Dg are X (n) and X (n + 1), and the value of the lower bit data Dy is If Y and the value of the interpolation gain data Dg 'are G, the data interpolation circuit 6 calculates the following equation to generate the interpolation gain data Dg'.
G = X (n) + (X (n + 1) -X (n)). Y / 2^N
Here, N is the number of bits of the lower bit data Dy, and N = 8 (2^N= 256). Since N is determined according to the mode, the data interpolation circuit 6 sets N according to the data value of the mode signal Sm.
Since the data interpolation circuit 6 performs data interpolation of the gain data Dg, the storage capacity of the RAM 52 can be significantly reduced.
[0042]
<1-9: Inverse logarithmic conversion circuit and multiplication circuit>
Next, the inverse logarithmic conversion circuit 7 has a complementary relationship with the logarithmic conversion circuit, and converts 32-bit interpolation gain data Dg 'from logarithmic expression to linear expression to generate 32-bit linear gain data DG.
Next, the multiplication circuit 8 multiplies the input data Din by the linear gain data DG to generate output data Dout.
[0043]
<2. Operation of Embodiment>
Next, the operation of the data processing device will be described. First, when the mode is specified in the control circuit 9, the gain data Dg corresponding to the mode is written in the gain table 5. Here, assuming that the specified mode is the third mode, the waveform of each unit of the data processing device in the gain characteristic providing process is, for example, as shown in FIG. Note that, in this figure, the data values of the respective parts are represented by replacing them with the levels of analog signals.
[0044]
When the input data Din (shown as an analog signal) shown in FIG. 7A is supplied to the absolute value generation circuit 1, the absolute value generation circuit 1 generates the absolute value data Dz shown in FIG. As a result, double-wave rectification is performed in an analog manner.
Thereafter, when the peak hold / time attenuating circuit 3 generates the envelope data De shown in FIG. 3C based on the absolute value data Dz, the data separating circuit 4 converts the envelope data De into the upper bit data Dx and the lower bit data Dx. Dy. Since the mode type in this example is the third mode, the number of bits of both the upper bit data Dx and the lower bit data Dy is 6 bits.
In this case, the read address generation circuit 51 first generates the upper bit data Dx as the first read address RAx during one unit time (1/256 fs) of the envelope data De, and then sets the upper bit data Dx to “ The data incremented by 1 "is generated as the second read address RAy. As a result, two pieces of gain data Dg are read from the RAM 52. FIG. 6D shows the gain data Dg that is read first.
[0045]
Thereafter, when the data interpolation circuit 6 performs an interpolation process based on the two pieces of gain data Dg and the lower bit data Dy to generate interpolation gain data Dg ′, the inverse logarithmic conversion circuit 7 converts the interpolation gain data Dg ′ into linear data. This is converted into an expression to generate linear gain data DG. Then, by multiplying the linear gain data DG by the input data Din in the multiplication circuit 8, a gain characteristic is given to the input data Din, and the output data Dout shown in FIG.
[0046]
FIG. 10 is a timing chart showing the operation of each unit of the data processing device. In this figure, the operation delay time of each unit is ignored. When 256 pieces of music data D1 to D256 are supplied to the data processing device as input data Din during a certain sampling period as shown in FIG. 7A, the peak hold / time attenuating circuit 3 sets each of the music data D1 to D256. Each of the envelope data De1 to De256 is generated as shown in FIG.
[0047]
Next, the data separation circuit 4 extracts predetermined bits from the most significant bits of each of the envelope data De1 to De256 according to the number of bits determined according to the mode type indicated by the mode signal Sm, and FIG. ) Are generated as upper bit data Dx1 to Dx256. For example, when the data value of the upper 2 bits of the mode signal Sm is “00” and indicates the first mode, the upper 4 bits are extracted and the upper bit data Dx1 to Dx256 are generated. When the data value of the upper 2 bits of the mode signal Sm is “01” and the second mode is indicated, the data value of the upper 5 bits of the mode signal Sm is “10” and the data value of the upper 2 bits of the mode signal Sm is “10”. When designating the third mode, the upper 6 bits are extracted. The upper bit data Dx1 to Dx256 extracted in this way correspond to the in-page address in each page of the RAM 52. In other words, the number of upper bits extracted from the envelope data De1 to De256 is determined according to the mode.
[0048]
Next, the read address generation circuit 51 extracts the lower bits of the mode signal Sm for each cycle of the reference clock signal CKref and generates the page addresses PA1 to PA256, as shown in FIG. Each of the page addresses PA1 to PA256 is an address indicating the type of the storage area 52A to 52D. For example, the period is the first mode, and the lower two bits of the mode signal Sm are “00” in the period T1, “01” in the period T2, “10” in the period T3, and “11” in the period T4. , The first page (storage area 52A) in the period T1, the second page (storage area 52B) in the period T2, the third page (storage area 52C) in the period T3, and the fourth page (storage area) in the period T4. The area 52D) will be designated.
Also, the period is the second mode, and if the lower two bits of the mode signal Sm change such as “00” in the periods T1 and T2 and “01” in the periods T3 and T4, the periods T1 and T2 Specifies the first page (storage areas 52A and 52B) and the second page (storage areas 52C and 52D) during periods T3 and T4.
Furthermore, if the third mode is performed during the period, the lower two bits of the mode signal Sm are uniquely “00”. In this case, since the storage areas 52A to 52D are handled as one page, the page addresses PA1 to PA256 are not generated.
[0049]
Next, the read address generation circuit 51 generates the first read addresses RAx1 to RAx256 by combining the page addresses PA1 to PA256 and the upper bit data Dx1 to Dx256, respectively.
For example, in the first mode, assuming that the page address PA3 in the period T3 is "10" and the upper bit data Dx3 is "0000", the first read address RAx becomes "100000". As a result, the data stored at the top of the third page (storage area 52C) in the first mode is specified. In the first mode, since the RAM 52 can be divided into four and different types of gain data Dg can be stored in each page, there is an advantage that a plurality of types of gain characteristics can be provided.
[0050]
In the second mode, if the page address PA4 in the period T4 is “1” and the upper bit data Dx4 is “10000”, the first read address RAx becomes “110000”. As a result, the data stored at the beginning of the second half of the second page (storage area 52D) in the second mode is specified. In the second mode, the number of divisions of the RAM 52 is two, and the type of the gain data Dg is smaller than in the first mode in which the number of divisions is four. However, the number of words per page is 32, and it is possible to improve the gain accuracy compared to the first mode of 16 words per page.
[0051]
Furthermore, in the third mode, if the upper bit data Dx1 in the period T1 is “000000”, the first read address RAx becomes “000000”. Thereby, the data stored at the head of the storage area 52A is specified. In the third mode, since the RAM 52 is not divided and used, the read address generating circuit 51 uses the 6-bit upper bit data Dx as it is as the first read address RAx. In the third mode, only a single gain characteristic can be provided, but since 64 words can be used per page, the gain accuracy can be further improved.
[0052]
Next, the address generation circuit 51 generates the second read addresses RAy1 to RAy256 by incrementing the first read addresses RAx1 to RAx256 by “1”. The generation timings of RAx and RAy are, as shown in FIG. 4E, first, the first read addresses RAx1 to RAx256 are generated while the reference clock signal CKref is at the H level, and then the reference clock signal CKref is generated. Are at the L level, the second read addresses RAy1 to RAy256 are generated.
[0053]
When the first and second read addresses RAx and RAy are supplied to the RAM 52, two sets of gain data Dgx1, Dgy1 to Dgx256 and Dgy256 are read from the RAM 52 as shown in FIG.
Thereafter, the data interpolation circuit 6 performs an interpolation process based on the two gain data Dgx1, Dgy1 to Dgx256, Dgy256 and the lower bit data Dy1 to Dy256 shown in FIG. Interpolation gain data Dg1 ′ to Dg256 ′ shown in FIG. Then, based on these results, the multiplying circuit 8 gives a gain characteristic to the input data Din, thereby generating output data Dout1 to Dout256 shown in FIG.
[0054]
As described above, in the present embodiment, the RAM 52 is appropriately divided according to the mode to store the gain data Dg having different precisions, while separating the upper bits determined according to the mode from the envelope data De, and A read address RA for accessing the RAM 52 is generated based on the read address RA. Therefore, according to this data processing device, when the accuracy of the gain characteristic to be provided may be low, the type of the gain data Dg can be increased, and the gain characteristic can be provided with high accuracy as needed. . As a result, the versatility of the data processing device can be improved.
[0055]
Furthermore, since the interpolation processing is performed based on the gain data Dg and the lower-order bit data Dy, the storage capacity of the RAM 52 can be reduced. In addition, since the number of data bits is reduced by using the logarithmic conversion circuit 2 and the logarithmic inverse conversion circuit 7, the storage capacity of the RAM 52 can be reduced and the operation time of the data interpolation circuit 6 can be reduced.
[0056]
<3. Modification>
The embodiment according to the present invention has been described above, but the present invention is not limited to the above-described embodiment, and various modifications described below are possible.
(1) In the above-described embodiment, the gain characteristic is controlled based on the envelope data De generated from the input data Din. However, the present invention is not limited to this. It goes without saying that gain control may be performed based on the generated envelope data De.
[0057]
(2) In the above-described embodiment, music data is assumed as the input data Din. However, the present invention is not limited to this, and is a data processing device that applies various effects such as wipe and chroma key to image data. You may.
[0058]
(3) In the above-described embodiment, the storage area of the RAM 52 is divided equally. However, the present invention is not limited to this, and may be divided unequally. For example, as shown in FIG. 11A, the first gain data Dga and the second gain data Dgb of 16 words are stored in the storage areas 52A and 52B, and the fifth gain data Dge of 32 words are stored in the storage areas 52C and 52D. You may make it memorize | store. Also, as shown in FIG. 3B, a 128-word RAM 52 'is used instead of the RAM 52, and the same gain data Dg as the RAM 52 is stored in the storage areas 52A to 52D, while the storage areas 52E to 52H are stored in the storage areas 52E to 52H. The seventh gain data Dgg of 64 words may be stored.
In short, the storage area of the RAM 52 is divided according to the processing mode, and the desired gain data is stored in advance in each storage area, while the higher-order bits are converted from the envelope data De according to the processing mode converted as necessary. Any configuration may be used as long as the data Dx is generated and the read address RA is generated by performing processing according to the mode on the upper bit data Dx.
[0059]
Further, the contents stored in the RAM 52 may be updated during the processing of the input data Din. For example, when the first mode is designated during a certain period, and the first to fourth pages are sequentially designated and repeated for each of the data D1 to D256 constituting the input data Din, the first mode is designated during the period. In order to sequentially use the gain data Dga to the fourth gain data Dgd, the first gain data Dga to the fourth gain data Dgd are stored in each page (storage areas 52A to 52D) as shown in FIG. Although it is necessary, in the next sampling period, the first mode is specified in the first half of the sampling period, the first gain data Dga and the second gain data Dgb are used, and the second mode is specified in the second half period. When the gain data Dge is used, the contents stored in the RAM 52 may be updated as shown in FIG. In this case, when one cycle of the reference clock CKref is set to one unit time t, the first half period Ta and the second half period Tb are configured by 128 unit times 128t. Since data is not read from the storage areas 52C and 52D in the first half period Ta, the storage contents of the storage areas 52C and 52D of the RAM 52 are stored in the third gain data Dgc using the 32 unit time 32t of the first half period Ta. And the fourth gain data Dgd is rewritten to the fifth gain data Dge. This makes it possible to use the fifth gain data Dge at the start of the second half period Tb.
[0060]
Therefore, according to the present invention, the gain data Dg stored in the RAM 52 can be rewritten while the input data Din is being continuously processed. As a result, it is possible to efficiently use the small storage capacity of the RAM 52 and use various types of gain data having different precisions and types, so that the versatility of the data processing device can be further enhanced.
In addition, if the gain data Dg is not updated during a period in which the input data Din is being continuously processed, it is not necessary to use a dual-port RAM as the RAM 52 and a single-port RAM may be used. Of course.
[0061]
【The invention's effect】
As described above, according to the present invention, the storage area of the storage unit is divided according to the processing mode, and while the gain data is stored in each storage area, the upper bits of the control data are separated. Since the storage unit is accessed based on the above, the storage area can be utilized without waste, and the versatility of the data processing device can be greatly improved.
[Brief description of the drawings]
FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention.
FIG. 2 is a timing chart showing an example of a relationship between input data and a mode signal in the device.
FIG. 3 is a block diagram showing a main configuration of a control circuit in the device.
FIG. 4 is a block diagram illustrating a configuration example of an absolute value generation circuit in the device.
FIG. 5 is a block diagram showing a specific configuration example of a peak hold / time attenuating circuit in the device.
FIG. 6 is a diagram showing an example of a separation mode according to a mode in a data separation circuit of the same device.
FIG. 7 is a block diagram showing a detailed configuration of a gain table of the device.
FIG. 8 is a conceptual diagram showing the relationship between modes and storage area division in the same table.
FIG. 9 is a waveform chart showing the overall operation of the device.
FIG. 10 is a timing chart showing the operation of each unit of the apparatus.
FIG. 11 is a conceptual diagram showing how a storage area is divided in a RAM according to a modification.
FIG. 12 is a timing chart showing an operation of updating stored contents in a RAM according to a modified example.
FIG. 13 is a characteristic diagram showing an example of input / output characteristics in the case of having a non-linear gain characteristic.
FIG. 14 is a characteristic diagram showing gain characteristics for obtaining the same input / output characteristics.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Absolute value generation circuit, 2 ... Log conversion circuit, 3 ... Peak hold / time attenuation circuit, 4 ... Data separation circuit (data separation part), 5 ... Gain table, 51 ... Read address generation circuit (Read address generation part) , 52 RAM (storage section), 6 data interpolation circuit (data generation section, interpolation section), 8 multiplication circuit (data generation section, multiplication section), 9 control circuit, Sm mode signal, RA read address , De: envelope data (control data), Din: input data, Dx: upper bit data, Dy: lower bit data, Dg: gain data, Dg ': interpolation gain data, Dout: output data.

Claims (6)

In a data processing device that gives various gain characteristics to input data,
According to the number of separation bits determined according to the processing mode indicating the accuracy of the gain characteristic to be provided, a data separation unit that separates higher-order bit data from control data obtained by performing predetermined processing on the input data,
A storage unit that stores in advance each gain data in each of the divided storage areas according to the processing mode,
A read address generation unit that performs a process according to the processing mode on the upper bit data to generate a read address;
A data processing device, comprising: a data generation unit that performs a gain process on the input data based on the gain data read from the storage unit based on the read address to generate output data. 2. The data processing apparatus according to claim 1, further comprising: an amplitude data generating unit configured to detect an amplitude of an input signal based on the input data and generate amplitude data, wherein the amplitude data is provided as the control data. . 3. The data processing apparatus according to claim 1, wherein each of the gain data indicates a different gain characteristic. The data separation unit separates the control data into the upper bit data and the lower bit data,
The data generation unit includes:
An interpolation unit that performs an interpolation process on the gain data read from the storage unit based on the lower-order bit data to generate interpolation gain data,
The data processing device according to claim 1, further comprising a multiplication unit configured to generate the output data by multiplying the interpolation gain data by the input data. 2. The read address generation unit according to claim 1, wherein an address designating each storage area is generated according to the processing mode, and the read address is generated by combining the address and the upper bit data. 3. The data processing device according to 2. Based on the gain data stored in the rewritable storage unit, in the data processing method of giving various gain characteristics to the input data,
Dividing the storage area of the storage unit according to the processing mode indicating the accuracy of the gain characteristic to be given, storing each gain data in each divided storage area,
According to the number of separation bits determined according to the processing mode, upper bit data is separated from the control data,
Performing a process according to the processing mode on the upper bit data to generate a read address;
A data processing method comprising: performing gain processing on the input data based on gain data read from the storage unit based on the read address to generate output data.

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