JP2002270620A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a silicon carbide(SiC) field effect transistor in which the influence of stacking fault upon a device is avoided. SOLUTION: The field effect transistor is formed on an SiC single-crystal substrate. A gate electrode of the transistor is arranged in the clockwise direction or the counterclockwise direction of at least 45 deg. and at most 135 deg., with respect to the direction of the stacking fault existing in the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a silicon carbide (Si)
C) The present invention relates to a field-effect transistor formed on a conductive layer formed on a single crystal substrate by epitaxial growth or ion implantation.

[0002]

2. Description of the Related Art Silicon carbide (SiC) has attracted attention as an environment-resistant semiconductor material because it has excellent heat resistance and mechanical strength and is physically and chemically stable. In recent years, demand for SiC single crystal wafers as substrate wafers for high-frequency high-voltage electronic devices and the like has been increasing.

When a power device, a high-frequency device, or the like is manufactured using a SiC single crystal wafer, a SiC thin film is usually epitaxially grown on the wafer by using a method called thermal CVD (thermal chemical vapor deposition). Generally, a dopant is directly implanted by an ion implantation method.

At this time, the plane orientation of the SiC wafer is as follows:
Usually, a (0001) plane or a (000-1) plane is used. On these planes, threading dislocations called micropipes are present at about 50 to 100 / cm ² , and not only in the ion implantation method but also in the epitaxial growth. , The micropipe is taken over as it is.

[0005] Devices fabricated on micropipes are known to have degraded characteristics (eg, T.S.
Kimoto et al. , IEEE Tran
s. Electron. Devices 46 (3)
pp. 471-474, 1999), and reduction of micropipes is urgently required.

[0006] On the other hand, Takahashi et al.
Si grown in <00> direction or <11-20> direction
This indicates that there is no micropipe in the C single crystal (J. Takahashi et al.,
J. Cryst. Growth 135, 199
4) Furthermore, Yano et al. Used an epitaxial thin film grown on a wafer having a (11-20) plane to form a MOS.
A device was prototyped, and in the case of 4H-SiC, the conventional (00
01) shows that the electron mobility is about 20 times as large as that using the (H. Yano et. Al., M.
ater. Sci. Forum 338-342,
2000) and the like, attention has been paid to epitaxial thin films grown on wafers having a (11-20) plane.

However, in the case of 6H-SiC, <1
(1-100) of SiC crystal grown in −100> direction
About 1000 times of the (000-1) plane, <11
Even in the (11-20) plane of the SiC crystal grown in the −20> direction, there is a defect called a stacking fault that is about 100 times larger. Similarly, there are stacking faults. Even if epitaxial growth is performed on such a wafer, stacking faults are considered to be inherited, and there is a concern that devices formed on these surfaces may be adversely affected.

The results of the above-mentioned Yano et al. Were obtained by using a (11-20) plane wafer obtained by cutting a so-called longitudinally parallel SiC single crystal grown in the c-axis direction. Does not need to consider the influence of the stacking fault because there is almost no stacking fault in the wafer. However, a large diameter (1-100) plane or (11-2)
In order to obtain a wafer having a 0) plane, it is necessary to grow SiC in the c-axis direction and make it thicker than the same length as its diameter, which is technically difficult.

Therefore, the (1-100) plane or (11)
-20) As a seed crystal, a wafer having a projected surface is defined as <1-1.
It is realistic to grow a single crystal by growing the diameter in the <00> direction or the <11-20> direction, and to prepare a wafer from this, but in this case, as described above, the problem of stacking faults occurs. Is inevitable.

Therefore, (1-1) of the SiC wafer grown in the <1-100> direction or the <11-20> direction
On the (00) plane or the (11-20) plane, and further on the plane on which those planes are epitaxially grown, there is no micropipe, the electron mobility of the MOS is also improved, and both the yield and the device characteristics are improved. Although an effective method, a new problem has arisen as to whether the effects of stacking faults on the device can be avoided.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to a Si device which avoids the effects of stacking faults on the device which is the above problem.
It is an object to provide a C field effect transistor.

[0012]

According to the present invention, there is provided a method for manufacturing a computer comprising:
When a device is formed on the (1-100) plane or the (11-20) plane of the SiC crystal grown in the> direction or the <11-20> direction, and further on the plane epitaxially grown on those planes, It has been found that the above problem can be solved by limiting the direction in which the current flows within, and the present invention has been completed.

That is, the present invention provides (1) a transistor formed on a silicon carbide single crystal substrate, wherein the gate electrode of the transistor is clockwise or counterclockwise with respect to the direction of stacking faults present in the substrate. More than 45 ° clockwise 13
(2) The field effect transistor according to (1), wherein the silicon carbide single crystal has a (11-20) plane orientation. ) The plane orientation of the silicon carbide single crystal is (1-
(1) the field-effect transistor according to (1),
It is.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the effect of stacking faults on device operation will be described.

It is considered that stacking faults existing in the SiC wafer become linear traps. When electrons are trapped therein, a depletion layer is formed around the stack to increase the potential, and the flow of electrons, that is, the current flow It is thought to be a barrier.

When a device is formed on a substrate having such a trap, a current in a direction crossing stacking faults is difficult to flow due to the influence of this potential, and a current smaller than a set value necessary for device operation is obtained. I ca n’t
It is expected that the device will not operate sufficiently. Therefore, in the present invention, it has been determined that the influence of the stacking fault can be avoided by reducing the frequency of the current crossing the stacking fault.

In the case of a field effect transistor, if the direction of the gate electrode is parallel to the direction of the stacking fault, the current between the source and the drain crosses the stacking fault vertically and becomes most susceptible to the influence. Is required to be within a certain angle range with respect to the direction of the stacking fault.

When electrons flowing between the source and the drain cross this defect a plurality of times, it is considered that energy is exponentially lost, that is, it is difficult for current to flow rapidly. Can be considered.

It has been confirmed from the measurement that the stacking fault density is about one at an interval of 3 to 4 μm. In a normal device structure, since the source-drain interval is about 5 μm, it flows between the source and the drain. In order for an electron to cross a stacking fault only once, assuming that the angle between the stacking fault direction and the current direction is θ, θ = sin ⁻¹ ((3-4) / 5),
That is, if the angle is smaller than about 45 °, the number of times of crossing the stacking fault becomes approximately 1 or less. this is,
When viewed from one direction with respect to the direction of the gate electrode, the angle with the stacking fault direction is required to be 45 ° or more, and is 135 ° or less from the opposite direction.

The optimum value is a state where the current does not cross the stacking fault, that is, the direction of the gate electrode and the stacking fault direction are 90 °. Specifically, in the present invention, <1-10
SiC grown in <0> direction or <11-20> direction
When forming a field-effect transistor on the (1-100) plane or the (11-20) plane of the crystal, or on the plane epitaxially grown on those planes, <1-10
The gate electrode is formed in a direction from 45 ° to 135 ° clockwise or counterclockwise from the 0> direction or the <11-20> direction.

This is because when a crystal is grown in the <1-100> direction or the <11-20> direction, stacking faults are unavoidable, unlike the vertical cutting of the crystal grown in the c-axis direction. Grown in the <1-100> direction (1-100)
This is because stacking faults exist in the <11-20> direction on the plane and in the <1-100> direction on the (11-20) plane grown in the <11-20> direction.

Actually, when the gate electrode is formed in the above-described direction, the same characteristics as those of the device on the (0001) plane which is usually manufactured are obtained. It was confirmed that device characteristics were obtained.

<1-100> direction or <11-20>
(1-100) plane or (1)
The 1-20) plane is easier to increase in diameter than the vertical cutting of a crystal grown in the c-axis direction, so that the cost of the wafer can be reduced, and the point of the present invention is also significant in that respect.

[0024]

(Embodiment) FIG. 1 shows a SiC grown in the <11-20> direction to form a field-effect transistor.
It is sectional drawing of the board | substrate which performed epitaxial growth on the (11-20) plane of a single crystal wafer.

Reference numeral 1 denotes an SiC wafer, and 2 denotes an epitaxially grown SiC buffer layer, which does not transmit the influence of substrate roughness, strain and the like upward. Reference numeral 3 denotes an epitaxially grown SiC active layer. In this example, nitrogen is doped, and a current flows.

A procedure for forming a field effect transistor using such a substrate will be described with reference to FIG.

First, as shown in FIG. 2A, a region where a device is to be formed is covered with a photoresist 4, and other portions are etched to a buffer layer by a method such as reactive ion etching.

Next, as shown in FIG. 2B, a pattern for the source electrode 5 and the drain electrode 6 is formed by a method such as photolithography, and the electrodes are formed by a method such as metal deposition and lift-off.

Next, as shown in FIG. 2C, the gate electrode 7 is formed in the same manner as in FIG. 2B, and the field effect transistor is completed.

In this example, in FIG. 2C, the direction perpendicular to the plane of the drawing is the direction of the gate.
1-100> clockwise or counterclockwise 4
It must be between 5 ° and 135 °. This is because the direction of the stacking fault is confirmed in advance, and FIG.
At the time of (a), the pattern may be formed such that the direction in which the gate should enter is as described above.

FIG. 3 shows an example of the drain voltage-drain current characteristics of the field-effect transistor prepared as described above when the gate electrode direction is 90 ° from the <1-100> direction.

The characteristics are similar to those of a field-effect transistor formed on a normal (0001) plane, and the pinch-off characteristics are good.

In this embodiment, the (11-20) plane of the SiC crystal grown in the <11-20> direction has been described, but the SiC crystal grown in the <1-100> direction has been described.
The same applies to the (1-100) plane of the crystal.

(Comparative Example) As a comparative example, when the direction in which current flows is not taken into consideration, for example, the same epitaxial substrate as that of the embodiment is used, and the gate direction is <1-100>. FIG. 4 shows the drain voltage-drain current characteristics.

First, it can be seen that the absolute value of the current is smaller by about two digits than in the embodiment. Further, it does not show good pinch-off characteristics, and it is determined that the normal flow of current is hindered by the influence of the electron trap caused by the stacking fault described above.

The present invention is applicable not only to the metal-semiconductor field effect transistor (MESFET) as in the embodiment but also to the metal-oxide-semiconductor field effect transistor (MESFET).
Obviously, it can be applied to OSFETs) and junction transistors (JFETs).

[0037]

As described above, according to the present invention, the (1-100) plane or the (11-100) plane of the SiC crystal grown in the <1-100> or <11-20> direction.
On the (-20) plane, and on those planes on which epitaxial growth has been performed, an electronic device or the like having excellent electrical characteristics can be manufactured.

Since there are no micropipes on these surfaces, the production yield can be increased. further,
The (1-100) plane or (11-20) plane of the crystal grown in the <1-100> or <11-20> direction can be made larger in diameter than the longitudinally cut crystal grown in the c-axis direction. This also has the effect of reducing the cost of the wafer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an epitaxial growth substrate to which the present invention is applied.

FIG. 2 is a process flow diagram of a field effect transistor formed according to the present invention.

FIG. 3 is a diagram showing drain voltage-drain current characteristics of a field effect transistor formed according to the present invention.

FIG. 4 is a diagram showing drain voltage-drain current characteristics of a field effect transistor formed by a conventional method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 SiC wafer 2 SiC buffer layer epitaxially grown 3 SiC active layer epitaxially grown 4 Photoresist 5 Source electrode 6 Drain electrode 7 Gate electrode

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hirokatsu Yashiro 20-1 Shintomi, Futtsu-shi, Chiba Nippon Steel Corporation Technology Development Division (72) Inventor Tatsuo Fujimoto 20-1 Shintomi, Futtsu-shi, Chiba New Japan (72) Inventor Masakazu Katsuno 20-1 Shintomi, Futtsu-shi, Chiba F-term 5F102 GB01 GC01 GD01 GD04 GD10 GJ02 GK02 GL02 GR01 GT01 HC11 HC19 5F140 AA29 BA02 BA16 BA20 BB15 BF41

Claims (3)

[Claims] 1. A transistor formed on a silicon carbide single crystal substrate, wherein a gate electrode of the transistor is rotated clockwise or counterclockwise by 45 ° with respect to a direction of a stacking fault existing in the substrate. A field-effect transistor, wherein the field-effect transistor is arranged in a direction not less than 135 ° or less. 2. The silicon carbide single crystal has a plane orientation of (11-
20. The field effect transistor according to claim 1, which is a (20) plane. 3. The silicon carbide single crystal has a plane orientation of (1-1).
2. The field effect transistor according to claim 1, which is a (00) plane.